JPH0719246B2 - Digital signal processor - Google Patents

Description

The present invention relates to a digital signal processing device and a signal processing method for processing time-series input data based on a predetermined algorithm and outputting it as time-series data. Regarding

(B) Conventional Technology In general, primitive information sources existing around us, such as voices and images, are often analog signals. A system that processes this analog signal by a digital method is a digital signal processing device (digital signal processing system: DSP system).

In recent years, digital circuits are rapidly becoming LSIs, and DSP systems can be easily realized on a single chip. Furthermore, high-accuracy processing is possible compared to analog signal processing, and arbitrary characteristics are stabilized by setting parameters. Since it has the characteristics that it can be uniformly obtained and adjustment can be made, DSP
The system came into practical use rapidly. Also, DS
The application range of the P system is broadly used for voice signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, underwater acoustic signal processing, and the like.

Also in the audio field, a DS (digital compact disc) player or a DAT (digital audio tape) player, which processes audio signals digitally as digital processing of audio signals progresses.
P system has been put to practical use.

A conventional DSP system has an architecture shown in FIG. 12 so that a digital filter can be easily formed.

In FIG. 12, the data bus (1) has an input / output circuit (I / O) (2), a data RAM (3), a multiplier (4), an arithmetic circuit (ALU) (5), and an accumulator ( ACC) (6) etc. are connected, output of data RAM (3) and data ROM (7)
Is connected to the multiplier (4), and the multiplication result output of the multiplier (4) is applied to one input of the ALU (5).
Each of these circuits is controlled by a microcode signal output from a decoder (9) that decodes the instructions sequentially read from the program ROM (8) in response to the instructions.

In the realization of a digital filter, the multiply-accumulate operation of the form Y = A.Xi + B.Xi _{- 1} + CXi- ₂ appears repeatedly. When this digital filter is realized by a DSP system, the calculation order of the nodes in the filter is determined, a program is created, the program is stored in the program ROM (8), and the calculation is performed in the data ROM (7). Stores the constant of the expression. Then, by executing the program, the sum of products operation is performed, and the operation result is sequentially stored in the data RAM (3).

(C) Problems to be solved by the invention When the DSP system shown in FIG. 12 is used in the audio field, it is necessary for audio such as graphic equalizer function, bass treble, loudness, low boost function, and surround effect function. Although the function can be realized, since there are left and right two-channel signals in the audio signal, the processing for realizing the above-mentioned function must be applied to the left and right channel signals, respectively. In order to change the characteristics of the left and right channels independently, different constants must be written in the data ROM.

Therefore, in a CD player or DAT player, the signal sampling cycle has a high frequency such as 44.1 KHz or 48 KHz. Therefore, all the processing for realizing the above-mentioned function is performed on the left and right channels during the sampling cycle. You have to finish each one. Therefore, depending on the processing speed of the DSP system, it may not be possible to realize any of the functions described above. That is, there is a drawback that the throughput of the DSP system deteriorates.

(D) Means for Solving the Problems The present invention has been created in view of the above points,
A pair of data buses for transferring digital data,
A pair of digital processing means each connected to the data bus, a control means for simultaneously controlling the operation of the pair of digital processing means according to a pre-programmed procedure, and sending address data to an externally connected storage device, External memory interface means for transmitting and receiving digital data and digital data applied from the outside are input based on a control signal applied from the outside, and the plurality of input digital data are input in a predetermined order. Interface means for transferring to the pair of data buses and outputting processed data sent to the pair of data buses to the outside, and a pair of digital processing means for digital data sent from the interface means to the pair of data buses Storage control register means for controlling whether or not to store inside Digital data exchange means for exchanging digital data of each other between a pair of data buses and data sent to one or both of the pair of data buses are set, and conditional branch control for controlling a jump condition based on the data. The digital processing means further creates address data for circulating and accessing a specific memory area of an externally connected storage device, and coefficient for multiplying input digital data. Storage means for storing constants “1”, “a”, “b” for setting, coefficients for configuring a digital filter, digital data before and during processing, a multiplication means and a calculation means, Further, the control circuit has a program memory unit for storing a program and a program counter unit for designating an address of the program memory unit. A decoder means for decoding an instruction read from the program memory means, a jump address means connected to one or both of the pair of data buses for setting jump destination address data, and the jump address means. Multiplexer means for selectively applying the jump destination address set to the program counter means to the program counter means, and a loop counter connected to one or both of the pair of data buses to set the number of times of execution of the same instruction. The purpose is to achieve many functions efficiently within a specified period.

(E) Operation In the above-mentioned means, when the specific memory area of the externally connected storage device is cyclically accessed through the external memory interface means, the address data is read from the storage means of the digital processing means and incremented by the arithmetic means. Alternatively, the operation of decrementing, outputting the result when the result is not the boundary of the specific memory area, and outputting the predetermined value stored in the storage means when the boundary is the boundary of the specific memory area is performed by a single instruction, The output address data is transferred to the storage means again, and at the same time, the start address of the specific memory area is added to the address data to create real address data, which is sent to the external memory interface means. Easy to access.

Further, when an overflow occurs during the processing of the digital data input from the outside by the digital processing means, a constant "1" stored in the storage means for adjusting the coefficient by which the digital data input next is adjusted. , "A", "b"
By selecting (a <1, b <1) and multiplying the coefficient at that time, the level of the input digital data is adjusted to a size at which overflow does not occur.

In addition, when data is externally written to the storage means in the digital processing means, the composite data of the digital data to be written, a value indicating the number of the data, a write destination address, and data indicating one of the pair of digital processing means is written. When applied to the interface means and held, the composite data is first taken out from the interface means, and each data is set in the loop counter means of the control means, the address designating means for designating the address of the storage means and the storage control register means. The number of data to be written based on these is taken out from the interface means and written in the storage means, so that data transfer from the outside becomes easy.

Further, the digital data exchange means makes it possible to exchange the digital data sent to the pair of data buses or the internal data of the pair of digital processing means with each other by executing one command.

Further, by setting the jump destination address data from the outside to the jump address register means provided in the control means through the interface means, the program counter means can be configured to execute the jump address register means of the jump address register means at the time of executing the Jap instruction or the conditional branch instruction. Since the address data is transferred, the flow of the program can be controlled externally.

Further, the data set in the condition setting register means in the conditional branch control means selects the output of the flag means connected to each digital processing means, and one digital processing means for generating the jump control signal. Or only the condition of the other digital processing means is satisfied,
Alternatively, when the condition of either one of the digital processing means is satisfied, or when the condition of both digital processing means is satisfied, it can be selected by a program or data from the outside.

With the above operation, the function is improved and the operation efficiency is improved, and the throughput of the digital signal processing device is improved.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, in which a pair of data buses (BUS1) (BUS2) (11) and the data buses (BUS1) (BUS2) (11) are provided. Connected digital processing circuits (12) (13) as well as data bus (BUS1) (BUS2)
A data input / output circuit (14) connected to (11), an interface circuit (15), an external memory interface circuit (16), a data exchange register (17), and a data bus (BU).
Audio including a storage control register (18) connected to S2), a conditional branch control circuit (19), and a control circuit (20) connected to the data bus (BUS2) and controlling the operation of each circuit. This is a DSP system for signal processing.
The system is integrated on a one-chip semiconductor device.

The data bus (11) is composed of 24 bits of 8 bits × 3. The data input / output circuit (14) receives 16-bit left-channel and right-channel sampling data (for example, digital data sampled at a sampling frequency of 44.1 KHz in the case of a CD player) externally applied to the input terminal IN. Serially input, the data of the right channel is sent to the data bus BUS1, the data of the left channel is sent to the data bus BUS2, and the processed right channel data sent to the data bus BUS1 and the data bus BUS2 are sent. The processed left channel data is received and serially output alternately from the output terminal OUT.

The data processing circuit (12) is for right-channel data processing, and the data processing circuit (13) is for left-channel data processing. That is, the data processing circuits (12) (13) are composed of a data RAM (21) and a constant RAM (2
2), constant ROM (23), address pointer (24) (25)
(26), multiplier (MUL) (27), ALU (28), accumulator (ACC) (29), temporary registers (TMP1 to T
It has MP8) (30). The data RAM (21) has a capacity of 24 bits × 128 for storing the data before processing transmitted from the data input / output circuit (14) and the data after the arithmetic processing, and has a data bus (11) and multiplication. Connected to the input of the container (27). The constant RAM (22) is a coefficient of the digital filter sent from the interface circuit (15), and
It has a capacity of 16 bits × 256 for storing address data and the like of an external memory device (not shown) connected through the external memory interface circuit (16), and has a data bus (1
1), the input of the multiplier (27), and the input of the ALU (28). Further, the constant ROM (23) is for creating a coefficient for multiplying the head address data of the specific memory area set in the external memory device, the address width and the digital data sent from the data input / output circuit (14). Constants "1", "a" (eg a = 0.99), "b" (eg b
= 1.01) and the maximum and minimum values that are set when the multiplication or calculation result overflows
It is a read-only memory of 256 bits and is connected to the input of the data bus (11) and the multiplier (27).

The address pointer (24) consists of 8 bits
A function for addressing the RAM (21), which is controlled by the microcode INC1 and DEC1 output from the control circuit (20) and increments (+1) and decrements (-1) the held address data. , And a circulating address function of circulating between address data “0” and a set value. The address pointer (25) is a 10-bit pointer that specifies the address of the constant RAM (22), and is controlled by the microcode INC2 output from the control circuit (20). It has the function of being cleared to "0" by the microcode CLEAR2 output from the circuit (20). Furthermore, the address pointer (26) is a constant ROM (23)
Is an 8-bit pointer that designates the address of the address, and has the function of decrementing the address data by the microcode DEC3 output from the control circuit (20).

The multiplier (27) performs multiplication of 24 bits × 16 bits, the A input is 24 bits and the B input is 16 bits, and the multiplication result is determined after one cycle. Furthermore,
The input selection circuit MPXA is used for the A and B inputs of the multiplier (27).
And MPXB are provided, and the input selection circuit MPXA is connected to the control circuit (2
Data bus (1 by microcode A-BUS from 0)
Select 1) and use microcode A-DRAM to data RAM
(21) is selected and applied to the A input, and the input selection circuit MPXB
Selects the data bus (11) with the microcode B-BUS and the constant RAM (22) with the microcode B-CRAM.
, And select the constant ROM (2
Select 3) and apply to the B input. The multiplication result is output in 32 bits.

The ALU (28) is a 32-bit arithmetic circuit. The 32-bit multiplication result input to one side and the 32-bit arithmetic result input to the other side.
The data of ACC (29) is added by the microcode ADD and the result is transferred to ACC (29). ACC (29)
Of the 32 bits, the upper 24 bits are connected to the data bus (11), and the lower 8 bits are connected to the lower 8 bits of the temporary register (30) by the auxiliary bus (31). The temporary register (30) is composed of 32-bit registers TMP1, TMP2 ... TMP8, and holds up to eight 32-bit data. The upper 24 bits of each are connected to the data bus (11). . Temporary register (30) by data bus (11) and auxiliary bus (31)
32-bit data is transferred between ACC and ACC (29).

The control circuit (20) controls each circuit according to a pre-programmed procedure, and its configuration is, as shown in FIG. 2, a program ROM (32) for storing a program including a combination of instruction codes and a program ROM (32). , Program R
Program counter (P that specifies the address of OM (32)
C) (33) and instruction decoder (I-DEC) (34) that decodes the instruction read from the program ROM (32) and outputs various control signals, and increments the address data of the program counter (33) Incrementer (35), stack (36) for storing return address during interrupt processing, jump address registers (VAR1) (37) and (VAR2) connected to data bus BUS2 and preset with jump destination address data ) (38), output of incrementer (35), output of stack (36), output of jump address registers (37) and (38), and output of address data stored in program ROM (32) The multiplexer (39) and the loop counter (which sets the number of times the same instruction is executed while leaving the data in the program counter (33) unchanged. LOOP) (40)
It consists of and. The program ROM (32) has a capacity of 32 bits × 512 and is a program for realizing a digital filter, a program for addressing an externally connected external memory device, and a program for extracting digital data from the interface circuit (15). , And other necessary programs are stored. Further, the digital data and address data contained in the instruction code read from the program ROM (32) can be sent to the data bus (11). Instruction decoder (34)
From, INC1, INC2, DEC1, CLEAR2, DEC3 for controlling the address pointers (24) (25) (26) and the input selection circuit MPXA, M
A-BUS, A-DRAM, B-BUS, B-CRAM, B-CRO that also controls PXB
M, ADD, THR, MD for controlling ALU (28), CHG for controlling data exchange register (17), conditional branch control circuit (1
OVFR, SIFR, CAFR, BOFR for controlling 9) and MBDL for controlling the storage control register (18) are output. Further, the multiplexer (39) receives the jump control signal JMP output from the conditional branch control circuit (19) and the control signal PRGC output from the instruction decoder (34) when the jump instruction, the skip instruction, or the return instruction is executed. , Its selection operation is controlled. Loop counter (40)
Is connected to the data bus BUS2 and controls the data sent to the data bus BUS2 by the control signal MBDL output from the instruction decoder (34) when the first transfer instruction is executed when the data is fetched from the interface circuit (15). input.

The interface circuit (15) is for transmitting and receiving data between the DSP system and an external control device, for example, a micro computer (not shown), and as shown in FIG. 3, an input register (SIPO) (41). And the holding register (LI
FO) (42), transfer end flag (F) (43), and output register (44). The input register (41) is
Serial input data applied from the micro computer
It is a 16-bit shift register that sequentially inputs SIN by a synchronous clock SCLK. When 16-bit data input is completed, the parallel output holds the input digital data in the holding register (42). The holding register (42) is a register having a capacity of 16 bits × 8,
The eight addresses of the holding register (42) are designated by the address pointer (45). Address pointer (45)
Is incremented each time writing is performed to the holding register (42) and decremented each time reading is performed. Therefore, the holding register (42) is decremented.
When reading out, the digital data is taken out in the reverse order of the written order. Holding register (4
When the address pointer (45) becomes "0" as a result of the reading in 2), the signal SE indicating that the reading is completed
MP is output to the micro computer. On the other hand, when the data transfer is completed, the micro computer will end signal SRDY.
Is applied and the transfer end flag (43) is set. The output register (44) is connected to the data buses BUS1 and BUS2
It is a bit shift register that inputs the data transferred to the data bus (11) in parallel and uses the transfer clock SOCLK from the micro computer to output the serial data SOU.
Output T.

The external memory interface circuit (16) is a circuit for addressing and transmitting / receiving data to / from a memory externally connected to the DSP system, and is connected to the data bus (11) as shown in FIG. Address holding register (RMA
D) (46) (47) and address holding registers (46) (4
Output register (48) connected to 7), input register (49) for inputting digital data fetched from an external memory device (not shown), connected to input register (49) and data bus (11) Input data holding register (RMR
D) (50) (51), output data holding registers (RMWR) (52) (53) connected to the data bus (11), and an output register (54). The address holding registers (46) and (47) each have 17 bits, and the output register (4
In 8), 17-bit address data is divided into 9 bits and 8 bits and applied to the external memory device at different timings. The 16-bit data read from the external memory device is divided into 8 bits and applied to the input register (49). These 16-bit data are combined into 16-bit input data holding registers (50) (51). Is to be applied to. The output data holding register (52) (53)
Is composed of 16 bits, holds the output data sent to the data bus (11), and outputs it to the output register (54). The output register (54) outputs the output data in 16 bits.
It is divided into bits and output to an external memory device.

In this embodiment, the external memory device is used to create a reflected sound and a reverberant sound, and the areas are divided as shown in FIG. 5, for example. In Figure 5,
From the address "0" to "A-1" of the external memory device, the digital data of the audio signal is delayed in the area for creating the primary reflected sound, the secondary reflected sound, the tertiary reflected sound ... The area from "A" to "A + n" is an area for creating reverberation sound, and can be accessed by circulating with independent address data "0" to "n". ing. The processing for that will be described later.

The data exchange register (17) holds the data sent to the data bus BUS1 and holds the 24-bit R → L register (17a) that outputs to the data bus BUS2 and the data sent to the data bus BUS2. Control signal CHG that consists of a 24-bit L → R register (17b) that outputs to the data bus BUS1, and that is output from the control circuit (20) when executing the exchange instruction.
Therefore, the data holding and output are R in one instruction cycle.
→ L register (17a) and L → R register (17b) are performed simultaneously. Therefore, it is possible to perform a signal operation such that the right channel digital data and the left channel digital data are exchanged with each other, each partner channel data is multiplied by a predetermined coefficient, and the own digital data is added or subtracted.

The storage control register (18) is a 2-bit register, and when a transfer instruction for fetching data from the interface circuit (15) is executed, a 2-bit control signal MBDL output from the control circuit (20) Data is set. The 2-bit output of the storage control register (18) is the data RAM (2) of the digital processing circuit (12) (13).
1) and a constant RAM (22) applied to control their write operations. That is, the interface circuit (15)
The data retrieved from the data RAM (21) or constant R
The write operation is controlled when the transfer instruction to transfer to AM (22) is executed. For example, when changing the constant of the digital filter written in the constant RAM (22), the right channel and the left channel can be changed at once by setting "1" to both 2 bits of the storage control register (18) in advance. To change the right channel and the left channel independently, the bit corresponding to the channel to be changed may be set to "1" and the other bit to "0". The data set to this storage control register (18) is stored in the control circuit (20).
It is performed simultaneously with the data setting to the loop counter (40) (Fig. 2) and the address pointers (24) and (25). That is, the micro computer is connected to the interface circuit (1
When data is transferred to the holding register (42) (Fig. 3) of 5), it is composed of data indicating the number of data, address data indicating the start address to write the data, and data indicating the right channel or the left channel. Transfer data last. As shown in FIG. 6, in the allocation of the composite data, among the 16-bit data, the lower 10 bits indicate the address data, the upper 4 bits indicate the number of data, and the remaining 2 bits specify the right channel and the left channel. The data. Therefore, when data is fetched from the interface circuit (15), composite data is fetched by first executing a transfer instruction to the loop counter (40), address pointer (25) and storage control register (18). Is set, and in the execution of the next transfer instruction, the transfer is performed based on the content of the composite data.

The conditional branch control circuit (19) outputs a signal output when the digital processing output of the ALU (28) of each digital processing circuit (12) (13) reaches a predetermined state to the data bus BUS2.
Select jump control signal based on the data applied from
JMP is generated, and as shown in FIG.
Bit condition setting register (55) and each ALU (28)
Borrow flags (R) and (L) (56) set by borrow signals BOR (R) and (L) output from the same, and carry flags (R) set by carry signals CAY (R) and (L). , (L) (57) and a sine signal SIN (R) indicating that the result data processed by the ALU (28) is negative,
Sign flags (R), (L) (5) set by (L)
8) and digital data overflow, that is, "7FF
FFFFF ”(36 bits) or more, and“ 80000
Overflow signal OVF (R), which is output when 000 ”(36 bits) or less (negative overflow)
Overflow flag (R) set by (L),
(L) (59) and the 2-bit output of the condition setting register (55) and its inverted output to control each flag (56)
(57) (58) (59) (R) and (L) selection circuit (60) for selecting the output. This selection circuit (60)
Is composed of an AND gate (61) and an OR gate (62). When B ₁ and B _{2 of} the condition setting register (55) are “1” and “1”, respectively, the respective flags (56) (57) ) (58) and (59) (R) or (L) is set, the jump control signal JMP is output and B ₁ and B ₂ are "1" respectively.
In the case of "0", each flag (56) (57) (58) (5
The jump control signal JMP is output only on the (R) side of 9), that is, only under the condition of the digital processing circuit (12), and conversely B ₁ , B ₂
If each is "0" or "1", each flag (56)
If the jump control signal JMP is output only on the (L) side of (57), (58) and (59), that is, only under the condition of the digital processing circuit (13), and B ₁ and B ₂ are both “0”, , Each flag (5
6) The jump control signal JMP is output only when both (R) and (L) of (57) (58) (59) are set. Therefore, the jump condition can be set according to the contents of the data set in the condition setting register (55). The borrow flag (56), the carry flag (57), and the sign flag (58) are set in the control circuit (2) at the last timing in the execution cycle of the conditional branch instruction.
0) is reset by the reset signals BOFR, CAFR, and SIFR output from the installation decoder (34), but the overflow flag (59) is not reset in the execution cycle of the conditional branch instruction based on the overflow flag. , An installation decoder by executing a single overflow flag reset instruction (34)
It is reset by the control signal OVFR output from.

Next, operations for realizing various functions using the DSP system shown in FIG. 1 will be described.

For example, when implementing a graphic equalizer in audio signal processing, the product represented by yi = xiA + xi _-1 B + xi _-2 C + yi _-1 D + yi _-2 E (A, B, C, D, E are filter constants) It is obtained by connecting a plurality of band digital filters realized by the sum operation.

FIG. 8 shows a 2-band graphic equalizer realized by vertically connecting two stages of band digital filters of a second-order direct IIR filter. In Figure 8, Z ^-1 (63) is the unit time (sampling cycle here).
(64) is a multiplication element of constants A to J,
(65) is an addition element.

FIG. 9 is a diagram showing a program for realizing the digital filter of FIG. 8, and FIG. 10 is an allocation diagram of data stored in the data RAM (21) and the constant RAM (22).
The program shown in FIG. 9 performs multiplication of constants by C, B, A, E, D, H, G, F,
In order of J and I, the constant RAM (22) address "0"
From "9" to "9", constants are stored in the same order. On the other hand, the data xi, yi, and zi are written into the data RAM (21) at every 3 addresses, but the sampling period, that is, 1 at each filter processing time for one input data xi ₊₁ .
The delay data is created by the delay element (63) by shifting the address and writing xi ₊₁ , yi ₊₁ , zi ₊₁ .
Therefore, the address pointer (24) is set in advance by a program so that the address pointer (24) is cyclically addressed from "0" to "7" and the address pointer (25) is cyclically addressed from "0" to "9". .

Here, at the time when step “0” of the program of FIG. 9 is executed for the input data xi, the data RAM (2
When the content of 1) is as shown in FIG. 10 (a), and when the address pointers (24) and (25) are both addresses "0", when step "0" is executed, the multiplier (27) For inputs A and B, data xi _-2 (input data two samples before) stored in address "0" of data RAM (21) and address "0" of constant RAM (22) are stored. Coefficient C
Is applied, but the multiplication result is determined and output in the next step. At the end of step "0", the command AP
The address pointers (24) and (25) are both incremented by 1INC and AP2INC, and the content becomes "1".

When the step "1" is executed, the data RAM (21) and the constant RAM (22) are selected as the inputs of the multiplier (27) as in the step "0", and are respectively stored in the address "1". The data xi _-1 and the constant B are applied to the multiplier (27). In addition, the result of multiplication at the previous step "0" is the instruction AL.
By UTHR, the first multiplication result C · xi ₋₂ is stored in ACC (29) without passing through ALU (28). At the end of the step "1", the address pointer (2
4) (25) is incremented and the content becomes address "2".

Next, when step "2" is executed, the command MULA-BUS,
The B-CRAM selects the data bus (11) for the input A and the constant RAM (22) for the input B of the multiplier (27). On the other hand, the instruction TMP1S sends the contents of the temporary register TMP1 to the data bus (11), and the instruction RAM1D
The data sent to the data bus (11) is stored in the address "2" of the data RAM (21) designated by the address pointer (24). At this time, the temporary register TMP1 has a data input circuit (1
Input data xi applied from the outside is stored in advance in 4). Therefore, the input data xi is multiplied by the constant A read from the constant RAM (22) by the multiplier (27) and is stored in the address “2” of the data RAM (21). On the other hand, by the instruction ALUADD, the multiplication result B.xi of step "1" and C.xi _-2 stored in ACC (29)
_-1 is added, and as a result, B · xi ₋₁ + C · xi ₋₂ becomes ACC.
Stored at (29). At the end of step "2", the address pointers (24) and (25) are incremented, and the contents become the address "3".

When step "3" is executed, the input A of the multiplier (27)
The data yi _-2 and the constant E stored in the address "3" of the data RAM (21) and the constant RAM (22) are applied to B and B, and the multiplication result A of the step "2" is given by the instruction ALUADD.
・ Contents of xi and ACC (29) B ・ xi _-1 + C ・ xi _-2 are ALU (28)
And the addition result is A · xi + B · xi ₋₁ + C · xi
_-2 is stored in ACC (29). At the end of the stop "3", the address pointers (24) and (25) are incremented to become the address "4".

When step "4" is executed, the input A of the multiplier (27)
The data yi _-1 and the constant D stored in the address "4" of the data RAM (21) and the constant RAM (22) are applied to B and B, and the multiplication result E of the step "3" is given by the instruction ALUADD.
・ Contents of yi _-2 and ACC (29) Axi + B, xi _-1 + C, xi _-2 is AL
It is added at U (28) and the result is A ・ xi ＋ B ・ xi _-1
+ C · xi ₋₂ + E · yi ₋₂ is stored in ACC (29). At the end of step "4", the instructions AP1DEC and AP2INC decrement the address pointer (24) to an address "3", and the address pointer (25) is incremented to an address "5".

When step "5" is executed, the input A of the multiplier (27)
In and B, the data yi _-2 stored in the address "3" of the data RAM (21) and the address "5" of the constant RAM (22).
The constant H stored in is applied. That is, the multiplier (2
In step 7), the second-stage multiplication of the digital filter shown in FIG. 8 is performed from step "5". Meanwhile, the instruction ALUADD
Results in multiplication result of step “4” D · yi ₋₁ and ACC (2
9) Content A ・ xi ＋ B ・ xi _-1 ＋ C ・ xi _-2 ＋ E ・ yi _-2 is ALU
It is added in (28) and the addition result is A ・ xi + B ・ xi _-1 ＋
C · xi ₋₂ + D · yi ₋₁ + E · yi ₋₂ is stored in ACC (29). The contents of ACC (29) at this time become the output yi of the first-stage digital filter. At the end of step "5", the address pointer (24) is incremented to become the address "4", and the address pointer (25) is incremented to become the address "6".

By performing steps "6" to "11" below, the filtering process is performed on the input data xi, the contents of the data RAM (21) are changed as shown in Fig. 10 (b), and the filtering process zi is obtained. To be And the start address is 1
By advancing to the address destination and repeating the same operation, the data RAM (21) changes as shown in FIGS. 10 (c) and 10 (d), and the filter outputs zi _{+ 1} , zi _{+ 2} ... Are obtained. Since this operation is simultaneously performed on both the digital processing circuits (12) and (13), the filtering processing for the right channel and the left channel is performed at the same time.

Next, an operation of cyclically accessing the cyclic memory area of the external memory device will be described. As shown in FIG. 5, the cyclic memory area is "0" to "n" as an independent memory.
Can be accessed with the address data up to, and the previous address data X is held at a predetermined address of the constant RAM (22). Therefore, a case where one address is accessed in the direction from the address “n” to the address “0” will be described.

First, the address where the address data X is stored is set in the address pointer (25) and the MD instruction is executed.
This MD instruction reads the address data X from the constant RAM (22), decrements it in the ALU (28) by the control signal MD, and as a result holds X-1 in ACC (29). If a borrow occurs as a result of 1, the constant RO
The end address "n" of the cyclic memory area stored at the predetermined address of M (23) is read out, and X- is stored in ACC (29).
Hold instead of 1. All of these operations are performed within the execution cycle of the MD instruction. Next, by the transfer command,
Constant RAM where address data "X" has been stored until now
The data of ACC (29) is transferred to and held at the address of (22). Further, the addition instruction ADD is executed, and the start address “A” of the cyclic memory area stored in the constant ROM (23)
Is read out and added to the data held in ACC (29), and the addition result, that is, "X-1 + A" is again read in ACC (2
Hold on to 9). As a result, the address data held in the ACC (29) becomes the real address data of the external memory device. In order to apply this to the external memory device, a transfer instruction is executed and the address data in ACC (29) is transferred to one of the address holding registers RMAD (Fig. 4) of the external memory interface circuit (16). To do. As a result, the address data "X-1 + A" is applied to the external memory device by the output register (48).

When a D-RAM (dynamic random access memory) is used as the external memory device, the D-RAM is refreshed by cyclically accessing the cyclic memory area. That is, when the actual address data "X-1 + A" is 16 bits, "X" for addressing the cyclic memory area is "0" to "n". Therefore, the bit changed by the cyclic access is 16 bits. It is a part of the address data. Therefore, the output register (48) shown in FIG. 4 is configured to output the changing bit as row address data of the D-RAM. Further, the address data is 16 bits, whereas the address holding registers (46) (47) and the output register (48) are composed of 17 bits, which means that the changing bits are the row address data of the D-RAM. This is because when the number of bits is less than 1, the remaining 1 bit is output as 1 bit of the row address data, and all the refresh is performed by operating this 1 bit.

By the output of the real address data "X-1 + A", the read data is taken in the data bus (11) via the input register (49) and the input data holding register RMRD (50) or (51), and The data to be written is written to the external memory device via the output data holding register RMWR (52) or (53) and the output register (54).

In this way, since the decrement and the transfer operation based on the result are performed within the execution cycle of the MD instruction, the program step for creating the address data becomes short.

Next, the function of adjusting the level of input data will be described. The digital data input in each sampling cycle is processed by the digital filter as described above, but if the level of the input data is too large or too small, overflow occurs during multiplication and calculation. When the filter output in the state where the overflow has occurred is converted into an analog signal to be an audio signal, it is reproduced as noise.

Therefore, in the DSP system shown in FIG. 1, it is possible to detect the overflow, control the filter output, and adjust the level of the input data. An example of the operation will be described with reference to FIG.

Instead of directly filtering the digital data input for each sampling cycle, the coefficient K is multiplied, and the multiplication result is used as the input digital data xi for filtering. In FIG. 11, first, the data input / output circuit (14)
Digital data is input from and is temporarily held at a predetermined address in the data RAM (21). And the multiplication instruction MUL
Thus, the unprocessed digital data read from the data RAM (21) is multiplied by the coefficient K held in the temporary register TMP3. This temporary register TM
P3 is used for holding the coefficient K, and in the initial state,
The constant "1" stored in the constant ROM (23) has been transferred in advance. After the multiplication, the instruction for resetting the overflow flags (R), (L) (59) in the conditional branch control circuit (19) is executed, and the overflow flag (R),
(L) and (59) are reset, and the digital data xi holding the multiplication result of the coefficient K is transferred to the temporary register TMP1. This temporary register TMP1
Is used for holding the input digital data xi when performing the filter processing as described above, and the input digital data xi is filtered as described above. When the filtering process ends, it is determined by an overflow flag determination command whether or not an overflow has occurred due to multiplication or calculation during the filtering process. At this time,
"1" and "1" are set in the condition setting register (55) (FIG. 7) of the conditional branch control circuit (19) so that it is possible to determine either the left or right overflow. Judgment result,
If no overflow has occurred, continue the next filtering process. If an overflow occurs, look at the output data of the filtering process and determine whether the overflow is a positive overflow or a negative overflow. To do. If it is a positive overflow, take out the maximum value "7FFFFFFF" stored at the specified address in the constant ROM (23) and set it in the data RAM (21) as the filter output zi. If it is a negative overflow Is the minimum value "80000" stored in the constant ROM (23).
000 ”is taken out and data RAM is output as filter output zi
Store it in (21). Then, when the filtering process is completed, the output data z stored in the data RAM (21) is stored.
Data input / output circuit (1
4) Transfer to and output. Here, before proceeding to the processing of the next input data, it is judged again whether or not overflow has occurred. Overflow flag (R) shown in FIG.
Since (L) and (59) are not reset when the overflow flag determination instruction is executed, they are still set if there is an overflow in the previous filter processing.
If the result of the determination is that there is an overflow, the level of the input digital data is too high, so in order to reduce the coefficient K, the constant "a" (a = 0.99) stored in the constant ROM (23). ) Address is set in the address pointer (26). On the other hand, if there is no overflow, it is determined whether the coefficient K held in the temporary register TMP3 is "1". When the coefficient K is "1", it is not necessary to change the coefficient K, so the address in which the constant "1" of the constant ROM (23) is stored is set in the address pointer (26), and the coefficient K is "1". If it is not "1", it is determined whether K> 1 or K <1. When the coefficient K> 1, the constant "a" is selected to bring it closer to "1". When the coefficient K <1, Select the constant "b". Then, by the multiplication instruction, the constant addressed by the address pointer (26) is read from the constant ROM (23), multiplied by the coefficient K held in the temporary register TMP3, and the result is transferred to the temporary register TMP3 as a new coefficient K. To do. Then, the next input digital data is multiplied by the coefficient K again. The set overflow flags (R), (L) (59) are reset by the reset instruction after multiplication.

In this way, when an overflow occurs during multiplication or calculation, the coefficient K is gradually increased / decreased every sampling cycle, so that the level of the input digital data changes gently. Further, even when the overflow disappears, the coefficient K gradually changes so as to become "1", so that when the output digital data is converted to analog and reproduced, there is no sudden change in sound.

Next, the operation when changing or writing the filter coefficient for configuring the digital filter stored in the constant RAM (22) will be described. When changing the coefficient of the digital filter, an externally connected micro computer sends the coefficient. Although the digital filter has the configuration shown in FIG. 8, the coefficient must be changed at each stage once. For example, if the coefficient is changed during the filter operation of the first stage, the filter output yi of the first stage becomes a distorted one that is not properly filtered. Therefore, a case will be described in which the five filter coefficients A, B, C, D, and E of the first stage are changed.

As shown in FIG. 10, the constant RAM (22) has filter coefficients C, B, A, E, D between addresses “0” to “4”.
Are stored in this order. Since the holding register (42) of the interface circuit (15) shown in FIG. 3 is read out in the order opposite to the order in which it is written, the microcomputer sets the filter coefficients D, E, A, B. , C in this order, and after the coefficient C, the composite data shown in FIG. 6 is sent. In this case, the lower 10 bits of the composite data are
The address where the coefficient C of the constant RAM (22) is stored, that is,
It is “0”, and the upper 4 bits are data indicating the number of coefficients, that is, “5”. Coefficients A, B, C, D, E
To change both the right and left channels of
The remaining 2 bits of the composite data are both "1", and when changing independently, only the bit corresponding to the channel to be changed is set to "1".

When the micro computer finishes transferring the coefficients D, E, A, B, C and the composite data, the transfer end flag (43) is set, so that the DSP system terminates the transfer by the transfer end flag (43) determination command. Is detected, first, a transfer instruction from the interface circuit (15) to the loop counter (40), the storage control register (18), and the address pointer (25) is executed. As a result, "5" is set in the loop counter (40), "0" is set in the address pointer (25), and "11" is set in the storage control register (18). Next, the number of times the transfer instruction from the interface circuit (15) to the constant RAM (22) is set in the loop counter (40),
That is, the constants executed five times and fetched from the holding register (42) are transferred to the constant RAM (22) in the order of C, B, A, E and D. Since the address pointer (25) is incremented each time the transfer instruction is executed, the constants C, B, A, E and D are stored at the respective addresses as shown in FIG.

Therefore, since the program for transferring the data from the interface circuit (15) can be realized by only two transfer instructions, the number of program steps can be shortened.

(G) Effect of the Invention As described above, according to the present invention, a multi-function and high-throughput DSP system can be realized, and it is easy to integrate it on a one-chip semiconductor element and easy to connect to an external device. Has the advantage that In particular, when used for audio signal processing, it has a great effect on improving the function of the audio device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 4 are more detailed block diagrams of the blocks shown in FIG. 1, and FIG. 5 shows an area of an external memory device. 6 and 6 are diagrams showing composite data externally applied to the DSP system shown in FIG. 1, FIG. 7 is an internal circuit of the block shown in FIG. 1, and FIG. 8 is a digital filter. FIG. 9, FIG. 9 is a diagram showing a program for realizing the digital filter of FIG. 8, and FIG. 10 is an address allocation diagram of a data RAM and a constant RAM for realizing the digital filter of FIG. FIG. 12 is a flow chart showing the operation of one function of the embodiment shown in FIG. 1, and FIG. 12 is a diagram showing a conventional example. (11) …… Data bus, (12) (13) …… Digital processing circuit, (14) …… Data input / output circuit, (15) …… Interface circuit, (16) …… External memory interface circuit, (17) ) …… Data exchange register, (18) …… Storage control register, (19) …… Conditional branch control circuit, (20)
...... Control circuit, (21) …… Data RAM, (22) …… Constant R
AM, (23) ... constant ROM, (24) (25) (26) ... address pointer, (27) ... multiplier, (28) ... ALU, (2
9) …… ACC, (30) …… temporary register.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03H 17/02 P 8842-5J (72) Inventor Masaki Kawaguchi 2-18, Keihanhondori, Moriguchi-shi, Osaka Address within Sanyo Electric Co., Ltd. (56) Reference JP 61-110256 (JP, A) JP 60-27977 (JP, A)

Claims (1)

[Claims] 1. A pair of data buses for transferring digital data, a pair of digital processing means respectively connected to the data buses, and operations of the pair of digital processing means are simultaneously controlled in accordance with a pre-programmed procedure. In the digital signal processing device, the digital data exchange means is provided between the pair of data buses, and the digital data exchange means holds the digital data sent to one of the data buses and holds the other. Of the first and second register means for holding the digital data sent to the other data bus and outputting it to one of the data buses. A digital signal processing device, characterized in that