JPH0429225B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a field-effect semiconductor device;
In particular, the present invention relates to a method of manufacturing a compound semiconductor field effect transistor having a shortened gate length, reduced resistance of electrodes and conductive paths, and excellent high frequency characteristics.

(b) Background of the technology The requirements necessary to realize a semiconductor device with excellent high-frequency characteristics are (a) short travel distance of the conductive medium, that is, small geometric dimensions of the semiconductor device; ) It is well known that the first requirement is that the moving speed of the conductive medium be high, and in order to satisfy this requirement, efforts are being made to realize fine patterns and high electron or hole mobility. Compound semiconductors such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and indium phosphide (Inp) are used as a means to achieve high electron mobility. High electron mobility transistors have been developed to achieve high electron mobility.

Furthermore, since high frequency characteristics such as the cutoff frequency as well as the time constant of all electric circuits depend on the resistance of the conductive path, it is desirable that the resistance of the conductive path be small in semiconductor devices as well. From this point of view, it is desirable that the impurity concentration in the region serving as the conductive path is high. However, on the other hand, since an increase in the impurity concentration inhibits the extension of the depletion layer, there are restrictions on the selection of the impurity concentration in the region below the gate. Therefore, in order to reduce the resistance of the conductive path without affecting characteristics such as the threshold voltage of the transistor, it is effective to increase the impurity concentration in regions other than the lower gate region.

In particular, compound semiconductors, which are materials that can be used to make semiconductor devices with excellent high-frequency characteristics, generally have a high surface state density, so surface depletion layers are likely to occur in conductive path regions other than gate regions, reducing the cross-sectional area of conductive paths. Since this results in a decrease in impurity concentration and causes an increase in resistance, it is desirable to keep the impurity concentration high in regions other than the gate lower region.

(c) Prior art and problems For these reasons, conventional semiconductor devices such as field effect transistors for high frequencies and high speed switching have been designed to have good ohmic contact with electrodes and to form conductive paths. In order to reduce the resistivity of the semiconductor region, high concentration impurities are selectively introduced into the source/drain regions.

In particular, in order to align this impurity-introduced region with the gate electrode, impurities are ion-implanted at a high concentration using the gate electrode disposed on the active layer of the semiconductor substrate as part of a mask, and then heat-treated. A structure is adopted in which a high impurity concentration region is formed by activating ions, and source/drain electrodes are provided in ohmic contact therewith.

As an example of applying the above structure to a compound semiconductor device, for example, the present applicant previously filed a patent application filed in 1983.
There is a semiconductor device and its manufacturing method provided by No.-189544.

However, in the self-alignment method in which impurities are introduced by ion implantation using the gate electrode as a mask, the gate length is shortened to increase the speed of semiconductor devices, especially when it is about 1 [μm] or less. It has become clear that the gate threshold voltage varies greatly, making it difficult to control it. This change in gate threshold voltage is caused by the impurity introduced by ion implantation diffusing into the semiconductor region that serves as the active layer covered by the gate electrode, and the impurity concentration in this region changes. The causes of this impurity diffusion include scattering of impurities due to collision with the substrate crystal lattice during ion implantation and lateral thermal diffusion of impurities during heat treatment to activate the implanted ions. Although both of these two factors can be alleviated by selecting the structure, material, manufacturing method, etc., it is essentially impossible to prevent them.

As one of the means for solving the above-mentioned problems in the self-alignment method, there is a manufacturing method previously proposed by the applicant of the present invention in Japanese Patent Application No. 57-030005.

In the present invention, an n-type impurity is introduced into the surface layer of a semiconductor substrate to form an active layer, a gate electrode is formed in a partial region on the active layer, and the active layer is used as a source/drain using the gate electrode as a mask. The present invention provides a manufacturing method in which a semiconductor buried layer containing an n-type impurity is removed from a formation region, a semiconductor buried layer containing an n-type impurity is grown in the removed region, and a source electrode and a drain electrode are formed on the buried layer. A manufacturing method similar to the above method is also provided for electron mobility transistors.

The prior invention does not affect the dimensions or impurity concentration distribution of the active layer region under the gate electrode,
It is possible to reduce the resistivity in this region by increasing the impurity concentration only in the source/drain region, but the manufacturing method is somewhat complicated, and it is difficult to ensure the withstand voltage between the gate source and drain. be.

(d) Purpose of the Invention The present invention reduces the ohmic contact resistance of source/drain electrodes and the resistance of a semiconductor region serving as a conductive path without affecting the dimensions or impurity concentration distribution of the active layer region under the gate electrode. Another object of the present invention is to provide a method for manufacturing a field effect semiconductor device, particularly a compound semiconductor field effect transistor, which has good high frequency and high speed switching characteristics.

(e) Structure of the Invention The objects of the present invention are to form a conductive active layer in a predetermined region on the surface of a semiconductor substrate, to selectively form a gate electrode on the active layer, and to forming a pair of conductive semiconductor regions facing each other with the gate electrode in between, by growing a semiconductor layer having a higher impurity concentration than the active layer on the active layer using the gate electrode as a mask; spatially separating the gate electrode and the conductive semiconductor region by etching;
This is achieved by a method for manufacturing a field-effect semiconductor device, which includes the step of forming electrodes in resistive contact with each of the conductive semiconductor regions.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

1 to 4 are cross-sectional views showing the main manufacturing steps of a first embodiment of the present invention relating to a GaAs shot barrier field effect transistor, and the structure of this embodiment will be explained while illustrating the manufacturing method.

Refer to Figure 1. Silicon (Si) is selectively implanted into the surface layer of the semiconductor device forming region of the semi-insulating GaAs substrate 1 at an energy of about 59 [KeV] and a dose of about 1.7×10 ¹² [cm ^-2 ]. ion implantation and then e.g. temperature
By performing an activation heat treatment at 850 [° C.] for about 15 minutes, an n-type active layer 2 with a thickness of about 0.1 [μm] and an impurity concentration of about 1×10 ¹⁷ [cm ^-3 ] is formed.

Next, a gate electrode 3 is provided on the active layer 2 using a material that does not lose its gate characteristics even at selective epitaxial growth temperatures to be described later. In this example, tungsten silicide (W ₅ Si ₃ ) is deposited to a thickness of, for example, 0.4 μ by sputtering.
A gate electrode 3 having a gate width of, for example, 30 [μm] and a gate length of about 2 [μm] is formed by photolithography and etching.

Refer to FIG. 2. An n-type high impurity concentration semiconductor layer 4 is selectively epitaxially grown in a region other than the gate electrode 3 on the surface of the GaAs substrate 1. In this example, hydride arsine (ASH ₃ ), trimethylgallium ((CH ₃ ) ₃ Ga), and hydrogen sulfide (H ₂ S) were grown using a metal organic pyrolysis vapor phase growth method (hereinafter abbreviated as MOCVD method). is sent to the reaction tube together with nitrogen (N ₂ ) gas, and at a temperature of approximately 600 [℃], the n ⁺ type
The thickness of the GaAs layer 4 is approximately 0.4 [μ
m].

The impurity concentration of this n ⁺ type GaAs layer 4 is 2×10 ¹⁸ [cm
^-3 ], and when using the ion implantation method commonly used to form conventional source/drain regions, the impurity concentration distribution forms a normal distribution in the depth direction, and even at the position of the maximum concentration, the impurity concentration distribution is approximately 1× 10 ¹⁸
While it cannot exceed about [cm ^-3 ],
The n ⁺ type GaAs layer 4 of this example has a high impurity concentration and a reduced resistivity. Further, the epitaxial growth layer can be made thicker as desired, and in this embodiment as well, it is grown thicker than the effective depth of the conventional source/drain regions, and from this point as well, the resistance value is reduced.

Refer to FIG. 3. In order to ensure gate reverse dielectric strength, the gate electrode 3 is plasma etched using, for example, a mixed gas of Freon (CF ₄ ) and oxygen (O ₂ ).

By this gate electrode etching process, the gate reverse dielectric strength voltage, which was unstable at about 0.2 to 1 [V] before the process, can be stabilized to about 10 [V] or more.

Next, portions of the n ⁺ type GaAs layer 4 other than the active layer 2 are selectively removed. In this embodiment, a chemical etching method is used in which silicon dioxide (SiO ₂ ) is used as a mask and a mixed solution of hydrofluoric acid (HF), water (H ₂ O), and hydrogen peroxide (H ₂ O ₂ ) is used as an etchant.

Refer to FIG. 4. A source electrode 5 and a drain electrode 6 are provided in ohmic contact with the n ⁺ type GaAs layer 4. In this embodiment, these electrodes are formed using gold germanium/gold (AuGe/Au) according to the conventional technique. In this way, the GaAs shot barrier field effect transistor device of this example is completed.

As shown in FIG. 5 as a second embodiment, instead of selectively removing the n ⁺ type GaAs layer 4 performed in the first embodiment, the element isolation region 7 is filled with oxygen (O), for example. A structure formed by increasing the resistance of the n-type GaAs layer 4 by implanting ions or chromium (Cr) ions is suitable for integrated circuits.

In the embodiment described above, the gate electrode 3
The thickness of the mask is approximately 0.4 [μm] as in the conventional case, but in the present invention, unlike in the case of using a mask for conventional ion implantation, there are no restrictions on the thickness and shape in terms of the manufacturing process. Furthermore, for the epitaxial growth of the high impurity concentration semiconductor layer of the present invention, it is possible to apply an appropriate method such as the MOCVD method as in this embodiment or the molecular beam epitaxial growth method. While the activation temperature is, for example, about 800 [°C], the epitaxial growth temperature can generally be lowered, for example, about 600 [°C]. It is not always necessary to use gate electrode materials, laminated structures, etc., and it becomes possible to select a wider range of gate electrode materials, laminated structures, etc. than in the past.

As explained above, since the semiconductor device of the present invention does not perform ion implantation and activation of the implanted ions by heat treatment, there is no scattering of the implanted ions into the active layer region under the gate electrode, and there is little lateral thermal diffusion. . Therefore, the gate threshold voltage is stable even when the gate length is shortened. Furthermore, the n-type of the above example
Since the ohmic contact electrode is provided in a semiconductor layer with high impurity concentration and low resistance, such as GaAs4, good ohmic contact is obtained and the conductive path has low resistance, reducing source resistance and drain resistance.

Furthermore, by expanding the selection range of the material and structure of the gate electrode, it becomes possible to reduce the resistivity of the gate electrode or to facilitate pattern formation.

Due to the above-mentioned effects, high frequency and high speed switching characteristics can be significantly improved compared to the conventional ones. As an example, the delay time per gate stage of an E/D configuration DCFL ring oscillator is 1.5 [μ
m] and 50 [PS], whereas with the method of the present invention, the gate length is 1 [μm] and it is 20 [PS].
can be shortened to

Although the embodiment described above is an example of a shot barrier field effect transistor, the present invention can also be applied to a high electron mobility field effect transistor including a heterojunction in a semiconductor substrate, and can be applied to a normal shot barrier field effect transistor. Similarly, it is possible to obtain effects such as ohmic contact and a reduction in the resistance of the conductive path.

(g) Effects of the Invention As explained above, according to the present invention, the gate threshold voltage can be stably maintained even when the gate length is shortened, and the resistance of the ohmic contact between the source and drain electrodes and the conductive path can be reduced. Furthermore, it is possible to reduce the resistance of the gate electrode, and provide a semiconductor device with excellent high frequency characteristics and high speed switching characteristics, particularly a field effect transistor using a compound semiconductor.

[Brief explanation of drawings]

1 to 4 are sectional views showing main manufacturing steps of a first embodiment of the present invention relating to a field effect transistor, and FIG. 5 is a sectional view of the second embodiment. In the figure, 1 is a semi-insulating linear GaAs substrate, 2 is an n-type active layer, 3 is a gate electrode, and 4 is n ⁺ type GaAs
5 is a source electrode, 6 is a drain electrode, and 7 is an element isolation region.

Claims (1)

[Scope of Claims] 1. A step of forming a conductive active layer in a predetermined region on the surface of a semiconductor substrate, a step of selectively forming a gate electrode on the active layer, and a step of performing the operation using the gate electrode as a mask. A step of forming a pair of conductive semiconductor regions facing each other with the gate electrode in between by growing a semiconductor layer having a higher impurity concentration than the active layer on the active layer, and etching the gate electrode. A method for manufacturing a field effect semiconductor device, comprising: spatially separating a gate electrode and the conductive semiconductor region; and forming an electrode in resistive contact with each of the conductive semiconductor regions.