JPH04277624A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance by forming a high melting point metal silicide of excellent conductivity self-aligningly in a buried contact. CONSTITUTION:A semiconductor device where a gate electrode 5 formed on one main face of a P-type silicon substrate 1 via a gate insulating film 3 is connected to an N-type diffusion layer 8 formed in the above-mentioned substrate, the semiconductor device coated with a high melting point metal silicide in a region of the diffusion layer uncoated with the gate electrode and at least in a part of the gate electrode surface.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an electrical connection structure between a gate electrode and a diffusion layer.

0002

2. Description of the Related Art Refer to FIGS. 3(a) and 3(b) for a structure (buried contact hole) for electrically connecting one end of a gate electrode to another diffusion layer in a static RAM memory cell according to the prior art. I will explain.

First, as shown in FIG. 3(a), a field oxide film 2 is formed on a P-type silicon substrate 1 by the LOCOS selective oxidation method, and a gate oxide film 3 with a thickness of 200A is formed. 3 is selectively etched to form a buried contact 4.

Next, as shown in FIG. 3(b), the thickness is 30 mm.
After forming a doped polysilicon film of 00A, patterning is performed to form a gate electrode 5. Thereafter, a source-drain (not shown) is formed by arsenic ion implantation, and an N-type diffusion layer 8 is formed by heat treatment to diffuse phosphorus from the gate electrode 5 into the P-type silicon substrate 1, and then the N-type diffusion layer 8 is formed to form the buried contact 4. The connection is complete.

[0005]

[Problems to be Solved by the Invention] As semiconductor devices become more highly integrated, the contact area between the gate electrode and the diffusion layer through a buried contact becomes smaller, and the junction of the N+ type diffusion layer becomes shallower. As a result, the total amount of phosphorus in the N+ type diffusion layer decreases, contact resistance increases, and the circuit does not operate properly.

[0006]

[Means for Solving the Problems] In the semiconductor device of the present invention, contact resistance in the buried contact portion is reduced by forming refractory metal silicide in the buried contact portion in a self-aligned manner.

[0007]

[Example] Regarding the first example of the present invention, FIG. 1(a)
This will be explained with reference to (d).

First, as shown in FIG. 1(a), a field oxide film 2 is formed on a P-type silicon substrate 1 by the LOCOS selective oxidation method, and a gate oxide film 3 with a thickness of 200A is formed. 3 is selectively etched to form a buried contact 4.

Next, as shown in FIG. 1(b), the thickness is 30 mm.
After forming a doped polysilicon film of 00A, patterning is performed to form a gate electrode 5.

Next, as shown in FIG. 1(c), a thickness of 10
A titanium film 6 of 00A is formed.

Next, as shown in FIG. 1(d), 600°C
A titanium silicide film 7 is formed on the exposed portion of the buried contact 4 and the surface of the gate electrode 5 by heat treatment for several tens of seconds in a nitrogen atmosphere. Next, the unreacted titanium film 6 is removed using an NH3-H2O2-based aqueous solution. Thereafter, a source-drain (not shown) is formed by arsenic ion implantation, and an N-type diffusion layer 8 is formed by heat treatment to diffuse phosphorus from the gate electrode 5 into the P-type silicon substrate 1, and then the N-type diffusion layer 8 is formed to form the buried contact 4. The connection is complete.

This buried contact 4 is connected to the gate electrode 5.
In addition to the diffusion layer 8, the contacts are also connected by titanium silicide, which has high conductivity, so that the contact resistance can be made smaller than before.

Next, a second embodiment of the present invention will be described with reference to FIGS. 2(a) to 2(e).

First, as shown in FIG. 2(a), a field oxide film 2 is formed on a P-type silicon substrate 1 by the LOCOS selective oxidation method, and a gate oxide film 3 with a thickness of 200A is formed. 3 is selectively etched to form a buried contact 4. Next thickness 30
After forming a doped polysilicon film of 00A, patterning is performed to form a gate electrode 5. Next, in order to form an LDD transistor, a low concentration P type impurity is ion-implanted, and then an oxide film 9 having a thickness of 2000 Å is formed by CVD.

Next, as shown in FIG. 2(b), after etching back by anisotropic etching to form a sidewall 10 made of an oxide film 9, an oxide film with a thickness of 100A is formed by a CVD method or a thermal oxidation method. 11 is formed.

Next, as shown in FIG. 2C, after forming a photoresist 12, by wet or dry etching, the sidewall 10 of the buried contact 4 is removed, leaving the sidewall 10 (not shown) of the transistor section. remove.

Next, as shown in FIG. 2(d), a thickness of 10
A titanium film 6 of 00A is formed.

Next, as shown in FIG. 2(e), 600°C
A titanium silicide film 7 is formed on the exposed portion of the buried contact 4 and the surface of the gate electrode 5 by heat treatment for several tens of seconds in a nitrogen atmosphere. Next, the unreacted titanium film 6 is removed using an NH3-H2O2-based aqueous solution. Thereafter, a source-drain (not shown) is formed by arsenic ion implantation, and an N-type diffusion layer 8 is formed by heat treatment to diffuse phosphorus from the gate electrode 5 to the P-type silicon substrate 1, and the buried contact 4 is connected. is completed.

In the first embodiment, since the gate electrode 5 is etched to form the titanium silicide film 7,
Titanium silicide film 7 is also formed on the side surfaces of gate electrode 5, resulting in a change in gate length L. On the other hand, in this embodiment, since a sidewall is formed on the gate electrode and titanium silicide is formed, the gate length L does not change, so that an LSI as designed can be manufactured.

[0020]

Effects of the Invention: Forming high-melting point metal silicide with excellent conductivity in a self-aligned manner in the buried contact has the effect of reducing contact resistance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in order of steps.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in order of steps.

FIG. 3 is a cross-sectional view showing a buried contact hole structure according to the prior art in the order of steps;

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Embedded contact 5 Gate electrode 6 Titanium film 7 Titanium silicide film 8 N-type diffusion layer 9 Oxide film 10 Side wall 11 Oxide film 12 Photoresist

Claims (1)

[Claims] 1. A semiconductor device in which a gate electrode formed on one main surface of a semiconductor substrate via a gate insulating film is connected to a diffusion layer formed on the semiconductor substrate, wherein the gate electrode of the diffusion layer 1. A semiconductor device characterized in that a region not covered with silicide and at least a part of the surface of the gate electrode are covered with high melting point metal silicide.