JPH0426217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a concave capacitor and a method for manufacturing the same.

[Background of the invention]

In recent years, in one-transistor memory cells consisting of one capacitor and one field-effect transistor per memory unit, as shown in Fig. 1,
It has been proposed that a concave portion 2 is provided in the capacitor portion 1 to increase the effective capacitor area. (Unexamined Japanese Patent Publication No. 1973-
130178) Note that in Figure 1, memory cell 1
The individual portions are indicated by dotted lines a in FIG.

FIG. 2 is a cross section taken along the line AA in FIG. 1. (1st
In the figure, the wiring patterns of the word line 9, bit line 12, etc. are omitted. ) In memory cells with such concave capacitors, the capacitor area can be significantly reduced compared to those with conventional planar capacitors, but when trying to configure large-scale memories by arranging these cells in high density, the following problem arises: occurs. That is, when concave capacitors are placed close to each other, a leakage current as shown by arrow 13 tends to flow between the capacitors, resulting in unstable memory operation. Since impurity diffusion for channel cutting is normally performed directly under the field SiO ₂ 7 separating the elements, leakage current tends to flow near the arrow 13 where the saddle of the potential is formed. Further, a similar leakage current occurs not only between the capacitors (between the sources) but also between the capacitors and the contact portions 3 of the adjacent cells (between the sources and drains).

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which leakage current between capacitors (between memory cells) is prevented.

[Summary of the invention]

The present invention, which prevents leakage current caused by a concave capacitor, involves inserting an insulating film between the concave capacitor and the semiconductor substrate, or separating cells with a groove deeper than the concave capacitor. Therefore, the leakage current path is cut off.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a process diagram showing one embodiment of the present invention.

First, as shown in Figure 3, the well-known LOCOS
After forming the field SiO ₂ 7 by the method,
A film of Si ₃ N ₄ 15 and PSG (phosphorus glass) 16 was deposited, and a photoresist pattern 17 was formed with openings in the areas where the concave portions of the capacitor were to be formed. The opening is located at the end of the field SiO ₂ 7.

_Next , _PSG16 ,
Si ₃ N ₄ 15, feed SiO ₂ 7 and pad SiO ₂ 1
4 and Si substrate 4 were etched. At this time, the etching rate ratio of each material is Si ₃ N ₄ :SiO ₂ :Si=2:2:
The etching conditions were selected so that the etching value was approximately 1, and the etching was terminated when the etching of the field SiO ₂ 7 was completed. Next, the photoresist 17 was removed and Si ₃ N ₄ 18 was deposited. (Figure 3 2) Using reactive sputter etching with CH ₂ F ₂ gas, Si ₃ N ₄ 18 is directionally selectively etched leaving Si ₃ N ₄ 19 deposited on the sidewalls, followed by and CCl ₄
A recess 20 was formed in the Si substrate 4 by reactive sputter etching using an O ₂ mixed gas. (Fig. 3) The etching method used at this time was to use Si ₃ N ₄ 18 and Si substrate 4.
Any material other than those described above may be used as long as it can selectively and directionally etch each of the materials. In addition, PSG
16 is added for protection of Si ₃ N ₄ 15, and can be omitted.

Next, after removing the PSG 16 with a hydrofluoric acid solution and oxidizing the Si surface of the recess 20, the side wall and surface
Si ₃ N ₄ 15,19 was removed with phosphoric acid solution and PolySi
(Polycrystalline silicon) 22 was deposited so that the recesses were not completely filled. (Fig. 3 4) Here, in order to prevent the generation of parasitic channels, an impurity diffusion layer of the same conductivity type as the substrate 4 is formed by ion implantation under the SiO ₂ 21 in the recess. is desirable.

After diffusing impurities of a conductivity type different from that of the substrate 4 into the PolySi 22 to make it resistive, the PolySi 22 was etched by reactive sputter etching using CCl ₄ gas. By doing this, the side walls of the recess can be
Only PolySi23 remains, and this PolySi is
It is connected to the substrate 4 at the concave side wall 24 on the side where the field SiO ₂ 7 is not provided.

Next, an insulating film 25 (for example, SiO ₂ , Si ₃ N ₄ or a multilayer film thereof) and PolySi 26 are deposited, and the third
A MOS type capacitor as shown in FIG. 6 was formed.

The capacitor formed as above is the third
As is clear from FIG. 6, SiO ₂ is present at the boundary with the substrate 4.
21 is inserted, and the structure is such that leakage current between the capacitors is extremely difficult to flow.

FIG. 4 is a plan view of the above manufacturing process. The pattern 31 forming a recess in the island region 30 surrounded by the SiO ₂ field is arranged as shown in FIG. It is sufficient that the concave pattern 31 overlaps the island region 30 even a little.
There is a large margin for matching patterns in ring graphs. In addition, as shown in FIG. 42, the formed capacitor part 1 is surrounded by SiO ₂ 21 at the periphery and bottom, and the leakage current between the capacitors shown by arrows 32 and 33 and the leakage current shown by arrow 34 occur. It is clear that leakage current between the capacitor and the bit line contact portion is less likely to occur. Note that the SiO ₂ 21 surrounding the capacitor may be connected between adjacent cells.

FIG. 5 shows an example in which a field is formed with thick SiO ₂ 35 by an element isolation method in which a groove formed in a Si substrate is filled with an insulating material. In such a case, the connecting portion 24 between the capacitor electrode 23 and the substrate 4
can be made larger.

Figure 6 shows a case where the separation groove is made even deeper, and the insulating material 36 is deeper than the concave part of the capacitor.
When the recess 2 is formed as shown in FIG.
, and use the substrate as one electrode of the capacitor as before. (FIG. 6 is a cross section taken along line B-B in FIG. 7.) In such a case, the alignment margin between the patterns of the island-like regions 30 and the recesses 2 will be small, but if the insulation material 36 or the recesses 2 By making the cross-sectional shape of the capacitor V-shaped, even if the pattern of the recess 2 is located at the end of the island region 30, the capacitor area will not be suddenly reduced.

〔Effect of the invention〕

As described above, according to the present invention, since an insulating film is formed around the concave capacitor, leakage current generated between adjacent capacitors can be eliminated. Therefore, memory cells including concave capacitors can be placed closely together, making it possible to construct a large-scale integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a plan view of a conventional memory cell, FIG. 2 is a sectional view taken along line AA in FIG. 1, FIGS. 3 and 4 are process diagrams showing an embodiment of the present invention, and FIGS. The figure is a sectional view showing another embodiment of the present invention, and FIG. 7 is a plan view of FIG. 6. 1... Capacitor part, 2, 20... Recessed part, 3...
...Contact part, 4...Si substrate, 5, 25...Insulating film for capacitor, 6, 22, 23, 26...
PolySi, 7, 35, 36...field SiO ₂ ,
9... Word line, 12... Bit line, 13... Leak current path, 15, 18, 19... Si ₃ N ₄ , 2
1...SiO ₂ , 30... Island-like region, 31... Concave pattern.

Claims (1)

[Claims] 1. formed close to each other on the surface of a semiconductor substrate,
two or more recesses whose sidewalls are substantially perpendicular to the substrate surface, an insulating film formed on the recess other than the sidewall at the upper end of the recess, and an upper end of the recess formed on the insulating film; a capacitor having a first electrode electrically connected to the substrate at a side wall portion of the capacitor, an insulating film formed on the first electrode, and a second electrode formed at a predetermined position on the insulating film. A semiconductor device characterized by: 2. A step of forming a recess in a semiconductor substrate so as to span the edge of an island region separated by an insulating film, a step of covering the inner surface of the recess with an insulating film, and a step of forming a recess for a lower electrode of a capacitor on the insulating film. A step of forming a film and electrically connecting the semiconductor substrate in the island-like region with the side wall portion of the upper end of the recess, and a step of forming an insulating film for a capacitor and a film for an upper electrode on the film for the lower electrode. A method for manufacturing a semiconductor device, comprising: