JPH0729992A - Memory cell structure of dynamic ram and its manufacturing method - Google Patents

Abstract

PURPOSE:To enhance the bond leak characteristics by using an SOI structure and also simplify a manufacturing process without forming a deep groove. CONSTITUTION:An active area 12 is formed in a buried state on the upper surface side of an insulation layer 11 and a groove 13 is formed in the insulation layer 11 in its side periphery, and a gate electrode 15 is formed on the active area 12 side in its inside via a gate insulation film 14, and also a source area 16 is formed on the upper layer side of the active area 12, and further a drain area 17 is formed on the lower layer side of the active area 12, to constitute a transistor 2. Further, a node electrode 21 connecting to a lower part of the drain area 17 is provided and a capacitor insulation film 22 is formed in its surface and a plate electrode 23 is formed covering it, to constitute a capacitor 3, and further a substrate 31 is adhered to a lower surface of a plate electrode 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM memory cell structure and a method for manufacturing the same, and more particularly to a dynamic RAM memory cell structure in which transistors and capacitors are formed in a vertical structure by using a bonded substrate and the same. It relates to a manufacturing method.

[0002]

2. Description of the Related Art One example of a conventional memory cell having a vertical transistor will be described with reference to the schematic sectional view of FIG.

As shown in the figure, a p-type diffusion layer 62 and ap ⁺ -type diffusion layer 63 are formed on the upper side of the silicon substrate 61. An element isolation region 65 is formed on the upper layer of the p-type diffusion layer 62 so as to surround a side periphery of a plurality of element formation regions 64, and a groove 66 is formed in the central portion of the element formation region 64. . An n ⁺ type diffusion layer 67 is formed in the upper layer of the p type diffusion layer 62 on both sides of the groove 66. The n ⁺ type diffusion layer 67 also serves as the bit line and the drain region of the transistor.

Further, the p ⁺ type diffusion layer 63 and the p above it are formed.
On the inner wall of the groove 66 in the lower layer of the mold diffusion layer 62,
A capacitor insulating film 68 is formed. Further groove 66
An n ⁺ type diffusion layer 69 is buried inside the capacitor via a capacitor insulating film 68. The upper part of the n ⁺ type diffusion layer 69 is connected to the p type diffusion layer 62, and a part of the impurities of the n ⁺ type diffusion layer 69 is diffused into the p type diffusion layer 62 to make contact with the silicon substrate 61. Is formed.
The upper part of the n ⁺ type diffusion layer 69 also serves as the source region of the transistor.

As described above, the p ⁺ type diffusion layer 63, the capacitor insulating film 68 and the n ⁺ type diffusion layer 69 form the capacitor 70.

Further, a gate insulating film 71 is formed on the inner wall on the upper side of the groove 66 and the upper surface of the capacitor 70. Further, a word line 72 made of an n ⁺ type polysilicon layer is formed. The word line 72 between the n ⁺ type diffusion layer 67 and the n ⁺ type diffusion layer 69 becomes the gate electrode 73. The channel region is formed in the p-type diffusion layer 62 between the n ⁺ -type diffusion layer 67 and the n ⁺ -type diffusion layer 69.

As described above, the n ⁺ type diffusion layer 67 and n
^{The +} type diffusion layer 69 and the gate electrode 73 form a transistor 74. Therefore, the memory cell 75 of the DRAM includes the capacitor 70 and the transistor 7.
4 and.

A dynamic RAM (hereinafter referred to as DR
A method of manufacturing the memory cell 75 (referred to as AM) will be briefly described with reference to manufacturing process diagrams shown in FIG. The same components as those described in FIG. 5 are designated by the same reference numerals.

As shown in FIG. 6A, a silicon substrate 61 has a p-type diffusion layer 62 and a p ⁺ -type diffusion layer 6 below the p-type diffusion layer 62.
And 3 are formed. First, such a silicon substrate 6
An element isolation region 65 that divides the element formation region 64 is formed on the p-type diffusion layer 62 of No. 1 by, for example, the LOCOS method. Further, the p-type diffusion layer 6 is formed by the ion implantation method.
An n ⁺ type diffusion layer 67 which also serves as a bit line and a drain region of the transistor is formed on the upper layer of 2. Further, by photolithography and etching, the p-type diffusion layer 62 in the central portion of the element formation region 64 is penetrated to the p-type diffusion layer 62.
^A groove 66 reaching the ⁺ type diffusion layer 63 is formed. This groove 66
Is formed to a depth of about 8 μm, for example. Further, a capacitor insulating film 68 is formed on the inner wall of the groove 66 and the upper layer of the n ⁺ type diffusion layer 67 by a thermal oxidation method or a CVD method.
To form.

Then, as shown in FIG. 6B, polysilicon containing phosphorus, for example, is buried in the trench 66 by, eg, CVD method. Then, polysilicon having a depth of about 1 μm to 2 μm above the groove 66 is removed by etching back, and an n ⁺ type diffusion layer 69 made of the above polysilicon is formed inside the groove 66. This n ⁺ type diffusion layer 6
9 becomes a capacitor electrode. Further, the exposed capacitor insulating film 68 (the portion indicated by the chain double-dashed line) is removed by etching. At this time, the n ⁺ type diffusion layer 69
The capacitor insulating film 68 on the upper peripheral side is also removed, and an undercut portion 76 is formed.

Next, as shown in FIG. 6C, the undercut portion 76 of the groove 66 is formed by, for example, the CVD method.
Then, non-doped polysilicon is deposited in a state of being buried, and then etched back to form a polysilicon layer 77 on the n ⁺ type diffusion layer 69. This polysilicon layer 7
In FIG. 7, impurities are diffused from the n ⁺ type diffusion layer 69, and n ⁺
The silicon substrate 61 becomes a part of the type diffusion layer 69, and a part of the diffused impurities diffuses into the p-type diffusion layer 62.
To form a contact with. Also, the n ⁺ type diffusion layer 69
Also serves as the source region of the transistor. As described above, the p ⁺ type diffusion layer 63, the capacitor insulating film 68, and the n ⁺ type diffusion layer 69 form the capacitor 70.

Thereafter, as shown in FIG. 6 (4), a gate insulating film 71 is formed on the inner wall of the groove 66 by, for example, a thermal oxidation method or a CVD method. Further, an n ⁺ type polysilicon layer 78 is formed on the surface of the gate insulating film 71.
Then, patterning is performed by photolithography and etching to form the word line 72 with the n ⁺ type polysilicon layer (78). Of the word lines 72, the word line 72 between the n ⁺ type diffusion layer 67 and the n ⁺ type diffusion layer 69 becomes the gate electrode 73. As described above, the n ⁺ type diffusion layer 67, the n ⁺ type diffusion layer 69, and the gate electrode 73 form the transistor 74. In addition, a channel (not shown) is provided in the n ⁺ type diffusion layer 67 and the n ⁺ type diffusion layer 67.
The p-type diffusion layer 62 is formed between the p-type diffusion layer 69 and the type diffusion layer 69.

Next, an example of a memory cell structure of a DRAM having an SOI structure will be described with reference to the schematic block diagram of FIG.
In the figure, (1) shows a schematic sectional view, and (2) shows a partially cutaway schematic perspective view.

As shown in the drawing, an n ⁺ type diffusion layer 82 and ap ⁺ type diffusion layer 83 are formed on the upper layer of the p type silicon substrate 81 from the upper side. Further, a groove 84 reaching the p ⁺ type diffusion layer 83 through the n ⁺ type diffusion layer 82 is formed. A capacitor insulating film 85 is formed on the inner wall of the groove 84. Further, a plate electrode 86 is formed inside the groove 84 with a capacitor insulating film 85 interposed therebetween.
The plate electrode 86 is also partially formed on the upper side of the n ⁺ type diffusion layer 82 with the insulating film 87 formed therebetween.

As described above, the n ⁺ type diffusion layer 82, the capacitor insulating film 85 and the plate electrode 86 form a capacitor 88.

Further, an insulating film 89 is formed so as to cover the capacitor 88. The insulating film 89 is made of, for example, silicon oxide. The n ⁺ type diffusion layer 8
A contact hole 90 is formed in the insulating film 89 above 2. Further, inside the contact hole 90 and on the upper surface of the insulating film 89, an active region 91 is formed by changing an amorphous silicon layer deposited by the CVD method into a crystalline silicon layer by the solid phase growth method, for example. Thus, the active region 91 made of the crystalline silicon layer and the insulating film 89 form an SOI structure.

A word line (93) is formed on the active region 91 via a gate insulating film 92. A part of the word line (93) becomes the gate electrode 94.
The active regions 91 on both sides of the gate electrode 94
A source region 95 and a drain region 96 are formed in the. The source region 95 is connected to the n ⁺ type diffusion layer 82 through the contact hole 90. The transistor 97 is configured as described above.

Further, an interlayer insulating film 98 is formed so as to cover the transistor 97. This interlayer insulating film 98
The upper surface of the interlayer insulating film 98 on the drain region 96.
A bit line 100 connected to the drain region 96 is formed through the contact hole 99 formed in FIG.
The DRAM memory cell 101 is configured as described above.

[0019]

However, in the memory cell structure of the DRAM described with reference to FIG. 5, it is difficult to controllably bury polysilicon in the trench (trench), and it is also difficult to form a refill contact. . Further, since the transistor is a bulk transistor, the junction leak is large. Further, in the memory cell structure of the DRAM described with reference to FIG. 7, since the SOI structure can suppress the junction leak, it is necessary to form the single crystal silicon layer on the insulating film. It is very difficult to uniformly manufacture a single crystal silicon layer, and it is almost impossible at present. Therefore, a polycrystalline silicon layer composed of large crystal grains is usually formed.

The present invention utilizes the SOI structure to prevent a junction leak and has a simple manufacturing process.
An object of the present invention is to provide an AM memory cell structure and a manufacturing method thereof.

[0021]

SUMMARY OF THE INVENTION The present invention is a memory cell structure of a dynamic RAM and a method of manufacturing the same for achieving the above object. The memory cell structure of the dynamic RAM is formed such that the active region is embedded on the upper surface side of the insulating layer. A groove is formed in the insulating layer on the side periphery of the active region,
A gate electrode is formed on the side periphery of the active region inside the gate electrode via a gate insulating film. A source region is formed on the upper side of the active region on one side of the gate electrode, and a drain region is formed on the lower side of the active region on the other side of the gate electrode. The transistor is configured in this way. Further, a node electrode having a capacitor insulating film formed on the surface is formed below the active region to connect to the drain region, and a plate electrode with a flat lower surface is formed to cover the capacitor insulating film side. Has been formed. The capacitor is configured in this way. Further, a substrate is attached to the lower surface of the plate electrode.

In the manufacturing method, first, in a first step, an island-shaped active region is formed in the semiconductor substrate on the upper surface side of the semiconductor substrate. Next, in a second step, after forming an insulating layer in a state of covering the active region, forming a node electrode connected to the active region through the insulating layer, and then forming a capacitor insulating film on the surface of the node electrode, A plate electrode is formed so as to cover the capacitor insulating film, and an upper surface of the plate electrode is made flat.
Subsequently, in a third step, after the substrate is attached on the plate electrode, the semiconductor substrate is removed leaving the active region.
Further, in a fourth step, conductive impurities are introduced into the upper layer and the lower layer of the active region to form the source region and the drain region. Then, in a fifth step, after forming a groove in the insulating layer on the side periphery of the active region, a gate insulating film is formed at least on the side periphery of the active region, and a gate electrode is formed on the side periphery of the gate insulating film inside the groove. To form.

[0023]

In the memory cell structure of the DRAM having the above structure, the junction leak is reduced by forming the active region in which the source region and the drain region are formed by the semiconductor substrate made of, for example, single crystal silicon.

In the above manufacturing method, by forming an island-shaped active region on the upper surface side of the semiconductor substrate, the active region is formed by a semiconductor substrate made of, for example, single crystal silicon. Since this active region is formed as the transistor of the memory cell, the junction leak is reduced. In addition, a node electrode connected to the active region is formed, then a capacitor insulating film is formed on the surface of the node electrode, and then a plate electrode is formed so as to cover the capacitor insulating film and have a flat upper surface. After sticking the substrate on the plate electrode, the semiconductor substrate is removed leaving the active region to form a capacitor. Therefore, it is not necessary to form a deep groove (trench) to form the capacitor, which facilitates the formation of the capacitor.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the figure, on the upper surface side of the insulating layer 11, the active region 1 is embedded in the insulating layer 11.
2 is formed. The insulating layer 11 is made of, for example, silicon oxide. The active region 12 is made of, for example, single crystal silicon.

A groove 13 is formed in the insulating layer 11 on the side periphery of the active region 12, and a gate insulating film 14 is formed inside the groove 13 and on the side periphery of the active region 12. There is. The gate insulating film 14 is made of, for example, silicon oxide. Furthermore, the gate electrode 1 is formed in a state where the inside of the groove 13 is embedded through the gate insulating film 14.
5 is formed. The gate electrode 15 is made of, for example, polycrystalline silicon.

A source region 16 formed by introducing conductive impurities is formed on one side of the gate electrode 15 and above the active region 12. In addition, on the other side of the gate electrode 15 below the active region 12,
A drain region 17 formed by introducing conductive impurities is formed. As described above, the transistor 2 forming the memory cell 1 of the DRAM is formed. Therefore, the active region 12 of the transistor 2 has the insulating layer 11
Since it is formed on the upper surface of, the portion has an SOI structure.

A node electrode 21 connected to the drain region 17 is formed on the lower surface side of the active region 12. The node electrode 21 has a substantially inverted concave cross section, and is made of, for example, polycrystalline silicon. A capacitor insulating film 22 is formed on the surface of the node electrode 21. This capacitor insulating film 22 is
For example, it is made of silicon oxide. The capacitor insulating film 2
A plate electrode 23 is formed so as to cover 2. The plate electrode 23 has a flat lower surface, and is made of, for example, polycrystalline silicon. As described above, the capacitor 3 forming the memory cell 1 of the DRAM is formed.

Further, on the lower surface of the plate electrode 23,
The substrate 31 is attached. The substrate 31 is made of, for example, single crystal silicon. The substrate 31 is not limited to single crystal silicon as long as it is made of a material that can be attached to the lower surface of the plate electrode 23.

Further, an interlayer insulating film 41 made of, for example, silicon oxide is formed so as to cover the active region 12 side. A contact hole 42 is formed in the interlayer insulating film 41 on the active region 12.
Then, the active area 1 is formed through the contact hole 42.
The bit line 43 connected to the source region 16 formed in 2
Are formed on the interlayer insulating film 41. The bit line 43 is formed of a metal having excellent conductivity (for example, an aluminum-based metal).

As described above, the memory cell 1 of the dynamic RAM (hereinafter referred to as DRAM) is constructed.

In the structure of the memory cell 1 of the DRAM having the above structure, the active region 12 in which the source region 16 and the drain region 17 are formed is formed of a semiconductor substrate made of, for example, single crystal silicon, so that the transistor 2 is formed.
The junction leak is reduced.

Next, the method of manufacturing the memory cell structure of the DRAM will be described with reference to manufacturing process diagrams (part 1) of FIGS.
(Part 2) and (Part 3) will be described. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2A, in the first step, an etching mask 52 is formed on the upper surface side of the semiconductor substrate 51 by the usual resist coating technique and photolithography technique. Then, the semiconductor substrate 5 is subjected to normal etching (for example, reactive dry etching).
The part indicated by the two-dot chain line 1 is removed, and the island-shaped active region 12 is formed on the remaining semiconductor substrate (51). Then, the etching mask 52 is removed by a normal asher process or wet etching.

Then, the second step shown in FIG. 2B is performed. In this step, the active region 12 is formed by a normal chemical vapor deposition method (hereinafter referred to as a CVD method), for example.
The insulating layer 11 is formed so as to cover the.

Then, a contact hole 24 is formed in the insulating layer 11 on the active region 12 by the usual photolithography technique and etching. After that, by asher processing or wet etching,
The etching mask (not shown) is removed.

Then, a node electrode forming film 25 made of polycrystalline silicon is deposited by the CVD method. Further CV
The insulating film 26 made of silicon oxide is formed by the D method.

Then, as shown in FIG. 2C, the node electrode forming film 25 (the portion indicated by the one-dot chain line) and the insulating film 26 (the portion indicated by the two-dot chain line) are formed by ordinary photolithography and etching. ) Are removed, and the node electrode forming film 25 and the insulating film 2 are formed on the active region 12.
Leave 6 and.

Further, as shown in FIG. 2D, the remaining node electrode forming film 25 and insulating film 26 are formed by the usual film forming and sidewall forming technique by etching back.
And a sidewall 2 made of polycrystalline silicon on the side wall of
Form 7. In this way, the remaining node electrode forming film 25 and the sidewall 27 form the node electrode 21 connected to the active region 12 through the contact hole 24.

After that, as shown in FIG. 3 (5), a resist film 28 is formed by a resist coating technique so as to cover the node electrode 21, and then the resist film on the node electrode 21 is formed by a photolithography technique. 28
The upper layer of the resist film 28 (the portion indicated by the two-dot chain line) around it (the portion indicated by the two-dot chain line) is removed. Then, the remaining insulating film 26 is removed by etching. After that, the resist film 28 is removed by asher processing or wet etching.

Next, as shown in (6) of FIG. 3, a capacitor insulating film 22 is formed on the surface of the node electrode 21 by a thermal oxidation method or a CVD method.

Further, a plate electrode 23 made of, for example, polycrystalline silicon is formed by the CVD method so as to cover the capacitor insulating film 22 side. Then, the upper surface of the plate electrode 23 is flattened by a precision polishing method (for example, mechanochemical polishing or polishing).
As described above, the capacitor 3 is formed by the node electrode 21, the capacitor insulating film 22 and the plate electrode 23.

Subsequently, the third step shown in FIG. 3 (7) is performed. In this step, a substrate 31 made of, for example, single crystal silicon is bonded to the upper surface of the plate electrode 23 by a normal wafer bonding technique. Further, the semiconductor substrate 51 (portion indicated by a chain double-dashed line) is removed by leaving the active region 12 by a precision polishing method (for example, mechanochemical polishing or polishing).

Next, the fourth step shown in FIG. 3 (8) is performed. Subsequent drawings are from (1) of FIG. 2 to (7) of FIG.
The drawings shown up to now are shown upside down. In this step, the source region 16 and the drain region 17 are formed by introducing a conductive impurity into the upper layer and the lower layer of the active region 12 by a normal ion implantation method. To form the drain region 17, for example, conductive impurities contained in the node electrode 21 may be diffused.

Subsequently, as shown in FIG. 4 (9), in a fifth step, the insulating layer 11 on the side periphery of the active region 12 is formed by the usual photolithography technique and etching.
A groove 13 is formed in the groove. As shown in the layout diagram of (10) of FIG. 4, the groove 13 is formed so as to surround the side circumferences of the 12 columns of the active regions forming the memory cell array.
3a is formed and the groove 1 is connected to each groove 13a.
3b is formed. In this way, the groove 13a and the groove 13b
The groove 13 is formed by and. The groove 13 is formed to be shallower than the bottom surface of the active region 12.

Subsequently, as shown in (11) of FIG. 4, the gate insulating film 14 is formed at least on the side periphery of the active region 12 by the thermal oxidation method or the CVD method.

Further, a gate electrode forming film 53 made of, for example, polycrystalline silicon is formed by the CVD method so as to fill the groove 13. After that, a portion indicated by a chain double-dashed line of the gate electrode forming film 53 is removed by a normal etchback technique, and the gate electrode 15 is formed while leaving the gate electrode forming film (53) inside the groove 13. At this time, the height of the gate electrode 15 is equal to that of the active region 1
It is formed in a state lower than the height of 2. As described above, the gate electrode 15, the gate insulating film 14, and the source region 1
A transistor 2 having 6 and a drain region 17 is formed.

Further, the sixth step shown in FIG. 4 (12) is performed. In this step, the interlayer insulating film 41 covering the gate electrode 15, the gate insulating film 14, and the source region 16 is formed by, for example, the CVD method.

Thereafter, the interlayer insulating film 4 on the source region 16 is formed by photolithography and etch back.
A contact hole 42 is formed at 1. Further, the bit line 43 connected to the source region 16 of the active region 12 through the contact hole 42 is formed by a normal wiring forming technique. As described above, the DRAM memory cell 1 is formed.

In the above manufacturing method, the island-shaped active region 12 of the semiconductor substrate 51 is provided on the upper surface side of the semiconductor substrate 51.
Thus, the active region 12 is formed by the semiconductor substrate 51 made of, for example, single crystal silicon. Since the active region 12 serves as the channel of the transistor 2 of the memory cell, the junction leak is reduced.

Further, after forming the node electrode 21 connected to the active region 12 and then forming the capacitor insulating film 22 on the surface of the node electrode 21, the capacitor insulating film 22 is covered and the upper surface side is flat. After the plate electrode 23 is formed and the substrate 31 is attached on the plate electrode 23, the semiconductor substrate 51 is removed leaving the active region 12 to form the capacitor 3. Therefore, since it is not necessary to form a deep groove (trench) to form the capacitor 3, the capacitor 3 can be easily formed.

[0052]

As described above, according to the present invention,
Since the active region in which the source region and the drain region are formed is formed on the insulating layer, the active region and the insulating layer form an SOI structure. Therefore, junction leakage can be reduced, so that electrical characteristics of the transistor can be improved.

In the above manufacturing method, since the island-shaped active region is formed on the semiconductor substrate, the active region can be formed on the single crystal silicon substrate. Further, since the source and drain regions are formed in the active region, the junction leak of the formed transistor can be reduced. In addition, since the node electrode is formed in the active region, the capacitor insulating film is formed on the surface of the active region, the plate electrode is formed to cover the capacitor insulating film, and the capacitor is formed. You don't have to. Therefore, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an example.

FIG. 2 is a manufacturing process diagram (1) of the embodiment.

FIG. 3 is a manufacturing process diagram (2) of the embodiment.

FIG. 4 is a manufacturing process diagram (3) of the embodiment.

FIG. 5 is a schematic configuration sectional view of a conventional example.

FIG. 6 is a manufacturing process diagram of a conventional example.

FIG. 7 is another schematic configuration diagram of a conventional example.

[Explanation of symbols]

 1 Memory Cell 2 Transistor 3 Capacitor 11 Insulating Layer 12 Active Region 13 Groove 14 Gate Insulating Film 15 Gate Electrode 16 Source Region 17 Drain Region 21 Node Electrode 22 Capacitor Insulating Film 23 Plate Electrode 31 Substrate 51 Semiconductor Substrate

Claims (2)

[Claims] 1. An active region formed in a state of being buried in an upper surface side of an insulating layer, a groove formed in the insulating layer on a side periphery of the active region, and a side periphery of the active region in the groove. A gate insulating film, a gate electrode formed on a side circumference of the gate insulating film so as to fill the trench, a source region formed on one side of the gate electrode above the active region, and a gate electrode of the gate electrode. A transistor having a drain region formed on a lower layer of the active region on the other side, a node electrode connected to the drain region and formed on a lower side of the active region, and a capacitor insulation formed on a surface of the node electrode. A film and a plate electrode formed so as to cover the capacitor insulating film side and having a flat lower surface side. Memory cell structure of a dynamic RAM, characterized in that it comprises a capacitor, and a substrate bonded to the lower surface of the plate electrode. 2. The method for manufacturing a memory cell structure of a dynamic RAM according to claim 1, wherein a first step of forming an island-shaped active region in the semiconductor substrate on the upper surface side of the semiconductor substrate; After forming an insulating layer on the semiconductor substrate so as to cover the capacitor, a node electrode connected to the active region through the insulating layer is formed, and then a capacitor insulating film is formed on the surface of the node electrode, and then the capacitor insulating film is formed. A second step of forming a plate electrode in a state of covering the film and forming an upper surface side of the plate electrode in a flat state; and bonding the substrate on the plate electrode, and then leaving the active region to leave the semiconductor substrate A third step of removing the source region and the source region and the drain region by introducing conductive impurities into the upper layer and the lower layer of the active region. Forming a groove in the insulating layer on the side periphery of the active region, forming a gate insulating film on at least the side periphery of the active region, and further forming a gate periphery on the side periphery of the gate insulating film. A method of manufacturing a memory cell of a dynamic RAM, which comprises performing a fifth step of forming a gate electrode inside the groove.