JPH04255129A - Control circuit for time division multiplex communication line - Google Patents

Abstract

PURPOSE:To detect a data quickly and to control a line fast even at production of a code error by providing a logic circuit controlling a clock or a synchronizing pulse to a consecutive (n) detection circuit depending on the result of discrimination of a parity check circuit to the system. CONSTITUTION:An AND circuit 104 connecting to a clock terminal C of each of DFFs 103A-C ANDs a frame pulse 12 and an output 13 of a parity check circuit 102. Suppose that a same data A not including a code error by two frames continuously from a data input terminal A is inputted to FFs 103A, B. When a circuit 102 receiving a data including a code error detects an error, the output 13 goes to an L level and since no clock enters the FFs 103A-C, a data including an error is not inputted. Then the data A is again received and inputted to the FFs 103A-C, a data of three consecutive frames is detected. Thus, even when a code error takes place, the line is quickly controlled with a delay by an error frame.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex communication line control circuit, and more particularly to a time division multiplex communication line control circuit that improves delay in line control due to delay in line data error detection.

0002

2. Description of the Related Art Generally, in time division multiplex communication, a transmission frame contains line control data for controlling a communication line, and it is extremely important to accurately detect this data. Therefore, regarding line control data, in order to avoid the influence of code errors caused by attenuation in the transmission path, mixing of external noise, etc., it is conventional to use n(n
= integer) A continuous detection circuit has been used.

[0003] Here, the n consecutive detection circuit determines that data has been detected for the first time when the parity check result is normal and the same data is received n times in a row. In this method, if the system does not have a multi-frame configuration, a parity bit is first added to the line control data on the data sending side so that the entire line control data within one frame has an even or odd parity. On the receiving side, the parity of the line control data of the received data is checked and compared with the received parity bit. If the two match, it is determined that all the received line control data is correct; if they do not match, it is determined as a parity error. I judge that. If this parity bit is normal n times in a row, and the received line control data is also logical “1” or “0” n times in a row, it is assumed that the line control data “1” or “0” has been received correctly. there was.

Conventionally, three consecutive detection circuits (n=3) in this type of time division multiplex communication line control circuit include a frame synchronization separation circuit 201, a parity check circuit 202, and a control data detection circuit, as shown in FIG. It is composed of a D-flip D-flop group 203, a D-flip-flop group 204 for detecting control data after passing through the parity check circuit 202, and a logic circuit 209 for logically determining the detection results of both. Furthermore, the frame structure of the data input from the data input terminal A is as shown in FIG. It consists of Furthermore, as shown in FIG. 5(a), for example, the bit structure within one frame is an 8-bit structure consisting of 1 frame bit, 5 information bits, 1 control data bit, and 1 parity check bit. Illustrate.

In FIG. 4, first, a frame synchronization separation circuit 201 converts received data (see FIG. 5) into line control data 2.
1. A frame pulse 22 is generated by separating the parity check bit and other bits and taking in the frame bit. The line control data 21 is sent to the D flip-flop 203, and the control data bit and parity check bit are combined and sent to the parity check circuit 203.
Sent to 2. If no error is detected by the parity check circuit 202, the parity check output signal 23 becomes high level. A frame pulse is used as a clock for the D flip-flop 203, and when this pulse is input, the output Q of the D flip-flop 203A becomes high level. At this time, line control data is also latched. If there is no parity error for three consecutive frames, the outputs Q of the D flip-flops 204A, B, and C are all at high level, and the output of AND208 is at high level. In the conventional example, it is assumed that normal parity is detected at this point. At this time, if the high level or low level of the line control data is detected for three consecutive frames, the data detection signal of the data output terminal D is output, and the output of the control data output terminal C of the D flip-flop 203 is used as the detection data. I reckon.

Next, the operation regarding the time required for parity check will be explained. Now, if no error is detected in the parity check circuit for two consecutive frames and the data is the same, the first stage 203A, 204A, second stage, and 203B of the upper and lower two groups of D flip-flops 203, 204 in FIG. , 204B are input with the line control data and the output high level of the parity check circuit 202, respectively. Normally, if the same data is received one more time and the outputs Q of each of the three D flip-flops in both groups match, it can be considered as data detection. If the time required to receive one batch of data is T, then the time required for detection is 3T.
It is. However, the third received data contains a code error,
When an error is detected in the parity check circuit,
The data detection signal becomes low level. Even if no error is detected in the next data, the data will not be detected unless the same data is received for a total of three consecutive frames. In this case, the time required for detection was 6T. That is, in the n consecutive detection circuit, the detection time required for a single parity error is 2nT at maximum, causing a delay in line control when an error occurs.

[0007]

[Problems to be Solved by the Invention] In the case of the n consecutive detection circuits used in the conventional time-division multiplex communication line control circuit described above, after detecting an error in the parity check circuit, the same Since it is considered that data is detected only when data is received, there is a drawback that the time required for detection is long. Therefore, a delay in detecting line control data for a communication line means a delay in line control, which is a drawback.

[0008]

Means for Solving the Problems The time division multiplex communication line control circuit of the present invention provides a time division multiplex communication line for transmitting an input data signal in which line control data including parity check data is included in the same frame as an information channel. In the line control circuit, a frame synchronization and separation circuit performs frame synchronization and separation/extraction of the line control data, a parity check circuit performs a parity check of the extracted line control data, and the frame synchronization and separation circuit An AND circuit inputs a synchronized clock signal as an output and a normal or abnormal signal of the parity check result of the parity check circuit, and a clock output from this AND circuit. and an n consecutive detection circuit that detects a match consecutively (integer) times, and only when the parity check circuit detects an abnormality in the parity check, data is not sent to the n consecutive detection circuit and the determination of n consecutive matches is omitted. I'm there.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In addition, the input data signal is as shown in FIG. 5 (a) explained in the conventional example.
). The embodiment of FIG. 1 has a frame synchronization separation circuit 101, a parity check circuit 102, and 3 flip-flops 103A to 103C when n=3.
It is composed of a D flip-flop group 103 which is a continuous detection circuit, two AND circuits 104 and 105, a NOR circuit 106, and an OR circuit 107, which will be described later.

Next, the operation of this embodiment will be explained. In FIG. 1, a common AND circuit 104 is connected to the clock terminal input of each of the flip-flops 103A to 103C. This AND circuit 104 performs a logical product of the frame pulse 12 and the output signal 13 of the parity check circuit 102. Assume that the same data A without code errors is received from data input terminal A for two consecutive frames and input to D flip-flops 102A and 102B. After that, if data containing a code error is received and an error is detected, the output signal 13 of the parity check circuit 102 is
is low level, so the D flip-flop 103C
Because the clock does not enter all D flip-flops including
3A to 103C are not input. Next, the error-free data A is received again and again, and this data is transferred to the D flip-flop 10.
When input to 3A to 103C, three consecutive frame data are detected and data is detected. In other words, in the case of the circuit of this embodiment, even if a code error occurs, the time required for the error frame is delayed, and the total time required for data detection is 4T at most. In this way, in this embodiment, the detection time required for one parity error is (n+1)T.

Next, a second embodiment of the present invention will be explained with reference to the circuit diagram of FIG. 2 and the input data format of FIG. 5(b). In the first embodiment described above, a parity bit for line control data is inserted in every frame. In other words, the case where one word is in one frame is shown, but in the second embodiment, as shown in FIG. An example of application is shown. Now, k (k=2,
3,...) frames constitute one multiframe, and the line control data is m bits in one frame. This also includes a parity check bit and a multiframe pattern bit, and the parity check bit is one bit in one multiframe, and in this embodiment, it is assumed that it is included in the kth frame. In the second embodiment, in addition to the first embodiment, a serial/parallel conversion circuit 109 and a multiframe synchronization detection circuit 111 are required, and each D flip-flop has a reset function in order to reset the output data when multiframe is asynchronous. Requires terminal. Further, k three consecutive detection units 112A to 112C are arranged in parallel in correspondence with line control data. Each of the three consecutive detection units 112A to 112C has a circuit configuration as shown in FIG.

Next, the operation of the second embodiment will be explained. First, the frame synchronization separation circuit 108 extracts line control data from the received signal, and also captures frame bits to generate a frame pattern. Multi-frame synchronization circuit 111
Now, read the multiframe pattern bits in the line control data and establish multiframe synchronization. The output data continues to be reset until synchronization is established, and then multi-frame pulses are output. When k frames of input data signals are received, the serial/parallel conversion circuit 109 converts the line control data for k serial frames into parallel line control data. Here, the line control data to be parallel-converted is from 1 frame to k-
control data bits consisting of m bits up to one frame;
There are two types of parallel data: m-bit control data bits including a parity bit (for example, 1 bit) of the k-th frame. Further, the serial-parallel conversion circuit 109 divides the m-bit control data bits into m-1 control data bits 14A and one control data bit 14B allocated for parity. The parallel-converted km-1 bit data is sent to the three continuous detection circuit section 1.
It is sent to D flip-flops 12A to 112C. D
A multi-frame synchronization pulse 17 is used as a clock for the flip-flop. The AND circuit 114 inputs the output signal 16 of the multi-frame synchronization detection circuit 111 and the output signal 16 of the parity check circuit 110 so as to be valid only when no parity error is detected, performs a logical product, and then outputs the D flip-flop. 112A-112
It is input to C's clock. In this example, since one multi-frame configuration is made up of k frames, data detection is performed at 3kT if there is no code error, and data is detected at 2kT.
After receiving the multiframe, a parity error is detected, and if no error is detected thereafter, it is assumed that data has been detected at 4kT. If we generalize the number of consecutive detections to n, then the time required for data detection is at most (n+1)k due to one parity error.
It becomes T.

[0014] The present invention can also be used when k frames are divided into i (i is a divisor of k) to form a block consisting of k/i frames, and parity bits are added to each block. Can be done.

[0015]

As explained above, in the present invention, by providing a logic circuit that controls the clock or synchronization pulse to the n consecutive detection circuit based on the determination result of the parity check circuit, data detection is possible even when a code error occurs. This has the effect that the required time can be shortened and line control can be performed more quickly. Also, the circuit configuration has the effect of being simpler than the conventional type.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram of main parts of a second embodiment.

FIG. 4 is a circuit diagram of a conventional time division multiplex communication line control circuit.

FIG. 5(a) is a frame data format diagram common to the conventional example and the present embodiment, and FIG. 5(b) is a diagram showing a multi-frame data format.

[Explanation of symbols]

101, 108, 201 Frame synchronization separation circuit 102, 110, 202 Parity check circuit 103, 203, 204 D flip-flop group 103A to C D flip-flop 104, 10
5, 113, 205, 208, 209 AND circuit 106, 206 NOR circuit 107, 207 OR circuit

Claims (2)

[Claims] 1. A control circuit for a time division multiplex communication line that transmits an input data signal in which line control data including parity check data is included in the same frame as an information channel, frame synchronization and separation/extraction of the line control data. a parity check circuit that performs a parity check on the extracted line control data, and a synchronized clock signal that is an output of the frame synchronization and separation circuit and a parity check result of the parity check circuit. It has an AND circuit that inputs a normal or abnormal signal, and an n consecutive detection circuit that is operated by a clock output from this AND circuit and detects that the line control data matches n times in succession (n is an integer). A control circuit for a time-division multiplex communication line, characterized in that only when the parity check circuit detects an abnormality in the parity check, data is not sent to the n-consecutive detection circuit and the data is omitted from the determination of n-consecutive matches. 2. In a time division multiplex communication line control circuit for transmitting an input data signal having a multi-frame configuration, the frame including at least one frame containing line control data having parity check data, the output signal of the frame synchronization and separation circuit. a multi-synchronization detection circuit that extracts a multi-frame synchronization signal from the multi-frame synchronization detection circuit; and a serial-parallel conversion circuit that converts the serial output signal of the separation circuit into a parallel signal, and n (n is an integer) consecutive matches only when the parallel output signal of this serial-parallel conversion circuit is input and a synchronization signal is input from the AND circuit. 2. The time-division multiplex communication line control circuit according to claim 1, further comprising a plurality of n consecutive detection circuit units for making determinations.