JPH04252515A - Semiconductor integrated circuit and microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits and microcomputers, and more particularly to semiconductor integrated circuits and microcomputers having both logic and memory functions that can be changed in the field.

0002

[Prior Art] A PLD (programmable logic device) is known as a semiconductor integrated circuit having a logic function that can be changed in the field.
This method is disclosed in Japanese Patent Application Laid-open No. 919, Japanese Patent Application Laid-Open No. 61-292412, Japanese Patent Application Laid-open No. 198919-1987, and the like.

[0003] Furthermore, a microcomputer whose logical functions such as input/output can be changed in the field was published in Japanese Patent Laid-Open No.
This method is disclosed in Japanese Patent Application No. 162971, Japanese Patent Application No. 63-244156, etc.

On the other hand, semiconductor integrated circuits having a memory function include ROM (read only memory) and PROM.
Memory devices such as (programmable read-only memory) and RAM (random access memory) are known.

[0005]

[Problem to be solved by the invention] JP-A-62-1989
The PLDs disclosed in Japanese Patent Application Laid-open No. 19, No. 61-292412, Japanese Patent Laid-open No. 61-198919, etc. only have a logic function and do not have a memory function that can be used as a memory. do not have. Therefore, if the system runs out of memory, it is necessary to add a separate memory circuit even if the PLD has excess logic functions.
There is a problem that causes waste.

Furthermore, the microcomputers disclosed in Japanese Patent Application Laid-open No. 1-162971 and Japanese Patent Application No. 63-244156 have a built-in logic function part that can be changed in the field, but the logic function part is stored in memory. It cannot be used as. Therefore, if there is a shortage of memory in the system, it is necessary to add a separate memory circuit even if the built-in logic function part is surplus, and the above PLD
As in the case of , there are problems that result in waste.

On the other hand, conventional memory devices can realize logic functions in addition to memory functions, but since there are significant restrictions on realizing logic functions, if they are used as logic circuits, the efficiency will be extremely low. . Therefore, even if there is excess memory function, it is necessary to add a separate logic circuit, resulting in a problem of waste.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit having both a logic function and a memory function that can be changed in the field so that it can be efficiently used as either a logic circuit or a memory circuit. It is in. Another object of the present invention is to provide a microcomputer that includes a built-in part that has both a logical function and a memory function that can be changed in the field.

[0009]

[Means for Solving the Problems] In a first aspect, the present invention provides a combinational circuit array including a plurality of combinational circuits of memory cells and switching elements, and a combinational circuit that is used as a logic circuit or as a memory circuit. The present invention provides a semiconductor integrated circuit characterized by including a combinational circuit block including a control means for controlling whether to use the combinational circuit block.

In a second aspect, the present invention provides a microcomputer further comprising a processor (6) for data processing on the same semiconductor substrate as the semiconductor integrated circuit according to the first aspect. provide.

[0011]

[Operation] The semiconductor integrated circuit according to the first aspect has both a logic function and a memory function because the combinational circuit is constituted by a combination of memory cells and switching elements. The control means allows selection in the field of which function to use, the logic function or the memory function. Therefore, it can be efficiently used for either logic circuits or memory circuits.

[0012] In the microcomputer according to the second aspect, since the combinational circuit block and the processor, which can be efficiently used for either logic circuits or memory circuits, are on one chip, the necessary logic functions and memory areas are combined into the combinational circuit block. This makes it possible to eliminate unnecessary additional circuits.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 shows the configuration of a microcomputer 1 according to an embodiment of the present invention. This microcomputer 1 has a common bus 2, a processor 6, a variable circuit 7, an input/output circuit 8, and a system control circuit 9 formed on the same semiconductor substrate.

The common bus 2 includes an address bus, a data bus, a control bus, and the like. The control bus includes read signal lines, write signal lines, and the like.

[0015] The processor 6 includes a CPU 3 and an EPROM.
(Electrically writable read-only memory) 4,
RAM (Random Access Memory) 5, which are connected to the common bus 2 by bus lead lines 16, 17, and 18, respectively.

[0016] In normal operation, the CPU 2 uses the EPROM 4
The program stored in the RAM 5 is read out via the common bus 2, and the program is read out from the RAM 5 via the common bus 2 according to the program.
It operates by exchanging data with the input/output circuit 8.

The variable circuit 7 is a programmable circuit that has data set under the control of the system control circuit 9 and can realize various logic functions and memory functions depending on the contents of the data. Its configuration will be detailed later.

The input/output circuit 8 performs data communication between the microcomputer 1 and the outside via an external input/output line 10.

The system control circuit 9 controls the microcomputer 1 to an initial state according to conditions such as a reset input signal line 11 applied to the microcomputer 1 from the outside and power-on, and also initializes the variable circuit 7.

FIG. 2 shows the configuration of the variable circuit 7. The variable circuit 7 includes a combinational circuit block 22, an address selector 23 that selects an address to be input to the combinational circuit block 22, and a memory input/output multiplexer 2 that multiplexes data input to and output from the combinational circuit block 22.
5, a logic input selector 27 that selects a logic input, and a logic output multiplexer 29 that multiplexes logic output data output from the combinational circuit block 22 in accordance with the logic input input from the logic input selector 27;
Each of the selectors 23 and 27 and the multiplexers 25 and 29
It is composed of selection control storage circuits 31, 32, 33, and 34 that hold data for controlling the operation of the .

The combinational circuit block 22 includes an address input line 24 from an address selector 23, a memory data input/output line 26 from a memory input/output multiplexer 25, a logic input line 28 from a logic input selector 27, and a logic output line 24. A logic output line 30 to the multiplexer 29, a write signal line 19w included in the connection line 19 between the variable circuit 7 and the common bus 2, a read signal line 19r, and a data bus 19d (
DB) is connected.

The address selector 23 has an address input line 24 to the combinational circuit block 22 and a data bus 19d (D) included in the connection line 19 between the variable circuit 7 and the common bus 2.
B), the address bus 19a (AB) included in the connection line 19 between the variable circuit 7 and the common bus 2, the input line 21i (IP) included in the connection line 21 between the variable circuit 7 and the input/output circuit 8, and the logic a first output line 29a of the output multiplexer 29;
A control line 31a from the selection control storage circuit 31 is connected thereto.

The memory input/output multiplexer 25 includes a memory data input/output line 26 to the combinational circuit block 22, a data bus 19d (DB) included in the connection line 19 between the variable circuit 7 and the common bus 2, and the variable circuit 7. and an input/output line 21io (IOP) included in the connection line 21 of the input/output circuit 8,
A second output line 29b of the logic output multiplexer 29, an output line 25a to the logic input selector 27, and a control line 32a from the selection control storage circuit 32 are connected.

The logic input selector 27 includes a logic input line 28 to the combinational circuit block 22 and a data bus 19d (DB) included in the connection line 19 between the variable circuit 7 and the common bus 2.
, the address bus 19a (AB) included in the connection line 19 between the variable circuit 7 and the common bus 2, and the address bus 19a (AB) included in the connection line 19 between the variable circuit 7 and the common bus 2.
A control bus 19c (CB) included in the connection line 19 of The third output line 29c of the logic output multiplexer 29 and the control line 33a from the selection control storage circuit 33 are connected.

The logic output multiplexer 29 includes a logic output line 30 from the combinational circuit block 22 and a variable circuit 7.
and the data bus 19d included in the connection line 19 of the common bus 2.
(DB), the output line 21o (OP) included in the connection line 21 between the variable circuit 7 and the input/output circuit 8, and the address selector 2
3, a second output line 29b to the memory input/output multiplexer 25, and a logic input selector 27.
A third output line 29c to and a control line 33a from the selection control storage circuit 33 are connected.

The selection control storage circuit 31 includes a control line 31a to the address selector 23 and a lead line 3 to the common bus 2.
1b is connected. The selection control storage circuit 32 includes:
a control line 32a to the memory input/output multiplexer 25;
A leader line 32b to the common bus 2 is connected. A control line 33a to the logic input selector 27 and a lead line 33b to the common bus 2 are connected to the selection control storage circuit 33. A control line 34 a to the logic output multiplexer 29 and a lead line 34 b to the common bus 2 are connected to the selection control storage circuit 34 .

Data is set in the combinational circuit block 22 by applying a memory address to the address input line 24 and writing data to the memory data input/output line 26. Setting of data in the selection control storage circuits 31-34 is performed via respective leader lines 31b-34b.

FIG. 3 shows the configuration of the combinational circuit block 22. The combinational circuit block 22 includes a large number of combinational circuits 4
A combinational circuit array 35 consisting of 5-1, 45-2, ..., an address decoder 36, and a memory data detection circuit 37
-1, 37-2, . . . , a logic input circuit 38, logic output circuits 39-1, 39-2, . . . , and logic input control storage circuits 40-1, 40-2, .

The address decoder 36 receives the address input line 24 as an input and uses the memory word line 41 as an output. The memory data detection circuits 37-1, 37-2, . . . use the write signal line 19w and the read signal line 19r as inputs, and use the memory data input/output line 26 and the memory data line 42 as input/output. The memory data line 42 is connected to the positive data line p (42p
) and a negative data line n (42n).

The logic input circuit 38 receives the logic input line 28 and the output lines of the logic input control storage circuits 40-1, 40-2, . . . as inputs, and outputs the logic word line 43. The logic word line 43 includes a positive output line P (43P) and a negative output line N (43N).
). Logic input control storage circuit 40-1,
When configuration control data "1" is stored in 40-2,...,
The same logic signal as the input of the logic input line 28 is output to the positive output line P, and an inverted logic signal is output to the negative output line N. On the other hand, when the configuration control data "0" is stored in the logic input control storage circuits 40-1, 40-2,..., both output lines P, N
"0" is output to the logic input line 28, and the input on the logic input line 28 becomes irrelevant. The positive output line P and the negative output line N are respectively input to paired combinational circuits 45-1, 45-2, .

The logic output circuits 39-1, 39-2, . . .
The logic data line 44 is used as an input, and the logic output line 30 is used as an output.

Logic input control storage circuits 40-1, 40-2
,... have the write signal line 19w, read signal line 19r, and data buses 19d-1, 19d-2,... as inputs,
The output line to the logic input circuit 38 is set as an output.

FIG. 4 shows the configuration of combinational circuit 45-1. The memory cell 45-1 is composed of a RAM (random access memory) cell 46 and two transistors 53 and 54. The RAM cell 46 has a first inverter 47 and a second inverter 48 which are cross-coupled.
, the output point 49 of the first inverter 47 and the positive data line 42
The transistor 51 connecting p and the second inverter 48
A transistor 52 connects the output point 50 of the negative data line 42n to the negative data line 42n. Note that the RAM cell 46 is SR
It may be AM or DRAM.

Two transistors 53 and 54 are provided between the logic data line 44 and the ground line 55.

Two transistors 5 in RAM cell 46
Gate electrodes 1 and 52 are connected to the memory word line 41.

The gate electrode of transistor 53 is connected to output point 49 of first inverter 47 . A gate electrode of transistor 54 is connected to logic word line 43P.

Writing data to the RAM cell 46 is as follows:
This is done by applying a signal at the power supply voltage level as a selection signal to the memory word line 41 while providing inverted data (Dp, Dn) to the positive data line 42p and negative data line 42n, respectively. Data is read from the RAM cell 46 by detecting the potentials of the positive data line 42p and negative data line 42n while applying a signal at the power supply voltage level as a selection signal to the memory word line 41. This provides memory functionality.

Furthermore, in the state in which data "1" is written in the RAM cell 46 (the output point 49 is in the state of level "1"),
When the logic word line 43P is selected, the transistors 53 and 54 become conductive, and the logic data line 44 goes to the ground level. On the other hand, when data "0" is written in the RAM cell 46 (output point 49 is at level "0"), the transistor 53 does not become conductive, so even if the logic word line 43P is selected, the logic line 44
does not reach the ground level. This operation and logic output circuit 39
-1 operation (described later) provides a logic function. FIG. 5 shows the configuration of the logic output circuit 39-1. The logic output circuit 39-1 includes a resistor 57 and a detection circuit 56. The resistor 57 connects multiple combinational circuits 45-1, 4
5-2, . The detection circuit 56 has the logic data line 44 as an input and the logic output line 30 as an output.

Now, all the RAs of the combinational circuits 45-1, 45-2, . . . connected to the same logic data line 44
When data "1" is written in the M cell 46, if even one of the logic word lines 43 becomes "1", the logic data line 44 goes to the ground level, so the logic output line 30 receives the logic value "1". 0” is output. On the other hand, when all of the logic word lines 43 are "0", the logic data line 44 does not go to the ground level, so a logic value "1" is output to the logic output line 30. That is, if we focus on the logic block 59,
It has the NOR logic function shown in FIG. however,
Since it is meaningless to NOR both the positive output line P and the negative output line N corresponding to the same logic input I, the paired combinational circuits 45-
Data “0” is stored in one of the RAM cells 46 of 1, 45-2, .
” (This will be explained in detail in the next program example).

FIG. 7 shows a specific example of the program. Logic input control storage circuit 40-1, 40-2, 40-3, 40
-4 as configuration control data “0”, “0”, “1”
", "1". As a result, only I3 and I4 of the logic input lines 28 become valid. Therefore, the 16 combinational circuits 45-1, 45-1 in the upper half of the combinational circuit array 35
45-2, . . . can be used as RAM.

Logic control data is written in the RAM cells 46 of the 16 combinational circuits in the lower half of the combinational circuit array 35 as shown in FIG. In this state, logic blocks L1, L2, L3, and L4 become two-input NOR circuits as shown in FIG. Therefore, the logic inputs I3 and I4 have logic functions as shown in FIG. R of the 16 combinational circuits in the lower half of the combinational circuit array 35
Since the logic control data written in the AM cell 46 can be arbitrarily rewritten, it is also possible to dynamically change the logic functions of the logic blocks L1 to L4.

FIG. 10 shows a detailed configuration of the system control circuit 9 and the common bus 2. The system control circuit 9 includes a reset control circuit 60, an initialization control circuit 61, a power-on reset circuit 62, and a counter 63.

When a power supply voltage is applied to the microcomputer 1, the power-on reset circuit 62 detects the rise of the voltage at a certain voltage level, and generates a power-on reset signal (PR) for a certain period of time. The power-on reset signal (PR) is transmitted to the initialization control circuit 61 via the power-on reset signal line 64.

When the initialization control circuit 61 receives the power-on reset signal (PR), it generates the following control signal. CU signal: A signal for initializing and counting up the counter 63, and is transmitted to the counter 63 via the CU signal line 65. RD signal: This is a read signal for reading the EPROM 4, and is a read signal line 13 in the initialization control output line 13.
The signal is transmitted to the read signal line 2r included in the common bus 2 via the signal line r. WR signal: A write signal for writing to the variable circuit 7, which is a write signal line 13 in the initialization control output line 13.
The signal is transmitted to the write signal line 2w included in the common bus 2 via the write signal line 2w. SE signal: This is a selection signal and is transmitted to the EPROM 4. SR signal: This is a selection signal and is transmitted to the variable circuit 7. IE signal: Initialization end signal, initialization end signal line 6
6 to the reset control circuit 60.

Based on the CU signal, the counter 63
Generates the address of EPROM 4 at initialization. Also,
The addresses of the combinational circuits 45-1, 45-2, . . . of the variable circuit 7 are generated. The generated address is transmitted to the address bus (AB) of the common bus 2 via the address line 13a in the initialization control output line 13.

The reset control circuit 60 outputs a reset signal (R) to the CPU 3 based on the reset input signal (RES) input from the reset input signal line 11 and the IE signal.
) and transmits the reset signal (R) to the CPU 3 via the CPU reset signal line 12.

FIG. 11 is a timing diagram of each of the above signals when the microcomputer 1 is initialized. The power-on reset circuit 62 detects the rise of the power supply voltage Vc at a certain level (a in the figure) and generates a power-on reset signal (PR) for a certain period (b in the figure). The initialization control circuit 61 is initialized by this power-on reset signal (PR).

When the power-on reset signal (PR) is released (c in the figure), the SE and SR signals are asserted.
A series of sequences for data transfer from EPROM 4 to variable circuit 7 is started.

At this time, until the IE signal is asserted (d in the figure), the CPU 3 is reset by the CPU reset signal (R).
is held in a reset state, and output to the common bus 2 is prohibited. That is, the common bus 2 is occupied by the system control circuit 9, the EPROM 4, and the variable circuit 7.

When an address is given to the address bus (AB) while the read signal (RD) to the EPROM 4 is asserted, data corresponding to the address is output from the EPROM 4, and the data is variable via the data bus 2d (DB). The signal is transmitted to the circuit 7.

Next, write signal (WR) to variable circuit 7
When an address is given to the address bus (AB) with
Data bus 2d corresponds to the addresses of 5-2,...
(DB) data is imported.

The above sequence is repeated for the required number of data while incrementing the counter 63 to perform initial settings.

FIG. 12 shows an example of the address map of the microcomputer 1. Address 0000~7FFF
A 32-kbyte EPROM 4 is arranged in the . The variable circuit 7 is arranged at addresses 8000-800C. A 1 kbyte RAM is arranged at addresses FC00 to FFFF. Initial setting data for initializing the variable circuit 7 is stored at addresses 0000 to 000C in the area of the EPROM 4. In the initial setting, this block is transferred to addresses 8000 to 800C in the variable circuit 7 area as described above.

Returning to FIG. 11, when the initialization is completed, the initialization control output line 13 is in the inhibited state (high impedance).
The SE signal and the SR signal are negated, and the IE signal is transmitted to the reset control circuit 60. This enables the reset input signal (RES),
The reset signal (R) changes in conjunction with the reset input signal (RES) (point d in the figure).

From then on, the microcomputer 1 operates according to the program stored in the EPROM 4.

As can be understood from the above explanation, in this microcomputer 1, the entire variable circuit 7 can be used as a logic circuit, the entire variable circuit 7 can be used as a memory circuit, or a part can be used as a logic circuit. Since a part of the memory circuit can be used as a memory circuit, the flexibility of the hardware can be improved and the waste of adding external circuits can be eliminated. Further, it is also possible to dynamically change the usage pattern of the variable circuit 7 according to the program during the operation of the microcomputer.

FIGS. 13(a) to 13(d) are examples of functions that can be realized by the variable circuit 7.

(a) The output of the logic circuit is used as the address of the memory circuit.

(b) The output of the memory circuit is used as the input of the logic circuit.

(c) The output of the logic circuit is stored in a memory circuit and used.

(d) Configuring a multi-stage logic circuit.

FIGS. 14 and 15 show the nMOS shown in FIGS. 4 and 5.
This is an example in which the example was changed to pMOS.

As yet another embodiment, EPROM4
Alternatively, an EEPROM or ROM may be used instead.

Another example is one in which the variable circuit 7 is not a part of the microcomputer 1, but is an independent semiconductor integrated circuit.

[0065]

[Effects of the Invention] Since the semiconductor integrated circuit of the present invention has both a logic function and a memory function that can be changed in the field,
It can be efficiently used in either logic circuits or memory circuits. Furthermore, since the microcomputer of the present invention has a built-in part that has both a logic function and a memory function that can be changed in the field, that part can be efficiently used for either a logic circuit or a memory circuit. It is possible to eliminate the waste of adding separate circuit components.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a variable circuit included in the microcomputer of FIG. 1.

FIG. 3 is a block diagram of a combinational circuit block included in the variable circuit of FIG. 2;

FIG. 4 is a circuit diagram of a combinational circuit included in the combinational circuit block of FIG. 3;

FIG. 5 is a circuit diagram of a logic block included in the combinational circuit block of FIG. 3;

FIG. 6 is a logical functional diagram of the logical blocks of FIG. 5;

FIG. 7 is a detailed block diagram of a combinational circuit block.

FIG. 8 is a logical functional diagram of a group of logical blocks included in the combinational circuit block of FIG. 7;

9 is a logic function diagram using another representation of a group of logic blocks included in the combinational circuit block of FIG. 7; FIG.

FIG. 10 is an explanatory diagram of initial setting of the variable circuit.

FIG. 11 is a timing diagram of initial setting of the variable circuit.

FIG. 12 is an address map diagram of the microcomputer in FIG. 1.

FIG. 13 is an exemplary diagram of how the variable circuit is used.

FIG. 14 is a diagram corresponding to FIG. 4 of another embodiment.

FIG. 15 is a diagram corresponding to FIG. 5 of another embodiment.

[Explanation of symbols]

1 Microcomputer 2 Common bus 3 CPU 4 EPROM 7 Variable circuit 8 Input/output circuit 9 System control circuit 22 Combinational circuit block 23 Address selector 25 Memory input/output multiplexer 27 Logic input selector 29 Logic output multiplexer 35 Combinational circuit array 36 Address decoder 37- 1, 37-2,... Memory data detection circuit 38
Logic input circuits 39-1, 39-2,... logic output circuits 40-1, 4
0-2,...Logic input control storage circuit 45-1, 45-
2,... Combinational circuit 46 RAM cells 53, 54 Transistor 59 Logic block 60 Reset control circuit 61 Initialization control circuit 62 Power-on reset circuit

Claims (17)

[Claims] 1. A combinational circuit array (35) comprising a plurality of combinational circuits (45) of memory cells (46) and switching elements (53, 54), and a combinational circuit array (35) that is used as a logic circuit or as a memory circuit. A semiconductor integrated circuit characterized in that it includes a combinational circuit block (22) having a control means (40-1, 40-2, . . . ) for controlling whether or not to use the combinational circuit block. 2. The semiconductor integrated circuit according to claim 1,
The control means (40-1, 40-2,...) controls whether a part of the combinational circuit array (35) is used as a logic circuit or a memory circuit, and independently controls the other part. A semiconductor integrated circuit characterized in that it is possible to control whether it is used as a logic circuit or a memory circuit. 3. In the semiconductor integrated circuit according to claim 1 or 2, the combinational circuit block (22) includes first access means (36, 37) for writing and reading data to and from the memory cells (46). -1,3
7-2,...) and the switching element (53, 54)
1. A semiconductor integrated circuit comprising second access means (38, 39-1, 39-2, . . . ) for performing logic input and logic output to the semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3,
First access means (36, 37-1, 37-2,...)
is a plurality of memory data detection circuits (37-1, 37-2
,...) and their memory data detection circuits (37-1, 3
7-2,...) and one combinational circuit (45-1, 45
-2,...), and a second access means (38, 39-1, 39-2,
...) includes a plurality of logic output circuits (39-1, 39-2,...
) and their logic output circuits (39-1, 39-2,...)
and second selection means (38) for associating a plurality of combinational circuits (45-1, 45-2, . . . ) with each other. 5. The semiconductor integrated circuit according to claim 4,
The input to the logic output circuit (39-1, 39-2,...) is
Memory cells (4
6) A semiconductor integrated circuit characterized by being defined by the mutual relationship of data stored in the above. 6. In the semiconductor integrated circuit according to claim 4 or 5, the second selection means (38) generates the same positive output and the inverted negative output as the logic data input to the combinational circuit block 22. 1. A semiconductor integrated circuit comprising positive and negative output means and inputting the positive and negative outputs to switching elements of a plurality of combinational circuits. 7. The semiconductor integrated circuit according to claim 6,
The second selection means (38) includes the control means (40-1, 40
-2, . . . ), both the positive output and the negative output of the positive/negative output means are set to the same level signal regardless of logic data. 8. The semiconductor integrated circuit according to claim 3,
First access means (36, 37-1, 37-2,...)
Input source switching means (23,
25) and first access means (37-1, 37-2,
), a data output destination switching means (25) for switching the output destination of data from the second access means (38), a logical input source switching means (27) for switching the input source of the logical input to the second access means (38), and a second access means (38) Means (39-1, 39-
1. A semiconductor integrated circuit further comprising at least one means of logic output destination switching means (29) for switching the output destination of logic outputs from the devices (2, . . . ). 9. The semiconductor integrated circuit according to claim 3 or 8, wherein the first access means (37-1, 37-
2,...) to the output destination of the data from the second access means (
38), and the output destination of the logic output from the second access means (39-1, 39-2,...) is connected to the first access means (36, 37-1, 37-2). ,…
) and connecting means (29a, 29b). 10. The semiconductor integrated circuit according to claim 1, wherein the memory cell (46) includes two inverting logic circuits (47) each having one input coupled to the other output. , 48). 11. A microcomputer further comprising a processor (6) for processing data on the same semiconductor substrate as the semiconductor integrated circuit according to claim 1. 12. The microcomputer according to claim 11, wherein a combinational circuit block (22), input source switching means (23, 25), and data output destination switching means (22) are provided.
5), and an initialization control means (61) for initializing at least one of the logical input source switching means (27) and the logical output destination switching means (29). microcomputer. 13. The microcomputer according to claim 12, further comprising initialization information storage means (
4) and a processor forced stop means (60) for forcibly stopping the processor (6), the initialization control means (61) forcibly stopping the processor (6) by the processor forced stop means (60). The microcomputer is characterized in that the microcomputer performs initialization based on the initialization information of the initialization information storage means (4) while the processor (6) is temporarily stopped, and after the initialization, the forced stop of the processor (6) is released. 14. The microcomputer according to claim 12 or 13, further comprising power-on reset means (62) for detecting that the power supply voltage has reached a predetermined voltage and outputting a power-on reset signal (PR). The initialization control means (61) is configured to control the power-on reset signal (
A microcomputer is characterized in that it starts an initialization operation in response to PR). 15. The microcomputer according to claim 13, wherein the initialization information storage means (4) is an electrically writable ROM. 16. The microcomputer according to claim 11, wherein the processor (6) includes an electrically writable ROM (ROM) that stores initialization information and a program for performing data processing.
4), a RAM (5) that stores data to be processed, and a CPU (3) that processes data according to the program in the ROM (4) using the data in the RAM (5). Features a microcomputer. 17. The microcomputer according to claim 11, further comprising: a common bus (2) connecting a plurality of means configured on a semiconductor substrate; and a common bus (2) connected to the common bus (2). A microcomputer characterized in that it has a single-chip configuration, and includes an input/output circuit (8) for inputting and outputting signals to and from the outside.