JPH04252372A - Variable pipeline structure - Google Patents

Abstract

PURPOSE:To realize a pipeline calculator in accordance with the calculation purpose by connecting a pipeline arithmetic pass extending over plural pipeline arithmetic units via selectors and dedicated passes. CONSTITUTION:Arithmetic units 100 and 200 has a three-stage pipeline structure to which composite arithmetic stages 110 and 210, multiplication stages 120 and 220, and accumulation stages 130 and 230 are connected, and each calculation unit processes each input data independently and parallely. On the input stage of the arithmetic logic calculators 117 and 217. selectors 116 and 216 are provided, and dedicated passes taken in the output of the adder-subtracters 214 and 114 of the other calculation unit is provided. In short, the dedicated passes mutually connecting the arithmetic units 100 and 200 is formed to realize the structure performing batterfly calculation.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention mainly applies to DSP (Digi
tal SignalProcessor). In particular, DCT (Dis
The present invention relates to a variable pipeline structure for performing butterfly operations and other operations in a high-speed algorithm (create cosine transform).

0002

2. Description of the Related Art An arithmetic unit in a conventional DSP is a fixed hardware consisting of a multiplier and an accumulator connected in cascade, and has a structure that always executes only multiplication and accumulation. Therefore, in the application algorithm of this DSP, when calculation passes other than multiplication and accumulation are required, such as a high-speed DCT algorithm, the algorithm is divided into a plurality of processes and executed.

0003

[Problems to be Solved by the Invention] As described above, in the conventional structure, it is necessary to divide the pipeline operation according to the algorithm to be handled, and a separate program design is required for the division. Furthermore, when dividing a pipeline operation, it is necessary to temporarily store the data to be processed between them, and if memory is used for this purpose, the power required to read and write the number of element data of the vector data to be processed is required. It took an extra amount of time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable pipeline structure that forms a pipeline structure depending on the purpose of pipeline operation and enables processing across a plurality of pipeline operation units.

[0005]

[Means for Solving the Problems] The present invention provides a dedicated path for interconnecting a plurality of pipeline arithmetic units in accordance with a predetermined purpose of arithmetic operations in a plurality of pipeline arithmetic units arranged in parallel; The present invention is characterized by comprising a selector for setting whether or not to connect to the other pipeline computing unit via the dedicated path based on instruction information set according to the purpose of the computation.

[0006]

[Operation] The present invention makes it possible to configure a pipeline path spanning a plurality of pipeline computing units by setting a dedicated path between the plurality of pipeline computing units according to the purpose of the computation. The desired calculation can be achieved with multiple pipeline processing steps. Note that the dedicated path is set by specifying the operation of the selector using instructions according to the purpose of calculation, and the calculation pipeline structure can be made variable.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention. In the figure, arithmetic units 100 and 200 have a three-stage pipeline structure in which complex arithmetic stages 110 and 210, multiplication stages 120 and 220, and accumulation stages 130 and 230 are connected in cascade, respectively. Each arithmetic unit normally processes each input data independently and in parallel, and outputs each processing result.

Here, the composite operation stage 110 includes registers 111 and 112, a selector 113, and an adder/subtractor (AS
U) 114, barrel shifter 115, arithmetic logic unit (A
LU) 117 and a selector 118. The multiplication stage 120 includes registers 121 and 122, and a multiplier (MPL).
It has 123. The accumulation stage 130 includes the register 13
1, selector 132, accumulator (ACC) 134, barrel shifter 135, registers 136, 137, selector 13
8,139.

[0009] Furthermore, the computation unit 200 includes a complex computation stage 210, a multiplication stage 220, and an accumulation stage 230.
The same is true for (1**:2**). The feature of this embodiment is that selectors 116, 216 are provided at the input stage of the arithmetic and logic units 117, 217, and a dedicated path (thick line) is provided to take in the output of the adder/subtractor 214, 114 of the other arithmetic unit via this selector. It is in the place where it is set up. That is, a dedicated path is formed to interconnect the arithmetic unit 100 and the arithmetic unit 200, thereby realizing a structure for performing butterfly computation.

[0010]Although the control register for controlling the operation of each selector in the instruction is omitted here, data forming an arithmetic pipeline structure according to the purpose of the operation is set in this control register. FIG. 2 is a diagram showing an equivalent circuit configuration of the butterfly calculation structure. Here, the selector 116 of the arithmetic unit 100
inputs the output of the adder/subtracter 214 of the arithmetic unit 200 to the arithmetic logic operator 117, and the selector 216 of the arithmetic unit 200 inputs the output of the adder/subtracter 214 of the arithmetic unit 100
The configuration is such that the output is input to the arithmetic and logic unit 217.

The operation of the butterfly calculation process will be described below with reference to an explanatory diagram of the butterfly calculation process shown in FIG. Note that in the case of DCT, W0 = W1 =1. Arithmetic unit 10
When the input signals of 0 are a and b, and the input signals of the arithmetic unit 200 are c and d, each adder/subtractor 114, 214 calculates a+b c+d, respectively. Subsequently, the output of the adder/subtractor 114 is inputted to the arithmetic logic unit 117 via the barrel shifter 115 and the output of the adder/subtractor 214 via the selector 116 . The output of the adder/subtractor 214 is inputted to the arithmetic logic unit 217 via the barrel shifter 215 and the output of the adder/subtractor 114 via the selector 216 . Therefore, each arithmetic and logic unit 117, 217 is (a+b)+(
c+d) (a+b)-(c+d) are calculated and latched in registers 121 and 221, respectively. Such a configuration allows the butterfly calculation shown in FIG. 3 to be pipelined.

FIG. 4 is a diagram showing the configuration of a second embodiment of the present invention. In the figure, calculation units 100, 200, 3
00 and 400 are composite operation stages 110 and 2, respectively.
10, 310, 410, multiplication stage 120, 220,
320, 420, cumulative stage 130, 230, 330
, 430 are connected in cascade to form a three-stage pipeline structure. Each arithmetic unit normally processes each input data independently and in parallel, and outputs each processing result.

Here, the compound operation stage 110 and the multiplication stage 120 are the same as those shown in FIG. 1, so the details thereof will be omitted. The accumulation stage 130 includes a register 131, a selector 132, and an accumulator (ACC).
134, barrel shifter 135, registers 136, 137
, selectors 138 and 139. In addition, the compound operation stages 210, 310, 410, the multiplication stages 220, 320, 420, and the accumulation stage 23 of other operation units
The same is true for 0,330,430 (1**:2
**:3**:4**).

The feature of this embodiment is that the accumulators 134, 234
, 334, 434 have selectors 133, 233,
333 and 433 are provided, and the output of the register 231 of the arithmetic unit 200 is sent to the arithmetic unit 1 via the selector 133.
00 to the accumulator 134 and the register 33 of the arithmetic unit 300 via the selector 433.
1 to the accumulator 434 of the arithmetic unit 400, and the output of the selector 139 of the arithmetic unit 100 to the arithmetic unit 30 via the selector 332.
0 to the accumulator 334 and the selector 439 of the arithmetic unit 400 via the selector 333.
A dedicated path P4 takes the output of the selector 339 of the calculation unit 300 to the accumulator 334 of the calculation unit 300 via the selector 232, and
A dedicated path P5 for inputting data into the accumulator 234 is provided. That is, all of the calculation units 100 to 400 are connected to realize a summation calculation structure.

Although the control register for controlling the operation of each selector in the instruction is omitted here, data forming an arithmetic pipeline structure according to the purpose of the operation is set in this control register. FIG. 5 is a diagram showing an equivalent circuit configuration of the sum calculation structure. Here, the input signals of the arithmetic unit 100 are ai, bi
and the input signals of the arithmetic unit 200 are ci, di
and the input signals of the arithmetic unit 300 are ei and fi
and the input signals of the arithmetic unit 400 are gi, hi
Then, each adder/subtractor 114, 214, 314, 41
4 (see FIG. 1) calculate ai + bi ci + di ei + fi gi + hi, respectively. Note that this output is sent to the arithmetic and logic unit 117,
217, 317, 417 (see FIG. 1), and the output thereof is sent to registers 121, 221, 321,
421 (see FIG. 1). Next, α, β, γ, and δ are set in advance in the registers 122, 222, 322, and 422 (see FIG. 1), respectively, and the multiplier 1
By multiplying the contents of each register by 23, 223, 323, 423 (see Figure 1), registers 131, 23
α(ai +bi) β(ci+di) γ(ei+fi) δ(gi+hi) are latched at 1, 331, and 431, respectively. Here, for ease of explanation, α=
Let β=γ=δ=1. The operation will be described below with reference to the explanatory diagram of the sum calculation process shown in FIG.

The accumulator 134 of the arithmetic unit 100 includes:
The output of register 131 is input via selector 132 and the output of register 231 is input via selector 133, and the result of the operation is latched in register 136. Further, the accumulator 434 of the arithmetic unit 400 includes a selector 4
32 to the output of register 431 and selector 43
The output of the register 331 is input through the register 436, and the result of the operation is latched in the register 436. At this time, the contents of each register 136, 436 are (ai + bi
)+(ci+di)(ei+fi)+(gi
+hi).

Further, the output of the register 136 is passed through the selector 139, the dedicated path P3 and the selector 332, and the output of the register 436 is sent to the accumulator 334 via the selector 439, the dedicated path P4 and the selector 333.
The result of the operation is latched into the register 336. At this time, the contents of the register 336 are (ai +
bi +ci +di ) +(ei +fi +gi
+hi).

Finally, the output of register 336 is input to accumulator 234 via selector 339, dedicated path P5, and selector 232. Accumulator 234 accumulates the contents of register 236 via selector 239 . Therefore, the register 236 contains Σ(ai +bi +ci +di +ei +fi
+gi +hi) is obtained. This is the selector 23 as the sum calculation result.
8.

[0019]

[Effects of the Invention] As explained above, the present invention connects a pipeline operation path spanning a plurality of pipeline operation units to a selector via a dedicated path.
A pipeline arithmetic unit suitable for the purpose of calculation can be easily realized. In other words, the operation of the selector can be specified by instructions according to the purpose of each operation, and it can be operated variably by software, so by arranging dedicated paths and designing each operation unit appropriately, all forms of pipeline operations can be performed. The container can be easily configured.

[0020] Therefore, program design associated with division of pipeline operations becomes unnecessary, and extra power consumption for memory reading and writing can be avoided, and even higher speed processing can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit configuration of a butterfly operation structure.

FIG. 3 is a diagram illustrating butterfly calculation processing.

FIG. 4 is a diagram showing the configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing an equivalent circuit configuration of a sum calculation structure.

FIG. 6 is a diagram illustrating a summation calculation operation.

[Explanation of symbols]

100, 200, 300, 400 calculation unit 11
0,210,310,410 Complex calculation stage 11
1,112,211,212,311,312,411
, 412 register 113, 213, 313, 413 selector 114,
214, 314, 414 Addition/subtraction unit (ASU) 115
,215,315,415 Barrel shifter 116,2
16,316,416 selector 117,217,3
17,417 Arithmetic logic unit (ALU) 118,218,318,418 Selector 120,
220, 320, 420 Multiplication stage 121, 12
2,221,222,321,322,421,422
Registers 123, 223, 323, 423 Multiplier (MPL)
130,230,330,430 Accumulation stage 13
1,231,331,431 Register 132, 13
3,232,233,332,333,432,433
Selector 134, 234, 334, 434 Accumulator (ACC)
135,235,335,435 Barrel shifter 13
6,137,236,237,336,337,436
, 437 Register 138, 139, 238, 239, 338, 339, 4
38,439 selector

Claims (1)

[Claims] 1. In a plurality of pipeline arithmetic units arranged in parallel, a dedicated path interconnects the plurality of pipeline arithmetic units in accordance with a predetermined arithmetic purpose, and a dedicated path configured in accordance with the arithmetic purpose. and a selector for setting whether or not to connect to the other pipeline computing unit via the dedicated path based on instruction information.