JPH0298777A - Parallel sum of product arithmetic circuit and vector matrix product arithmetic method - Google Patents

Abstract

PURPOSE:To accelerate a matrix arithmetic operation by operating sum of product arithmetic circuits in parallel by a value stored in a memory circuit in advance and a value to be supplied to an input bus. CONSTITUTION:The memory circuit 2 can write the value from the input bus 1, and read out different values from output ports p1-p4 simultaneously, and sum of computing elements 3-6 calculate the products of two input systems supplied from the input bus 1 and the output of the memory circuit 2, and accumulate them in internal accumulators. And the values accumulated in the sum of product arithmetic parts 3-6 are outputted to corresponding latch circuits 13-16, and only either one of buffer gates 23-26 is selected by control from the outside, and the contents of the latch circuits 13-16 are read out to the outside via an output bus 12. Thereby, a fast matrix arithmetic operation can be performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an arithmetic circuit and an arithmetic method used in a digital signal processing device, particularly a parallel product-sum arithmetic circuit and an arithmetic method using the same. The present invention relates to a parallel product-sum calculation circuit and a vector-matrix product calculation method that can calculate products between vectors and matrices at high speed.

[Conventional technology]

The arithmetic circuits used in conventional digital signal processing processors have built-in multipliers and accumulators, and they operate in parallel using pipeline processing to efficiently execute product-sum operations. Band signal processing is performed in real time.

However, in applications such as image signal processing and image generation, which have a bandwidth about 1000 times that of an audio signal, higher-speed matrix calculation processing capacity is required in order to perform real-time processing.

Therefore, as a method for increasing the speed, in addition to improving the operating speed of the arithmetic circuit, it is possible to introduce parallel processing in which a large number of multipliers and accumulators are arranged. In fact, with recent advances in LSI technology,
It is now possible to mount a plurality of arithmetic units with relatively large circuit scales, such as parallel multipliers, on the same chip.

With this problem in mind, H and T are particularly popular as circuits that perform matrix calculations at high speed through parallel processing.

Many circuit configuration methods have been proposed based on the systolic array method proposed by KUNG et al. (for example, IB
EH Computer Magazine Volume 15 (1), 37
(See page 46). These matrix arithmetic circuits are hardware circuits in which arithmetic units are arranged so as to maximize the parallelism of individual arithmetic functions such as matrix multiplication and to minimize the wiring length between the arithmetic units.

[Problem to be solved by the invention]

However, since these matrix calculation circuits each have a single-function circuit configuration optimized for a specific calculation function, it is difficult to apply them directly to the calculation section of a general-purpose digital signal processing processor.

In order to increase flexibility, it is possible to introduce sub-bus configurations and bus switches between a large number of computing units to increase the degree of freedom in connection, but this increases the hardware scale and complicates the control program, making it difficult to use. A problem arises in that the arithmetic circuit becomes difficult to use.

An object of the present invention is to provide an arithmetic circuit that speeds up matrix operations by arranging arithmetic units in parallel so that it can be applied to applications such as image signal processing and image generation. It is an object of the present invention to provide a parallel product-sum calculation circuit and a vector-matrix product calculation method with a circuit configuration and control method that realize flexible calculation processing with simple control so as to be suitable as a calculation unit.

[Means to solve the problem]

The parallel product-sum operation circuit of the present invention includes an input bus, a memory circuit that can simultaneously read values stored at different addresses to N outputs, each of which is connected to the input bus and one output of the memory circuit, N product-sum calculators that accumulate and store two values input from an input bus and a storage circuit, and N latch circuits each connected to the N product-sum calculators to capture the calculation results; It is characterized by comprising means for updating the contents of the storage circuit, means for initializing the storage contents of the product-sum calculator, and means for reading the values of the N latch circuits to the outside.

The vector-matrix product calculation method of the present invention uses the above-mentioned parallel product-sum calculation circuit to calculate the M-dimensional vector C''
(C+ Cz ・” CM) and M rows and N columns matrix A=
(asn1m=1.2.---, M; n=l.

2,...,N), calculate the vector matrix product C-A of N
This is a vector matrix product calculation method for obtaining a dimensional vector BCe+ez...eN), in which the values of elements all11 of the matrix A are stored in the storage circuit in advance, and the values of the elements C1 of the input vector C are stored in the input bus. 'I,' l
+...r cH, and the elements of the column vectors constituting the matrix A are each aInn ” Zri
+...+aMr+, the N product-sum calculators calculate the element en of the vector E by inner product operation of the input vector C and the N column vectors, and the calculated result is is simultaneously captured in the latch circuit,
It is characterized in that it is then read out to the outside.

Further, the parallel product-sum calculation circuit of the present invention is characterized in that the function of the product-sum calculation unit includes a function in which subtraction can be selected by external control.

Further, the vector matrix product calculation method of the present invention uses the above-mentioned parallel product-sum calculation circuit in which the product-sum calculation unit includes a subtraction function, and the M-dimensional complex vector C= (c).

+j (LIm=1.2. . . -, M) and a complex matrix A of M rows and N columns = ("me+J ban I m""!
+L...1M; n-1,2,...,N) complex vector matrix product C-A is calculated, and N-dimensional complex vector E= (e, +jffiln=1.2....,
N) is a vector matrix product calculation method for obtaining the real part en and the imaginary part fn of the matrix, wherein the real part all11 and the imaginary part ba11 to the matrix are stored in the storage circuit in advance, and the input bus is used to store the complex vector C The components of ' l+ dIn C! , dIn
. . . are sequentially supplied in the order of . The components of the column vectors of matrix A from the circuit are aI,
, + bII'l+ ” Enr b 1n+
...Sequentially read out in the order of amnrbHn, calculate Σ(ai.Ci ``i+sdi) in 2M operations by alternately using the addition function and subtraction function of the product-sum calculation unit, and take charge of calculating the imaginary part fn. The product-sum calculator converts the components of the column vector into the matrix as bIn+aIn+b2n
, 3g11+..., b□+aN11 and 2M times of product-sum operations, Σ(bi, ,C8+ai
di), 2N numerical values from the first element to the Nth element of the output vector E are simultaneously calculated in the corresponding 2N product-sum calculators, and the calculated inner product value is It is characterized in that it is read out to the outside after being taken into the latch circuit at the same time.

[Effect]

In the present invention, in order to reduce the number of required calculation steps and knobs, a product-sum calculation unit is assigned to calculate one element of an output vector.

The vector-matrix product of the vector C and the matrix is calculated by calculating the inner product of the vector C and the column vector of the matrix, and each inner product value becomes one element of the output vector as it is. Therefore, if a plurality of product-sum calculators are prepared and calculation of the elements of the output vector is assigned to each one, each element can be calculated without referring to the outputs of other product-sum calculators.

At this time, if each product-sum calculator simultaneously performs calculations in a predetermined order, each product-sum calculator refers to element C7 of the same vector C. Therefore, in the parallel product-sum operation circuit according to the present invention,
One of the two inputs of each product-sum calculator is made common, and elements Ci of the vector C are supplied in a predetermined order.

On the other hand, the elements of the matrix A are simultaneously supplied to each product-sum calculation unit for each column vector, but in the parallel product-sum calculation circuit according to the present invention, the elements of the matrix A are stored in advance in a storage circuit with N outputs. This is achieved by simultaneously reading at externally specified addresses.

In this way, by determining the value stored in the memory circuit in advance and the value supplied to the input bus, the product-sum operation circuit can be operated in parallel to obtain the vector matrix product, and the memory circuit can be read out using a microprogram, etc. By controlling the address and data supply to the input bus and the initialization timing of the product-sum calculation unit based on the vector matrix product calculation method according to the present invention, vectors without restrictions on the number of dimensions of the matrix that can be handled or deterioration in calculation efficiency. Enables matrix multiplication operations.

The present invention also enables complex vector operations. The product-sum calculator is also equipped with a subtraction function so that it can also handle complex operations. Furthermore, the product-sum calculator used is assigned in advance to calculate the real part or imaginary part of the output complex vector, and the input bus is used to alternately calculate the real part and imaginary part of the complex vector C under external control. The complex operation is realized by supplying the subtraction function described above according to the calculation formula of complex multiplication.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a parallel product-sum calculation circuit according to the first invention. As shown in FIG. 1, the circuit of this embodiment has an input bus 1, a memory circuit 2 having four outputs, and sum-of-products operating units 3.4 and 5.6. Details are shown in FIG. Furthermore, latch circuits 13, 14, 15, and 16 that latch the outputs of the product-sum calculators 3, 4, and 5.6, and buffer gates 23, 24, and 24 that output the I values stored in the latch circuits to the output bus 12, It has 25.26.

The memory circuit 2 is a 16-word, 4-output type memory circuit into which values can be written from the input bus 1, and provides four independent addresses of 4 bits each to the address terminal 11, and outputs ports pt, p2, . p3. Four different values can be read simultaneously from p4.

The product-sum calculators 3, 4, 5.6 are connected to the input bus 1 and the memory circuit 2.
Computes the product of the two input sequences fed to the output of and accumulates it in an internal accumulator.

The product-sum calculators 3, 4, 5.6 all have the same configuration,
The details are shown in FIG. As shown in FIG. i2, the product-sum calculator includes a multiplier 31 that calculates the product of values supplied to two input ports, and an adder 32 that adds the output of the multiplier 31 and the value of the accumulator 33. Adder 3
2 can also output the output of the multiplier 31 as it is by setting the input of the accumulator to "0" under external control. In this product-sum calculator, when input series are given to two input terminals at the same time, the product of the first value is loaded directly into the accumulator 33, and the second and subsequent products are multiplied by the value of the accumulator 33. The outputs of the device 31 are added together and stored again. By repeating this operation a necessary number of times, the inner product value between vectors of arbitrary length can be calculated.

The value accumulated in each product-sum calculator is stored in the corresponding latch circuit 1.
Output on 3.14.15.16. latch circuit 13,
14, 15, and 16 are buffers that simultaneously capture the outputs of the corresponding multiply-accumulators when a capture signal is applied to the clock terminal.) 23, 24, 25, and 26 capture only one of them by external control. is selected, and the contents of the latch circuit are read out via the output bus 12.

As described above, the parallel product-sum operation circuit of FIG. 1 according to the first invention has an input bus 1 and a memory circuit that can simultaneously read values stored at up to N (four in this embodiment) different addresses. 2, each of which is connected to one output of the input bus 1 and the memory circuit 2, and N product-sum operations that accumulate and store the product of two values input from the input bus 1 and the memory circuit 2. Vessels 3-6
, N latch circuits 13 to 16 that are connected to the N product-sum calculators 3 to 6 and take in the product-sum calculation results, means for updating the contents of the storage circuit 2, and product-sum calculators 3 to 6. 6, and N latch circuits 13 to 16.
and means for reading out the value of.

The parallel product-sum calculation circuit and calculation method described above are based on the following principle.

First, the product-sum calculation circuit and vector-matrix product calculation method according to the present invention shown in FIG. 1 will be explained using the vector-matrix product calculation shown in equation [1] as an example.

The calculation of equation [1] requires a total of 16 product-sum calculations, and therefore, for example, approximately 16 steps are required when the calculation is performed using an I-chip signal processing processor having one product-sum calculation circuit. However, if four product-sum calculation units are used, it should be possible to reduce the number of calculations to a maximum of four steps.

In the calculation method according to the present invention, as described below, in order to reduce the number of required calculation steps, a product-sum calculation unit is assigned to calculate one element of the output vector.

The vector-matrix product of the vector C and the matrix A is calculated by calculating the inner product of the vector C and the column vector of the matrix, and each inner product value becomes one element of the output vector as it is. Therefore, if four product-sum calculators 3 to 6 are prepared and each is assigned the calculation of an element of the output vector, each element can be calculated without referring to the output of other product-sum calculators. . At this time, each product-sum calculation unit 3 to 6 has [1
] If calculations are performed simultaneously in the order of subscripts i=1 to 4 in the equation, each product-sum calculator 3 to 6 refers to element C1 of the same vector C. Therefore, in the parallel product-sum calculation circuit according to the present invention, one of the two inputs of each product-sum calculation 33 to 6 is made common, and elements c of the vector C are supplied in the order of i=1 to 4.

On the other hand, the elements of the matrix are simultaneously supplied to each product-sum calculation unit for each column vector, but in the parallel product-sum calculation circuit according to the present invention, the elements of the matrix A are stored in advance in the notation tα circuit 2 with N outputs. This is achieved by simultaneously reading out the objects at externally specified addresses.

For example, in discrete cosine transformation expressed by vector matrix product, the elements of the matrix are usually constants and do not change, so it is sufficient to write the coefficients once in the storage circuit 2 before processing. In other adaptive signal processing applications as well, matrix element values do not change frequently, so updating of matrix element values does not necessarily have to be fast.

Furthermore, in the example of a K-dimensional discrete cosine transform, the matrix is
Although it has 2 coefficients, since there are only 2 types of values, the storage capacity only needs to be 2 words.

In this way, there is an advantage that the storage circuit can be effectively utilized by utilizing the duplication of matrix element values.

When the number of dimensions of the output vector is less than or equal to the number of product-sum calculation units,
As described above, it is determined in M steps corresponding to the number of dimensions of the input vector. When the number of dimensions of the output vector is greater than N, after obtaining N elements of the output vector, the elements of the vector C are given again to the input bus, and from the storage circuit 2,
Given the remaining column vectors of matrix A, compute the next N output vector elements. At this time, when the first N calculation results are obtained, they are immediately fetched from the accumulator 33 in the product-sum calculation unit to the latch circuits 13 to 16, and then 01 is supplied to the input bus for the next calculation. , the product-sum calculator can be used non-stop.

As described above, in the parallel product-sum calculation circuit according to the present invention, the read address of the memory circuit 2 and data supply to the input bus, and the initialization timing of the product-sum calculation units 3 to 6 are controlled by a microprogram or the like according to the present invention. Control based on the vector-matrix product calculation method enables vector-matrix product calculations without restrictions on the number of dimensions of the matrices that can be handled and without deterioration in calculation efficiency.

As described above, the vector-matrix product calculation method of the second invention uses the calculation circuit of the first invention to calculate the vector-matrix product C-A of the M-dimensional vector C and the M-by-N matrix A. In this method, the elements of the matrix A are stored in advance in the memory circuit 2, the elements of the input vector C are sequentially supplied to the input bus 1, and from the N outputs of the memory circuit 2, the elements of the matrix A are stored in the memory circuit 2 in advance. By sequentially reading out the elements of the column vectors constituting C, N product-sum calculators 3 to 6 calculate the inner product of the input vector C and each of the N column vectors by performing M product-sum calculations, and obtain the inner value. are corresponding lattice circuits 13 to 16 at the same time.
The data is imported into the system, and then read out to the outside.

Hereinafter, a vector matrix product calculation method using the parallel product-sum calculation circuit shown in FIG. 1 will be specifically explained with reference to FIG. 3 as well.

In the explanation, without loss of generality, the above (1)
, ) calculation example is used. First, before processing [1]
The element amn of the matrix of the formula is sent to the storage circuit 2 via the input bus 1.
write to. Hereinafter, as shown in FIG. 3, for the subscript i in equation [1], four steps from i=1 to 4 are performed to input the input ports of FIG. p
3. p4° is applied to the clock terminal 17 to execute the calculation.

When i=1, the input bus 1 is supplied with the element c of the vector C, and the output p1. of the storage circuit 2 is supplied. p2゜p3. p4 has one each a ll+ a lt+ a ll+ 2
14. For this purpose, the address terminal 11 is
all.

The addresses of aIz, a-th, and a-th are supplied simultaneously.

In the product-sum calculator 3, the multiplier 31 outputs the product of the read value all and c to the output port pl of the storage circuit 2. Also, the adder outputs the output of the multiplier as is, and C
The product CIall of 1 and all is stored in the accumulator 33 of the product-sum calculator. The product-sum calculator 4.5.6 simultaneously performs the same operation as the product-sum calculator 3, and the product-sum calculator 4.5.6
The accumulator has the product CIa12+'1a13
．． 'Ia14 is stored at the same time.

When i=2, C2 is supplied to the input bus 1, and in the product-sum calculator 3, the multiplier 31 outputs the value ax read to 02 and pl.
Outputs the product of +. Further, the adder 32 adds the output of the multiplier 31 and the value C1all of the accumulator 33,
The addition result is stored in the accumulator 33. Therefore, the accumulator 33 of the product-sum operation circuit 3 has CIall+
C! a! + is stored. The product-sum calculators 4, 5.6 simultaneously perform the same operations as the product-sum calculator 3, and the product-sum calculator 4.
5.6 accumulator has % 'Ial! +C! a!
z, 'Ia12''Za!!+CIa14+Ctat4 are stored simultaneously.

Below, for i=3.4, each product-sum operator 3°4.5
．． 6 repeats the same operation as for i-2. As a result, for i and x4, the accumulators of the product-sum calculator 3.4゜5.6 have Σ Ci a il+ Σ cta = z, respectively.
Σ Ci”il!@I
! -Ki Mine C4ai.

is stored, and the elements of equation [1] are found in the accumulator of each product-sum calculator. The four values found are the clock terminal 1.
7 is supplied with "1", and the latch circuits 13, 14, 15.
16, and can be read out to the output bus 12 under external control.

Next, an embodiment of the parallel product-sum operation circuit according to the third invention is shown in FIG. 4.As shown in FIG.
An input bus 1, a memory circuit 2, and a product-sum calculator 30. 4.
50. 6, a latch circuit 13, 14, 15, 16 that latches the output of the product-sum calculator 30, 4, 50.6, and a buffer gate 23 that outputs the data stored in the latch circuits 13 to 16 to the output bus 12. .24, 25° 26, and a control terminal 18 for controlling the product-sum calculator 30, 50. The parallel product-sum calculation circuit shown in FIG. 4 includes a product-sum calculation unit 30.
1, excluding 50 and control terminal 18.

It has the same configuration and functions as the embodiment shown in FIG.

The accumulation function of the product-sum calculator 30.50 has an added function that allows selection of subtraction by external control.

That is, the product-sum calculator 30.50 receives the input bus l and the output p1. The product of the two input sequences respectively supplied to p3 is calculated and accumulated in an internal accumulator. The configuration of the product-sum calculator 30.50 is shown in FIG.

As shown in FIG. 5, the product-sum calculator 30.50 includes a multiplier 31 that calculates the product of values supplied to two input ports, and an adder that adds the output of the multiplier 31 and the value of the accumulator 33. The adder 32 can output the output of the multiplier 31 as it is to the accumulator 33 by setting the input on the accumulator side to 10''. Subtract the output value of multiplier 3 from the value of and output it. Adder 3
2. The output of the M calculator 34 is input to the selector 35,
When the control terminal l8 is "0", the output of the adder 32 is "
1", the output of the subtracter 34 is selected and output to the accumulator 33. Therefore, in this product-sum calculator,
When the adder 32 is selected, the output of the multiplier 31 can be stored as is or by adding it to the value of the accumulator 33, and when the subtracter 34 is selected, the output of the multiplier 31 can be stored from the value of the accumulator 33. The value obtained by subtracting the output can be stored in the accumulator 33.

In this way, in the parallel product-sum operation circuit according to the third invention,
In addition to the accumulation function of the product-sum calculator according to the first invention, it also has a subtraction function so that it can also handle complex operations.

A vector-matrix product calculation method according to a fourth invention includes an operation for calculating a complex vector-matrix product of an M-dimensional complex vector C and a complex matrix A with M rows and N columns, using the calculation circuit having the above configuration according to the third invention. In this method, numerical values constituting the matrix A are stored in advance in the storage circuit 2, calculation of the real part or imaginary part of the output complex vector is assigned in advance to the product-sum calculator, and the input bus 1 is alternately supplying the real part and the imaginary part of the components of the complex vector C under external control;
Complex operations are realized by selecting the subtraction function according to the third invention according to the calculation formula of complex multiplication.

The third feature that enables such complex vector operations. The principle of the fourth invention will be explained using an example of formula [2] with a total of 1γ.

Here, a complex vector matrix product is calculated between a two-dimensional complex vector C and a 2-by-2 complex matrix.

Note that jZ=1.

In digital calculations, a complex number is represented by a set of two numbers, a real part and an imaginary part, so the two-dimensional complex vector that is the result of the calculation of equation [2] is actually represented by four numbers.

Therefore, the four values Σ enclosed in the Σ symbol on the right side of [2]
(Cial 'jbi+) + Σ(C4bi+
“diai+)+Σ(C7aiZ-diblg)
+ Σ (CibiZ"dfai!) is prepared by four product-sum calculation units and assigned to each. At this time, focusing on the calculation in one product-sum calculation circuit and fixing the subscript i, The calculation of is two multiplications and one addition or subtraction, so to calculate i for 1 and 2,
1] Similar to the calculation of each element in the equation, four product-sum operations are required.

Furthermore, if we pay attention to the order of the four product-sum operations, [1]
Similar to the formula calculation method, the four product-sum calculators simultaneously refer to the real part C7 or the imaginary part d of the elements of the same complex vector C. Therefore, in the configuration of the parallel product-sum operation circuit, the input bus is shared in common as in the first invention, and the elements of the complex matrix A may be stored in advance in the storage circuit.

The elements of the input complex vector C, for example, CI+dl+CZ
When the real part and the imaginary part are alternately supplied in the order of +d2r..., it is sufficient to read out the four outputs in accordance with the input order of the elements of the vector C so that each multiplication in equation [2] is calculated. Specifically, a product-sum calculator a that calculates the real part of the n-th column
11%+ bIfi+ bZnr bZnr・・
・The product-sum calculator that calculates the imaginary part of the nth column has b
I+1+ ”IPl+ bZnr bZnr
” ' Read out in order.

However, Σ(ciai) corresponds to the real part of the output.

−d, b i,), d, b,,,
The terms must be accumulated with their signs reversed. Therefore, the product-sum calculator 30.50, which is in charge of the real part of the output, is provided with a subtracting function in addition to the function of adding the multiplication results. It can be controlled from

Hereinafter, a vector matrix product calculation method using the parallel product-sum calculation circuit shown in FIG. 4 will be specifically explained with reference to FIG. 6. For the explanation, the calculation example of the above-mentioned formula [2] will be used without considering the -membrane property. First, prior to processing, the elements allII+b□ of the matrix A in equation [2] are written into the storage circuit 2 via the input bus 1. Hereinafter, in four steps from k=1 to 4, an operation is performed while supplying the elements of the vector C of equation [2] alternately in the order of 'In dI+ C2+ d' to the input bus 1 as the real part and the imaginary part. Ru.

At k-1, element c of vector C is supplied to input bus 1, and at the same time element c of vector C is supplied from storage circuit 2 to each product-sum calculation circuit 30.
4.50. 6 has aII+bIl+alt, respectively.
,bI! Read out.

In the product-sum calculator 30, the multiplier 31 outputs the product C1a of the value all read out from the storage circuit 2 to pl at the same time as C3. Furthermore, by supplying "0" to the control terminal 18, selecting the output of the adder 32 by the selector 35, and causing the adder 32 to directly output the output of the multiplier 31,
CIall is stored in the accumulator 33. The product-sum calculators 4 and 50.6 perform the same operation as the product-sum calculator 30, and the accumulator of each product-sum calculator has '1bll'.
+ C1a, g, c+b+z are stored.

When k=2, the imaginary part d of the complex vector C is supplied to the input buffer, and in the product-sum calculator 30, the multiplier 31
At the same time, the product of S and S read out from the memory circuit 2 to pi is output. At this time, 11'' is applied to the control terminal 18 to supply the output of the subtracter 34 to the accumulator 33, and from the value CIall of the accumulator 33, the output d of the multiplier 31,
amn is subtracted and C1alldlb11 is stored in the accumulator 33. The product-sum calculator 50 also reads out bl! to p3! and d, the same operation as the product-sum calculator 30 is performed, and the accumulator of the product-sum calculator 50
a It d l b 11 is stored. On the other hand, in the product-sum calculator 4.6, d supplied to the input bus 1 and
all+ read out from memory circuit 2 to p2゜p4
``The product dl alI+ d1a1□ of I2 is added to each accumulator c1bll+ala11.c
lbl! +alal! shall be.

When k=3, element C2 of vector C is supplied to input bus 1, and at the same time, element C2 of vector C is supplied from storage circuit 2 to each product-sum calculation circuit 30.
4.50. 6, each a! In')21゜a
21. b! ! Read out.

In the product-sum calculator 30, the multiplier 31 outputs the product of (!a,,) which is supplied to pl from the storage circuit 2 at the same time as 02.

Further, "O" is applied to the control terminal 18, and the selector 35
selects the adder 32, outputs the sum with the accumulator value, and stores it in the accumulator 33. The product-sum calculator 50 also performs the same operation as the product-sum calculator 30. As a result, the accumulators of the product-sum calculator 30 and 50 each have ''.
l al I-dl bl I +Ct al 1
+C1al! -dlbl! +C! Al! is stored.

In the product-sum calculation units 4 and 6, C2 supplied to the input bus l and p2 . b 2 read out in p4 respectively
+, b ffi! The same operation as when k=2 is repeated for C1bll+dllall+C! b! 1.
C1bl! +cl+a, , +C1b2g are stored simultaneously.

When k=4, d2 supplied to input bus 1 and pi, p2 . p3. b read simultaneously to p4
! I+a! l+b! ! For +322, each repeats the same operation as when =2.

As described above, four values constituting the result of equation [2] are obtained in the accumulator of each product-sum calculator in four steps between 1 and 4. The determined value is simultaneously stored in the latch circuit and read out to the output bus 12 under external control (not shown).

〔Effect of the invention〕

As described above, according to the parallel product-sum calculation circuit and vector matrix product calculation method according to the present invention, the product-sum calculation circuit can be operated in parallel by determining the value stored in the storage circuit in advance and the value supplied to the input bus. It can be operated to obtain vector matrix products. Furthermore, since the elements of the matrix are stored in the memory circuit, in the case of a matrix with duplicated values, such as a symmetric matrix, the memory capacity may be small, and the memory circuit can be used effectively. Furthermore, since the calculation method divides the output vector into elements, it is easy to program the calculation of vectors larger than the number of product-sum calculation units by repeating calculations.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the first invention, FIG. 2 is a diagram showing an example of a detailed configuration of a product-sum calculator, and FIG. 3 is for explaining the calculation method of the second invention. 4 is a diagram showing an embodiment of the third invention, FIG. 5 is a diagram showing an example of a detailed configuration of a product-sum calculator that also has a subtraction function, and FIG. FIG. 2 is a diagram illustrating a calculation method according to the invention. 1...Input bus 2...Storage circuit 3-6.30.50...Product-sum calculator 13-16...Latch circuit

Claims (4)

[Claims] (1) An input bus and a memory circuit that can simultaneously read out values stored at different addresses to N outputs, each of which is connected to the input bus and one output of the memory circuit. N product-sum calculators for accumulating and storing the two values calculated; N latch circuits each connected to the N product-sum calculators to take in the calculation results; and updating the contents of the storage circuit. means for initializing the storage contents of the product-sum calculator;
1. A parallel product-sum operation circuit comprising: means for reading out values of two latch circuits to the outside. (2) Using the parallel product-sum calculation circuit according to claim 1, an M-dimensional vector C=(c_1c_2...c_M) and M rows N
Column matrix A=(a_m_n|m=1, 2,...,M;
Calculate the vector matrix product C・A of n=1, 2, ..., N), and calculate the N-dimensional vector E (e_1e_2...e_N)
A vector matrix product calculation method for calculating, wherein the value of the element a_m_n of the matrix A is stored in the storage circuit in advance, and the element c_m of the input vector C is stored in the input bus as c_1, c_2, . . . c_M, and the elements of the column vectors constituting the matrix A are each a
_1_n, a_2_n, ..., a_M_n are sequentially read in the order, and the N product-sum calculation units calculate the element e_n of the vector E by the inner product operation of the input vector C and the N column vectors. A vector matrix product calculation method, characterized in that the results are simultaneously taken into the latch circuit and then read out to the outside. (3) The parallel product-sum calculation circuit according to claim 1, wherein the function of the product-sum calculation unit includes a function in which subtraction can be selected by external control. (4) Using the parallel product-sum calculation circuit according to claim 3, an M-dimensional complex vector C=(c_m+jd_m|m=1, 2
,...,M) and a complex matrix of M rows and N columns A=(a_m_n
+jb_m_n | m=1, 2, ..., M; n=1, 2
, ..., N), calculate the complex vector matrix product C・A,
N-dimensional complex vector E=(e_n+jf_n|n=1
, 2, .
The components of the complex vector C are sequentially supplied to the input bus in the order of c_1, d_1, c_2, d_2, etc., and the real part of the complex vector E is stored in advance in the product-sum calculator. e_n or the imaginary part is assigned to the product-sum calculator which is in charge of calculating the real part e_n.
b_1_n, a_2_n, b_2_n, ..., a_M
_n, b_M_n are read out in order, and the addition and subtraction functions of the product-sum calculator are used alternately to calculate
(a_i_nc_i - b_i_nd_i), and the product-sum calculator in charge of calculating the imaginary part f_n calculates the components of the column vectors of matrix A as b_1_n, a_1_n, b_
2_n, a_2_n, ..., b_M_n, a_M_n
are read out sequentially in the order of Σ(b
_i_nc_i+a_i_nd_i), and 2N numerical values from the first element to the Nth element of the output vector E are simultaneously calculated in the corresponding 2N product-sum calculators,
The vector matrix product calculation method is characterized in that the determined inner product values are simultaneously fetched into corresponding latch circuits and then read out to the outside.