JPH0425098A - Ceramic multilayer substrate - Google Patents
Ceramic multilayer substrateInfo
- Publication number
- JPH0425098A JPH0425098A JP2127294A JP12729490A JPH0425098A JP H0425098 A JPH0425098 A JP H0425098A JP 2127294 A JP2127294 A JP 2127294A JP 12729490 A JP12729490 A JP 12729490A JP H0425098 A JPH0425098 A JP H0425098A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- substrate
- dielectric
- ceramic multilayer
- high dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 36
- 239000000919 ceramic Substances 0.000 title claims description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 239000003989 dielectric material Substances 0.000 claims abstract description 10
- 238000010030 laminating Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 13
- 230000032798 delamination Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- UVTGXFAWNQTDBG-UHFFFAOYSA-N [Fe].[Pb] Chemical compound [Fe].[Pb] UVTGXFAWNQTDBG-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 235000013405 beer Nutrition 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器等の回路に広く用いることのできる
セラミック多層基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a ceramic multilayer substrate that can be widely used in circuits of electronic devices and the like.
従来の技術 近年、セラミック多層基板は熱伝導性や耐熱性。Conventional technology In recent years, ceramic multilayer substrates have improved thermal conductivity and heat resistance.
化学的耐久性等の点で有機材料基板よシ優れた特性を有
するため、有機材料基板に代るものとして、また電子機
器の小型化、多様化に伴い、高密度配線、高密度実装基
板として広く使用されるように2、、
なってきた。さらに、今後はコンテ゛ンザ等の受動部品
までその内部に内蔵するところのセラミック多層基板の
需要が高まると予想される。Because it has superior properties to organic material substrates in terms of chemical durability, etc., it can be used as an alternative to organic material substrates, and as electronic devices become smaller and more diverse, it can be used as high-density wiring and high-density mounting substrates. It has become widely used2. Furthermore, demand for ceramic multilayer substrates that incorporate passive components such as containers is expected to increase in the future.
以下図面を参照しながら従来のセラミック多層基板につ
いて説明する。A conventional ceramic multilayer substrate will be described below with reference to the drawings.
第2図は従来のセラミック多層基板の製造過程の一部を
示す断面図であり、第3図は従来の製造方法によシ作製
されたセラミック多層基板の断面図である。FIG. 2 is a sectional view showing a part of the manufacturing process of a conventional ceramic multilayer board, and FIG. 3 is a sectional view of a ceramic multilayer board manufactured by the conventional manufacturing method.
第2図に示すように、低誘電率を有する無機物粉体を主
成分としこれに熱可塑性樹脂等を添加して成形したセラ
ミックグリーンシート1aの必要個所に穿孔機等でビア
ホール2を形成し、その内部に導電ペーストを印刷等で
充填し導体層3を設ける。さらに他のセラミックグリー
ンシー)Ib上に導体ペーストで配線4やコンデンサ用
の電極ペースト5を印刷する。また高誘電率を有する無
機物粉体を主成分とし、これに熱可塑性樹脂等を添加し
て成形した高誘電体グリーンシート6にも同じく必要個
所に穿孔機等でビアホー/I/2を形成3 、−
し、その内部に導体層3を設ける。このように構成され
たグリーンシーI・を必要枚数順次積層した後、焼成す
ることによって第3図に示すセラミツ、り多層基板が得
られる。As shown in FIG. 2, via holes 2 are formed using a punching machine or the like at necessary locations on a ceramic green sheet 1a which is formed by adding a thermoplastic resin or the like to the inorganic powder having a low dielectric constant as a main component. A conductive layer 3 is provided by filling the inside with a conductive paste by printing or the like. Furthermore, wiring 4 and electrode paste 5 for capacitors are printed using conductive paste on another ceramic green sheet) Ib. In addition, beer holes/I/2 are similarly formed at necessary locations on the high dielectric green sheet 6, which is formed by molding an inorganic powder having a high dielectric constant and adding a thermoplastic resin, etc., to the inorganic powder 3. , - and a conductor layer 3 is provided therein. After sequentially stacking the required number of Green Sea I's thus constructed, the ceramic multilayer substrate shown in FIG. 3 is obtained by firing.
第3図において、7は高誘電体層、8は電極であり、9
は電極8によって挟まれたコンデンサである。また10
はビアホール、11はスル−ホーであり、高誘電体層7
や低誘電率セラミック層12に設けられている配線導体
13や電極8と電気的に接続している。In FIG. 3, 7 is a high dielectric layer, 8 is an electrode, and 9 is a high dielectric layer.
is a capacitor sandwiched between electrodes 8. 10 more
is a via hole, 11 is a through hole, and the high dielectric layer 7
It is electrically connected to the wiring conductor 13 and the electrode 8 provided on the low dielectric constant ceramic layer 12 .
一般的には、このように構成されたセラミック多層基板
に回路部品等を実装し、電子機器等に使用される。Generally, circuit components and the like are mounted on the ceramic multilayer substrate configured in this way and used in electronic devices and the like.
発明が解決しようとする課題
しかしながら上記従来の構成では、高誘電体層7に形成
された電極8間で、電位が異なる場合、電気容量が生じ
、したがってコンデンサ9を形成することができるが、
高誘電体層7」二に設けられているコンデンサ9を接続
する配線間や、信号線間にも電気容量が発生し、信号の
クロスト−りや遅延の原因となる。また高誘電体層γに
信号線等を配線し々い場合には、低誘電率セラミック層
12上に設けられている配線導体13間をスルーホ)v
llやビアホール10で接続しなければならず、第3図
に示すように高誘電体層7を貫通するビアホー/I/1
0とヌル−ホー/v11の間で不必要な電気容量を発生
するなど大きな課題があった。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, if the potentials differ between the electrodes 8 formed on the high dielectric layer 7, an electric capacitance occurs, and therefore a capacitor 9 can be formed.
Electrical capacitance also occurs between wirings connecting the capacitors 9 provided in the high dielectric layer 7'2 and between signal lines, causing signal crosstalk and delay. In addition, when wiring a signal line or the like to the high dielectric layer γ, the wiring conductors 13 provided on the low dielectric constant ceramic layer 12 are connected through through holes)
The via hole /I/1 must be connected through the high dielectric layer 7 as shown in FIG.
There were major problems such as unnecessary capacitance being generated between 0 and Null-Ho/v11.
さらに、セラミック多層基板に内蔵されるコンデンサ9
の容量を大きくするだめには高誘電体層7の暦数を増加
させる必要がちシ、したがってセラミック多層基板に占
める高誘電体ノー7の体積も大きくな9、低誘電率セラ
ミク層12と高誘電体層7を同時に焼成する際、その境
界面にクラックを生じたり、層間剥離を生じるという極
めて重大な課題を有していた。Furthermore, the capacitor 9 built into the ceramic multilayer board
In order to increase the capacitance of the high dielectric layer 7, it is necessary to increase the number of high dielectric layers 7, and therefore the volume of the high dielectric layer 7 that occupies a large amount of the ceramic multilayer substrate 9. When the body layers 7 are fired at the same time, there is a very serious problem in that cracks occur at the interface between them and delamination occurs.
本発明は、上記課題を解決するものであり、信号線間に
クロストークや信号の遅延などの障害を発生することの
ない信頼性に優れたセラミック多層基板を提供すること
を目的とするものである。The present invention is intended to solve the above-mentioned problems, and aims to provide a highly reliable ceramic multilayer board that does not cause problems such as crosstalk or signal delay between signal lines. be.
課題を解決するための手段
5ぺ−7
本発明は上記目的を達成するために、セラミック多層基
板を構成する低誘電率基板に複数個のビアホールとスル
ーホールを設け、必要とする数のビアホールとスルーホ
ールの内部に高誘電体4.J 全充填し、基板の内部に
コンデンサを内蔵する構成としたものである。Means for Solving the Problems Page 5 - 7 In order to achieve the above object, the present invention provides a plurality of via holes and through holes in a low dielectric constant substrate constituting a ceramic multilayer substrate, and provides the required number of via holes and through holes. 4. High dielectric material inside the through hole. J is completely filled and has a structure with a built-in capacitor inside the board.
作 川
したがって本発明は」二層した構成によって不必要な電
気容量を発生することがないので、信号線間にクロスト
−りや信号の遅延などの障害を生じることがなく、また
高誘電体層と低誘電率セラミック層の同時焼成時に発生
する収縮歪によるクラックや層間剥離という現象を避け
ることもできる。Sakukawa Therefore, the present invention does not generate unnecessary capacitance due to the two-layer structure, so there is no problem such as crosstalk or signal delay between signal lines, and the high dielectric layer It is also possible to avoid phenomena such as cracks and delamination due to shrinkage strain that occur during simultaneous firing of low dielectric constant ceramic layers.
実施例
以下、本発明の一実施例について図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の構成を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.
同図において21はアルミナやガラス等からなる低誘′
「E率基板、22は鉄・鉛系ペロフヌカイl−4gを主
成分とする高誘電体材、23は内層導体、24は表面導
体、25は内層導体23と表面導体24を電気的に接続
するスルーホール導体である。高誘電体材22は内層基
板を構成する低誘電率基板21に設けられている多数の
スルーホル26の必要個所に充填されている。In the figure, 21 is a low dielectric material made of alumina, glass, etc.
``E-rate board, 22 is a high dielectric material mainly composed of iron-lead-based perovunkai l-4g, 23 is an inner layer conductor, 24 is a surface conductor, and 25 is an electrical connection between the inner layer conductor 23 and the surface conductor 24. The high dielectric material 22 is a through-hole conductor.The high dielectric material 22 is filled in necessary locations of a large number of through holes 26 provided in a low dielectric constant substrate 21 constituting an inner layer substrate.
次に」二層実施例の動作について説明する。」二層実施
例において、表面導体24は低誘電率基板210両面に
形成されてい配線(図示せず)を電気的に接続しておシ
、内層導体23は内層基板を形成している低誘電率基板
21の表面に形成されている配線を構成すると同時に低
誘電率基板21のスルーホール26に充填されている高
誘電体層22の電極として動作し、高誘電体材22とと
もにスルーホール26またはビアホール27の内部でコ
ンデンサ28を構成している。Next, the operation of the two-layer embodiment will be described. In the two-layer embodiment, the surface conductor 24 is formed on both sides of the low dielectric constant substrate 210 to electrically connect wiring (not shown), and the inner layer conductor 23 is the low dielectric conductor 23 forming the inner layer substrate. At the same time, it constitutes the wiring formed on the surface of the low dielectric constant substrate 21, and acts as an electrode for the high dielectric layer 22 filled in the through holes 26 of the low dielectric constant substrate 21. A capacitor 28 is configured inside the via hole 27.
以」二のように本実施例によれば、セラミック多層基板
に内蔵するコンデンサ28をグリーンシトとして作成す
る必要がなくスルーホール26やビアホール27の内部
に設けることができまた高誘電体層22の量を低誘電率
基板21の量に比較了\−2
して極めて少なくすることができるので低誘電率JI(
板21と高誘電体制22との収縮率の差による影響が小
さく、クラックや層間剥離等の障害を防止することがで
きる。As described below, according to this embodiment, the capacitor 28 built into the ceramic multilayer substrate does not need to be formed as a green sheet, and can be provided inside the through hole 26 or via hole 27, and the capacitor 28 built in the high dielectric layer 22 The amount can be extremely small compared to the amount of the low dielectric constant substrate 21, so the low dielectric constant JI (
The effect of the difference in shrinkage rate between the plate 21 and the high dielectric structure 22 is small, and problems such as cracks and delamination can be prevented.
なお、本実施例において、低誘電率基板21の4J別と
してアルミナとガラスを主成分としたが低誘電率を有す
る制別であれば他のセラミック利を使用することもでき
、寸だ高誘電体材として鉄鉛系ペロブスカイ1−を使用
しだが、高誘電率を有するイ2料であれば他の誘電利料
を使用することもできる。In this embodiment, alumina and glass were used as the main components for the 4J of the low dielectric constant substrate 21, but other ceramic materials can be used as long as they have a low dielectric constant. Although iron-lead based perovsky 1- is used as the body material, other dielectric materials can be used as long as they have a high dielectric constant.
発明の効果
以−1−のように本発明によれば、低誘電率基板に複数
個のビアホールとヌルーホールヲ設け、必要とする数の
ビアホールとスルーホールの内部に高誘電体制を充填し
て順次積層することによって多層セラミック基板の内部
にコンデンサを形成しているので、信号線が高誘電体制
を挟んで向い合うことがなく、クロスドータや信号の遅
延等の障害がなくなり、したがって配線密度を」−げる
ことができる。Effects of the Invention As described in -1-, according to the present invention, a plurality of via holes and null holes are provided in a low dielectric constant substrate, and the required number of via holes and through holes are filled with a high dielectric structure and laminated sequentially. By doing this, a capacitor is formed inside the multilayer ceramic substrate, so the signal lines do not face each other with a high dielectric layer in between, eliminating problems such as cross daughters and signal delays, and thus reducing wiring density. can be done.
さらに高誘電体制がセラミック多層基板全体に占める割
合いが小さいために低誘電率基板の材料との収縮率の差
による歪が小さく、層間でクラックや層間剥離等が発生
しないという利点を有する。Furthermore, since the high dielectric structure occupies a small proportion of the entire ceramic multilayer substrate, the strain caused by the difference in shrinkage rate with the material of the low dielectric constant substrate is small, and there is an advantage that cracks and delamination between the layers do not occur.
第1図は本発明の一実施例におけるセフミック多層基板
の断面図、第2図は従来のセラミック多層基板の製造過
程の一部を示す断面図、第3図は同セラミック多層基板
の断面図である。
21・・・・低誘電率基板、22・・・・・高誘電体制
、26・・・・・・スルーホール、27・・・・・・ビ
アホール、28・・・・・コンデンサ。Fig. 1 is a sectional view of a cefmic multilayer board according to an embodiment of the present invention, Fig. 2 is a sectional view showing part of the manufacturing process of a conventional ceramic multilayer board, and Fig. 3 is a sectional view of the same ceramic multilayer board. be. 21...Low dielectric constant substrate, 22...High dielectric system, 26...Through hole, 27... Via hole, 28... Capacitor.
Claims (1)
基板において、前記低誘電率基板に複数個のビアホール
と複数個のスルーホールを形成し、必要とする数の前記
ビアホールとスルーホールの内部に高誘電体材を充填し
、基板の内部にコンデンサを内蔵する構成としたセラミ
ック多層基板。In a ceramic multilayer substrate formed by laminating a plurality of low dielectric constant substrates, a plurality of via holes and a plurality of through holes are formed in the low dielectric constant substrate, and a required number of via holes and through holes are formed. A ceramic multilayer board filled with a high dielectric material and with a built-in capacitor inside the board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2127294A JPH0425098A (en) | 1990-05-16 | 1990-05-16 | Ceramic multilayer substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2127294A JPH0425098A (en) | 1990-05-16 | 1990-05-16 | Ceramic multilayer substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0425098A true JPH0425098A (en) | 1992-01-28 |
Family
ID=14956405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2127294A Pending JPH0425098A (en) | 1990-05-16 | 1990-05-16 | Ceramic multilayer substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0425098A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994007348A1 (en) * | 1992-09-24 | 1994-03-31 | Hughes Aircraft Company | Dielectric vias within multilayer 3-dimensional structures/substrates |
US6200400B1 (en) * | 1998-01-15 | 2001-03-13 | International Business Machines Corp. | Method for making high k dielectric material with low k dielectric sheathed signal vias |
-
1990
- 1990-05-16 JP JP2127294A patent/JPH0425098A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994007348A1 (en) * | 1992-09-24 | 1994-03-31 | Hughes Aircraft Company | Dielectric vias within multilayer 3-dimensional structures/substrates |
US6200400B1 (en) * | 1998-01-15 | 2001-03-13 | International Business Machines Corp. | Method for making high k dielectric material with low k dielectric sheathed signal vias |
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