JPH04250635A - Manufacture of two dimensional electron gas field effect transistor - Google Patents

Abstract

PURPOSE:To reduce source resistance of an FET using InAs as a channel. CONSTITUTION:In a two dimensional electron gas field effect transistor using an InAs layer for a channel and AlxGa1-xSb for a potential barrier layer, the structure between a gate and a source is composed by forming Si3N4 on the InAs channel surface by a plasma CVD(Chemical Vapor Deposition) method, or formed by introducing plasma of hydrogen or ammonia on the InAs layer so as to cause damage to the InAs layer, increase electron density and reduce sheet resistance. In consequence, source resistance of the FET is reduced so as to enable a high speed FET to be manufactured.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor using a compound semiconductor.

0002

2. Description of the Related Art A conventional two-dimensional electron gas field effect transistor in a semiconductor is obtained by forming a gate, source, and drain in a structure in which n-type AlGaAs is formed on or on both sides of an undoped GaAs layer, for example. ing(
For example, Mimura et al., Japanese Journal of Applied Physics, Volume 19 (1990) L225
page). Electrons move from the n-type AlGaAs layer to the GaAs layer, but since the GaAs layer is undoped, there are few electron scatterers, and the n-type AlGaAs layer that supplied the electrons is ionized, but is far from the GaAs layer. Therefore, electrons can travel at high speed without being scattered. By applying this high electron mobility to FETs, high-speed transistors can be obtained.

[0003] If the materials are InAs and AlGaSb, F
With ET, you can get faster speeds. If the layer structure is made such that the undoped InAs layer 2 is sandwiched between the AlGaSb layers 1 on both sides as shown in FIG. 3, the mobility of the electrons accumulated in the InAs layer 2 will be about 20,000 cm2/Vs at room temperature (
For example, G. Tuttle et al., AlSb/InAs/A
lSb quantum well heterojunction FET, Device・Re
search・Conference (1987) IIA
-7). The reason why such a large mobility is obtained is that the effective mass of electrons in InAs is as small as 0.027 me (me is the mass of free electrons). This structure has gates and
If a FET is manufactured by forming a source and a drain, an FET with very good characteristics can be manufactured.

By the way, a problem with FETs is how to reduce the source resistance. Reducing source resistance is important for increasing the speed of FETs. To reduce the source resistance, use the layer structure shown in Figure 3 to create a depletion type FET.
If the source electrode is formed from an alloy with a structure in which InAs is sandwiched between AlSb, the electron concentration between the gate 5 and the source 4 can be high and low resistance can be achieved. On the other hand, in the enhancement type FET, since there are no electrons in the area between the gate 5 and the source 4, it is necessary to implant Si ions into this area and then activate it to form electrons in this area. The problem with the former FET is that it is difficult to control the alloy of this material system, and the alloy ends up on the substrate. If a GaAs substrate, which is not lattice-matched to this material system, is used as the substrate, there is an insulating substrate, so the alloy up to the substrate is not a particular problem, but if a GaSb substrate, which is lattice-matched, is used, there is no insulating substrate. Therefore, FET operation becomes impossible. The electron mobility is G, which is not lattice matched.
Since it is 1.5 to 2 times larger when using a lattice-matched GaSb substrate than when using an aAs substrate,
Basically, it is most preferable to use a GaSb substrate. The problem with the latter case is that it involves a laborious process of ion implantation and activation. In this case as well, it is preferable to use GaSb as the substrate because a higher mobility can be achieved.

By the way, when the surface of InAs is exposed,
It is known that the Fermi level is pinned in the conduction band and electrons are accumulated on the surface. Therefore, in a FET, a low source resistance can be easily achieved by exposing the InAs surface from the source to the source end of the gate and forming a non-alloy metal as the source on the InAs. This is the same for both depression type and enhancement type FETs. The sheet resistance in this case is approximately 30
It is about 0Ω/□. This value can be said to be very small as a value that can be easily realized, but since the characteristics of this type of FET are very good, further reduction is required.

[0006]

[Problem to be solved by the invention] In a FET using InAs for the channel, if the InAs surface is exposed from the source to the source end of the gate and a non-alloyed metal is formed as the source on the InAs, the resistance can easily be reduced to about 300 Ω/□. Low source resistance can be achieved. However, although this value can be said to be small for a value that can be easily achieved, there has been a demand for further reduction because the characteristics of this type of FET are very good.

The purpose of the present invention is to solve these problems and
The object of the present invention is to provide a high-speed manufacturing method for FETs that realizes low source resistance.

[0008]

[Means for Solving the Problems] In order to achieve the above object, in the method for manufacturing a two-dimensional electron gas field effect transistor according to the present invention, an InAs layer is used for the channel, and an InAs layer is used for the channel.
In a method for manufacturing a two-dimensional electron gas field effect transistor using lxGa1-xSb as a potential barrier layer,
Plasma C is applied on the InAs channel surface between the gate and source.
VD (Chemical/vapour/deposit)
tion) method to form Si3N4.

Further, in the present invention, in a method for manufacturing a two-dimensional electron gas field effect transistor using an InAs layer as a channel and AlxGa1-xSb as a potential barrier layer, the InAs channel surface between the gate and source is heated with hydrogen or It is exposed to ammonia plasma.

Further, in the present invention, in a method for manufacturing a two-dimensional electron gas field effect transistor using an InAs layer as a channel and AlxGa1-xSb as a potential barrier layer, the InAs channel surface between the gate and source is heated with hydrogen or Si3N after exposure to ammonia plasma
4.

[0011]

[Operation] When the surface of InAs is exposed in air or vacuum, the Fermi level is pinned in the conduction band, and electrons are accumulated on the surface at a density of about 1×10 12 cm −2 . In this case, the sheet resistance is approximately 300Ω/□. When Si3N4 is formed on the surface of this InAs by plasma CVD, which is the method of the present invention, an electron concentration of about 5 x 1012 cm-2 is formed at the interface between InAs and Si3N4,
As a result, the sheet resistance is reduced to about 100 to 150 Ω/□.

This is because when Si3N4 is formed by mixing silane and ammonia plasma, electrons are induced by plasma damage. This increase in electron concentration can be achieved by exposing the InAs surface to plasma, for example, by exposing it to hydrogen or ammonia plasma for about 1 second to 1 minute, regardless of the presence or absence of Si3N4 formation. By this method, many electrons are induced on the InAs surface and the sheet resistance can be reduced. Further, after exposure to these plasmas, Si3N4 may be formed as a protective film thereon.

In an FET, if the structure between the gate and the source is as shown in the present invention, as described above,
A high concentration of electrons can be induced on InAs, and the sheet resistance can be reduced to about 100 to 150 Ω/□. Therefore, the source resistance can be reduced to about half compared to the case where only the InAs surface is exposed, and the speed of the transistor can be increased to about twice.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of an FET corresponding to claims 1 and 3 of the present invention. GaSb is used for the substrate 3, and under the gate 5, an AlGaSb layer 1 (thickness 200 angstroms) is formed on both sides of an InAs layer 2 (thickness 200 angstroms).
It has a sandwiched structure. The source 4 and drain 6 are formed by non-alloy vapor deposition of metal (Al, Au, etc.) on the InAs surface. Between the gate 5 and source 4 and between the source 4 and drain 6 are S on the InAs surface.
An i3N4 film 7 is formed. In the method of claim 1, I
Plasma CVD (Chemical Vap) on nAs surface
The Si3N4 film 7 is formed by the our-deposition method.
Before forming S, it is exposed to hydrogen or ammonia plasma for about 10 seconds, and then S
An i3N4 film 7 is formed. The growth of the layered structure is e.g.
It can be produced by the BE method.

FIG. 2 shows an FET corresponding to claim 2 of the present invention.
shows the structure of The substrate 3 is made of GaSb, and the structure below the gate 5 is such that an InAs layer 2 (thickness: 200 angstroms) is sandwiched between AlGaSb layers 1 (thickness: 200 angstroms) on both sides. The source 4 and drain 6 are formed by non-alloy vapor deposition of metal (Al, Au, etc.) on the InAs surface. The InAs surfaces between the gate 5 and source 4 and between the source 4 and drain 6 are exposed and exposed to hydrogen or ammonia plasma for about 10 seconds.
The nAs surface remains exposed.

[0016]

According to the method of the present invention, the source resistance of the FET can be reduced to about half that of the conventional method, and a high-speed transistor can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an FET structure according to claims 1 and 3 of the present invention.

FIG. 2 is a sectional view showing an FET structure according to claim 2 of the present invention.

FIG. 3 is a cross-sectional view showing a conventional FET structure.

[Explanation of symbols]

1 AlGaSb layer 2 InAs layer 3 Board 4. Sauce 5 Gate 6 Drain 7 Si3N4 film

Claims (3)

[Claims] Claim 1: An InAs layer is used for the channel, and Alx
In a method for manufacturing a two-dimensional electron gas field effect transistor using Ga1-xSb as a potential barrier layer,
Plasma C is applied on the InAs channel surface between the gate and source.
VD (Chemical/vapour/deposit)
A method for manufacturing a two-dimensional electron gas field effect transistor, characterized in that Si3N4 is formed by a method. [Claim 2] An InAs layer is used for the channel, and Alx
In a method for manufacturing a two-dimensional electron gas field effect transistor using Ga1-xSb as a potential barrier layer,
A method for manufacturing a two-dimensional electron gas field effect transistor, which comprises exposing an InAs channel surface between a gate and a source to hydrogen or ammonia plasma. 3. Using an InAs layer for the channel, Alx
In a method for manufacturing a two-dimensional electron gas field effect transistor using Ga1-xSb as a potential barrier layer,
A method for manufacturing a two-dimensional electron gas field effect transistor, characterized in that Si3N4 is formed after exposing an InAs channel surface between a gate and a source to hydrogen or ammonia plasma.