JPH04247761A - Synchronization detection circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to noise and to keep a synchronization timing constant even at fluctuation of luminous quantity by bringing a level of one output of two photoelectric conversion elements when no optical beam is made incident forcibly to a prescribed clamp level. CONSTITUTION:Photodiodes PD1, PD2 are arranged in cascade in the beam scanning direction and an optical current output is subject to amplification and I/V conversion by amplifiers A1, A2 to obtain voltages V1, V2. The voltage V2 is inputted to a lower limit clamp circuit 5, which clamps a level when no optical beam is made incident to a prescribed level V21. Then the level V21 is set higher than a predicted noise level, the voltage is inputted to a comparator 6 together with the voltage V1 and the voltages V1 and V21 are compared to obtain a synchronization timing V0 representing the scanning timing. Thus, malfunction due to noise is prevented and the level V21 is set to obtain a cross point with respect to the voltage V1 and V21 even when the incident luminous quantity is low thereby keeping the cross point due to luminous quantity fluctuation, that is, the synchronization timing constant.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection circuit, and is used, for example, as a synchronization sensor for an optical scanning recorder.

0002

2. Description of the Related Art When a two-channel split photodiode is used as a synchronization sensor for an optical scanning recorder, its light receiving surface is arranged as shown in FIG. 3(a). That is, the rectangular light receiving surfaces of photodiode PD1 and photodiode PD2 are arranged along the scanning direction of the light beam. Therefore, the photocurrent outputs IPD1 and IPD2 of the photodiodes PD1 and PD2 become as shown in FIG. cross each other. Therefore, this cross point can be detected as the synchronization timing.

A conventional synchronization detection circuit is configured as shown in FIG. In the synchronous detection circuit shown in (a) of the same figure, the output photocurrents of photodiodes PD1 and PD2 are amplified and I/V converted by amplifiers A1 and A2, respectively, and the output V1
, V2 are input to the differential amplifier 1. The differential output V3 is then compared with a predetermined reference level E by a comparator 2 to obtain a synchronous timing output V0. Here, the differential output V3 is as shown in Figure 5(a), and the synchronous timing output V0 is as shown in Figure 5(b), so the light beam is transmitted between the photodiode PD1 and the photodiode PD.
The time point t2 when the boundary of 2 is passed is determined. Figure 4(b)
In the synchronization detection circuit, when comparing the I/V conversion outputs V1 and V2 with the comparator 3, one of the outputs V2
Apply a constant bias E to the synchronous timing output V0
I am getting .

The conventional circuits shown in FIG. 4 are both optical push-pull circuits, and the technology is the same in that the output of the photodiode PD1 and the output of the photodiode PD2 are compared. In both cases, when the light beam is not incident on either photodiode PD1 or PD2, the state of the output V0 may not be determined, so in the circuit shown in FIG. In addition, in the circuit shown in FIG. 6(b), a bias E is added to the output V2. Also, instead of the reference level E or bias E, the comparator may have hysteresis.

[0005]

[Problems to be Solved by the Invention] However, by providing the comparator with hysteresis or adding a bias in this way, the synchronization timing fluctuates over time when the amount of light changes. This will be explained with reference to FIG. In the figure, the solid line indicates the I/V conversion output of the photocurrent when the amount of light incident on the photodiode PD is at a high level, and the dotted line indicates the I/V conversion output of the photocurrent when the amount of light incident on the photodiode PD is at a low level. Further, FIG. 11A shows a state in which the aforementioned bias (hysteresis is also the same) is large, and FIG. 6B shows a state in which it is small. Here, in addition to electromagnetic induction disturbance noise, the noise can be considered to be noise caused by reflected light when a light beam is incident on the frame portion of the package, reflected by the upper surface of the package and incident on the light receiving surface.

Therefore, if the bias (or hysteresis) is set high in consideration of this noise level, malfunctions will not occur as shown in FIG. 6(a), but the synchronization timing will vary depending on the level of light intensity. . Therefore, in order to reduce the time fluctuation of the synchronization timing, we
If the above bias or hysteresis is made small, the synchronization detection circuit will malfunction due to noise, and an incorrect synchronization timing signal will be output.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, it is an object of the present invention to provide a synchronization detection circuit whose synchronization timing does not change due to changes in the amount of light and which does not malfunction due to noise.

[0008]

[Means for Solving the Problems] A synchronization detection circuit according to the present invention detects the scanning timing of a light beam based on the outputs of two photoelectric conversion elements whose light receiving surfaces are arranged along the scanning direction of the light beam. In the detection circuit, two Is are used to convert the photocurrent outputs of the two photoelectric conversion elements into current/voltage, respectively.
/V conversion means, a clamping means for clamping and outputting the output level of one I/V conversion means to a predetermined level in a state where no light beam is incident on the light receiving surface of one photoelectric conversion element; The present invention is characterized by comprising a comparing means for outputting a synchronization timing signal indicating the scanning timing by comparing the output of the I/V converting means and the output of the clamping means.

[0009]

[Operation] According to the present invention, the output level of one photoelectric conversion element when no light beam is incident is clamped to a predetermined level, so malfunctions due to noise that does not reach this predetermined level are prevented. do not have. In addition, only the output level when no light beam is incident is clamped, and other levels are kept as they were, so the time of the cross point (synchronization timing) remains constant even if the light intensity fluctuates. Retained.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a synchronization detection circuit according to an embodiment. The light receiving surfaces of photodiodes PD1 and PD2 are arranged as shown in Figure 3(a), and the respective photocurrent outputs are amplified and I/V converted by amplifiers A1 and A2, and output as voltage outputs V1 and V2. be done. Here, the output V2 is input to the lower limit clamp circuit 5, and the level when no light beam is incident is clamped to a constant value, and is input to the comparator 6 as the clamp output V21. This clamp level is set to exceed the expected noise level, and is set to a level so that the cross point of the outputs V1 and V21 can be obtained even when the amount of light incident on the photodiodes PD1 and PD2 becomes low. be done.

FIG. 2 shows the operation of the circuit of the above embodiment,
Figure (a) shows the I/V conversion output V1 corresponding to the photocurrent output of the photodiode PD1 and the photodiode P
The photocurrent output of D2 is I/V converted and lower limit clamped to output V21, and FIG.
The synchronization timing output V0 obtained as the cross point of V1 and V21 is shown for both high and low light levels. Regarding output V21, the lower limit is clamped,
Since the level of the waveform does not change at all in the portion exceeding the clamp level, the cross point, that is, the time of the synchronization timing does not change even if the amount of light changes. On the other hand, even if there is noise below the clamp level, no cross points will appear, so malfunctions will not occur. Moreover, even when there is no incident light, no cross points occur, so an uncertain state in which the output is not determined can be avoided.

In the above embodiment, the lower limit clamp circuit 5
is provided between the I/V conversion amplifier A2 and the comparator 6, but it may also be built into the amplifier A2 or the comparator 6. Furthermore, if the polarity of the amplifier A2 is reversed, upper limit clamping may be performed instead of lower limit clamping. Furthermore, when clamping the output of the amplifier A1 instead of the amplifier A2, the falling point of the output of the comparator 6 may be used as the synchronization timing to be detected.

[0014]

[Effects of the Invention] As explained above in detail, the present invention provides
Since the output level of one photoelectric conversion element when no light beam is incident is forcibly clamped to a predetermined clamp level, malfunctions will not occur due to noise that does not reach this clamp level. Also, only the output level when no light beam is incident is clamped, and the other levels are kept as they were.
The time of the cross point (synchronized timing) even if the light intensity fluctuates
is held constant. Therefore, it is possible to provide a synchronization detection circuit whose synchronization timing does not change due to changes in the amount of light and which does not malfunction due to noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a synchronization detection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of the circuit in FIG. 1;

FIG. 3 is a diagram showing the arrangement of photodiode PD1 and photodiode PD2 and I/V conversion output of photocurrent.

FIG. 4 is a circuit diagram of a conventional synchronization detection circuit.

FIG. 5 is a waveform diagram showing the operation of the circuit in FIG. 4;

FIG. 6 is a waveform diagram showing a drawback of the prior art.

[Explanation of symbols]

PD1, PD2...Photodiode V0...Synchronization timing signal 5...Lower limit clamp circuit 6...Comparator

Claims (2)

[Claims] 1. A synchronization detection circuit that detects the scanning timing of the light beam based on the outputs of two photoelectric conversion elements whose light-receiving surfaces are arranged along the scanning direction of the light beam. two I/V conversion means for converting the photocurrent output of the conversion element into current/voltage, and one of the I/V in a state where the light beam is not incident on the light receiving surface of one of the photoelectric conversion elements; clamping means for clamping the output level of the converting means to a predetermined level and outputting it;
A synchronization detection circuit comprising: comparison means for outputting a synchronization timing signal indicating the scanning timing by comparing the output of the other I/V conversion means and the output of the clamping means. 2. The clamping means is connected to the one I/V.
Claim 1 built in the converting means or the comparing means
The synchronization detection circuit described.