JPH04219851A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is applicable to SCSI (Small
Computer System Interface
e) It relates to a semiconductor integrated circuit that inputs and outputs signals via a bus. In recent years, the number of SCSI devices equipped with controls based on the SCSI standard has increased, and there is also a demand for miniaturization of these devices.

0002

2. Description of the Related Art An example of a conventional SCSI system will be described with reference to FIG. 3. A SCSI control circuit 1 and a number of external circuits 2 each have a pair of data lines DBi and
The input data line DBi transfers data from each external circuit 2 to the SCSI control circuit 1, and the output data line DBo transfers data from the SCSI control circuit 1 to each external circuit 2. . For example, a pair of data input/output lines DBi, DBo
1 bit of data is transferred.

Each data line DBi, DBo is first connected to a pair of SCSI via a switching circuit 2a in each external circuit 2.
Connected to bus 3. That is, the SCSI bus 3 is connected to the input buffer circuit 4a, and the output signal output from the SCSI bus 3 to the input buffer circuit 4a is sent to the SCSI control circuit 1 via the input data line DBi.
The signal is input to the input buffer circuit 5a in the internal input buffer circuit 5a. Also, SCS
The output signal output from the I control circuit 1 to the output buffer circuit 5b is input to the output buffer circuit 4b in the switching circuit 2a via the output data line DBo, and is output from the output buffer circuit 4b to the SCSI bus 3. . Note that each of the buffer circuits 4a to 4b has input/output characteristics that satisfy the SCSI standard.

The input buffer circuit 5b in the SCSI control circuit 1 and the input/output buffer circuits 4a and 4b constituting the switching circuit 2a are controlled based on the switching signal CH output from the SCSI control circuit 1,
Each of them is activated when an H level control signal is input. The switching signal CH is inverted and inputted to the output buffer circuit 5b in the SCSI control circuit 1, and the switching signal CH is inputted to the output buffer circuit 4b in the switching circuit 2a via the inverter 6 and the signal line DBoe. , are further inverted and input to the input buffer circuit 4a.

In such a SCSI system, when the switching signal CH becomes H level, the input buffer circuit 4a in the switching circuit 2a is activated, and the output buffer circuit 4b in the switching circuit 2a and the SCSI control circuit 1 are activated.
Since the internal output buffer circuit 5b is inactive, the SCSI bus 3 and input data line DBi are connected from the external circuit 2.
When data is transferred to the SCSI control circuit 1 through becomes inactive, SCSI
Data is transferred from the control circuit 1 to the SCSI bus 3 via the signal line DBo and the switching circuit 2a.

[0006]

[Problem to be Solved by the Invention] However, in the above-mentioned SCSI system, each input/output data line DBi, D
Since a signal line DBoe is required for each switching circuit 2a provided between the SCSI bus 3 and the SCSI bus 3, the system is multi-bit, and the input/output data lines DBi, DBo and the associated switching circuit 2a are required. As the number of SCSI control circuits 1 increases, the number of terminals of the SCSI control circuit 1 increases, which becomes an obstacle to miniaturization.

An object of the present invention is to provide a SCSI system that does not require an increase in the number of terminals of a SCSI control circuit in proportion to the increase in the number of bits in the SCSI system.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, the SCSI control circuit 1 and a large number of external circuits 2 are connected to input/output data lines DBi and DBo.
A control signal for controlling the operation of each external circuit 2 is output from the SCSI control circuit 1 as a digital binary signal, and based on the digital binary signal, a predetermined external circuit is selected from a large number of external circuits 2. A decoder 7 that selects a circuit and outputs a control signal is interposed between the SCSI control circuit 1 and the external circuit 2.

[0009]

[Operation] Based on the digital binary signal output from the SCSI control circuit 1, the decoder 7 outputs a control signal to a predetermined external circuit from among a large number of external circuits 2 to control the operation of the external circuit 2.

0010

[Example] An example embodying this invention is shown below in Figure 2.
Explain according to the following. Incidentally, the same components as those of the conventional example are given the same numbers and the explanation thereof will be omitted. This embodiment includes input/output data lines DBi, DBo, input/output buffer circuits 4a, 4b in the external circuit 2 connected to the input/output data lines DBi, DBo, input/output buffer circuits 5a, 5a in the SCSI control circuit 1, 5b has the same configuration as the conventional example. The means for transferring control signals that control the operations of the input/output buffer circuits 4a and 4b in the external circuit 2 are different.

That is, the decoder 7 interposed between the SCSI control circuit 1 and the external circuit 2 has a SCSI
An output control signal OE for collectively controlling the selection signals SL1 to SL3 based on 3-bit digital binary signals and the output signal of the decoder 7 is input from the control circuit 1. The decoder 7 is provided with eight output terminals, each with an NA
It is connected to one input terminal of the ND circuit 8. When the H level output control signal OE is input to the decoder 7, all output signals of the decoder 7 become H level and L
When the selection signals SL1 to SL3 are input while the level output control signal OE is input, the selection signal SL
The binary signals 1 to SL3 are converted into decimal numbers, and an L level signal is output from one output terminal corresponding to the converted number.

The other input terminal of each NAND circuit 8 receives a control signal C from the SCSI control circuit 1.
TL is output, and the output signal of each NAND circuit 8 is output to the switching circuit 2a in the external circuit 2, respectively. When an H level signal is output from each NAND circuit 8, the output buffer circuit 4b of each switching circuit 2a is activated, and when an L level signal is output, the input buffer circuit 4a is activated.

Now, in the SCSI system configured as described above, 8
When selecting one data bus from the data buses DBo, the SCSI control circuit 1 outputs an L level output control signal OE and an H level control signal C.
When TL is output and selection signals SL1 to SL3 are input in this state, the decoder 7 outputs the 3-bit digital 2
Any one of the output terminals corresponding to the forward signal becomes L level. Then, since one of the NAND circuits 8 outputs an H level signal, the output buffer circuit 4b is activated in the switching circuit 2a connected to that NAND circuit 8, and the output data line DBo is transferred from the SCSI control circuit 1 to the output data line DBo. The data is transferred to the selected external circuit 2 via.

On the other hand, since all output data lines DBo can be used in parallel during output operations other than arbitration operations, it is necessary to set all output signals of each NAND circuit 8 to H level. To do this, if the control signal CTL is set to L level, the selection signals SL1 to SL
3, the output signal of each NAND circuit 8 becomes H level, and each output data line DBo can be used simultaneously.

Furthermore, since all input data lines DBi can be used simultaneously during input operation, the output control signal O
When E is set to H level, all the output signals of the decoder 7 are set to H level, and the control signal CTL is set to H level, all the output signals of each NAND circuit 8 are set to L level, and each input data line DBi can be used at the same time. Become.

As described above, in this SCSI system, 8
To control the operation of each switching circuit 2a corresponding to the input/output data lines DBi and DBo for bits, the SCSI control circuit 1 sends output control signals OE,
It is sufficient to output five types of signals: the control signal CTL and the selection signals SL1 to SL3. Therefore, eight terminals are required to output a control signal for each switching circuit 2a, but this can be reduced to five. The reduced number of terminals is the input/output data lines DBi, DBo.
It becomes larger as the number of lines, that is, the number of bits increases.

[0017]

[Effects of the Invention] As detailed above, this invention provides SCS
This provides an excellent effect of preventing the number of terminals of the SCSI control circuit from increasing in proportion to the increase in the number of bits in the I system.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a system configuration diagram showing one embodiment of the present invention.

FIG. 3 is a system configuration diagram showing a conventional example.

[Explanation of symbols]

1 SCSI control circuit 2 External circuit 7 Decoder

Claims (1)

[Claims] Claim 1: A SCSI control circuit (1) and a large number of external circuits (2) are connected to data lines (DBi, DBo).
), the SCSI control circuit (1) outputs a control signal for controlling the operation of each external circuit (2), and the SCSI control circuit (1) outputs a digital signal as the control signal. It outputs a binary signal and connects many external circuits (
The decoder (7) that selects a predetermined external circuit from 2) and outputs a control signal is connected to the SCSI control circuit (1).
and an external circuit (2).