JPH04211832A - Information processor - Google Patents

Abstract

PURPOSE:To prevent an output pulse from being interrupted even if the period of the input of an external clock becomes short by permitting the reset of pulse output after inhibiting the reset of the pulse output and updating a comparing register in response to the set signal of the pulse output. CONSTITUTION:An event counter 223 counts the external clock, and a first comparing register 224 compares this count value with a set value. On the other hand, a free-running counter 201 counts an internal clock, and second comparing registers 210 to 21n compare this count value with the set value. A first flip flop 226 is set by a coincidence signal from the comparing register 22, and is reset by the write signal of the set value of the comparing registers 210 to 21n. Second flip flops 240 to 24n are set by the coincidence signal from the comparing register 224, and is reset by the output of the flip flop 226 and the coincidence signal from the comparing registers 210 to 21n.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for controlling peripheral equipment using clock input from the peripheral equipment.

0002

2. Description of the Related Art Pulse generators are widely used for controlling peripheral devices that perform various real-time controls, including automobile engine control.

The prior art will be explained below with reference to FIGS. 1, 8, and 9. Figure 1 is a block diagram of the pulse generator.
The pulse generator 100 is a central processing unit (hereinafter referred to as CPU).
) 101, interrupt request generation circuit (hereinafter referred to as INT
102, peripheral hardware 103, and peripheral bus 104.

[0004] Also, the peripheral hardware 103 includes an INT
Output interrupt signal 105 to C102, INTC
102 performs priority determination of these interrupt signals and outputs an interrupt request signal 106 to the CPU 101. Upon receiving the interrupt request signal, the CPU 101 performs predetermined processing according to a program preprogrammed in an internal or external memory.

FIG. 8 shows a free running counter (hereinafter referred to as FRC) 501 that counts an internal count clock φ inside the peripheral hardware 103;
Compare register A that compares with the counter value of 501
510 to 51n, a capture register 520 that captures the counter value of the FRC 501, an external clock input buffer 521, and an edge detection circuit 522 for the external clock input signal input from the input buffer 521.
An event counter 523 that counts the external clock detected by the edge detection circuit 522;
Compare register B524 compares with the counter value of counter 523, and is set by match signal 525 of compare register B524, and compare register A5
Flip-flop circuits (hereinafter referred to as F.F.) 540-54n that are reset by match signals 530-53n from F.10-51n; It is composed of output buffers 550 to 55n that output F540 to 54n. The match signal 525 of compare register B 524 resets the event counter 523 and also resets the capture register B 524.
Capture trigger signal of register 520 and INTC1
This is an interrupt signal to 02.

Referring to the timing chart of FIG. 9, the operation will be explained by taking as an example a pulse output of 0 output from the output buffer 550.

First, when a predetermined number of external clocks are input and the count value of the event counter 523 reaches the value preset in the compare register B524 and a match occurs, a match signal 525 is sent from the compare register B524.
is output, F. F540 is set and pulse output 0 becomes high level "1". The match signal 525 also becomes a capture trigger signal for the capture register 520, and the value D0 of the FRC 501 at that time is captured into the capture register 520, and the event counter 5
23 and further outputs an interrupt signal 105 to the INTC 102.

[0008] When the interrupt signal 105 is input, the INTC 102 performs processing to determine the priority order, etc.
An interrupt request signal 106 is output to U101. CPU
101 performs interrupt processing according to a preprogrammed program when an interrupt request signal 106 is input. Here, the value D0 of capture register 520
FRC501 corresponding to the desired pulse output width T0
A value obtained by adding the count number W0 of , D0 +W0, is written to the compare register 210.

Here, since the count clock is φ, T0 = W0 /φ (W0: number of counts, φ:
FRC501 count frequency) holds true.

When the FRC501 counts up and reaches the value D0 +W0, the compare register A51
A match signal 530 of 0 is output. The match signal 530 is
F. Reset F540 and set pulse output 0 to LOW level "0".

When the external clock is further input and the event counter is counted, a match with the compare register B524 occurs again, and the F. F540 is set and the pulse output 0 becomes high level "1" again.

Thereafter, by repeating the same operation, it is possible to obtain a pulse output with a high width T0 synchronized with the external clock input.

[0013]

However, when the period of the external input clock becomes shorter and the generation period of the match signal 525 of the compare register B524 becomes shorter than the pulse width T0, that is, the period TC in FIG. To become and,
F by match signal 525 of compare register B524
．． F540 is set to double and FRC501 is set to D before compare register A510 is updated from D2 +W0 to D3 +W0 by interrupt processing.
2 +W0, the value of compare register A510 matches, a match signal 525 is output, and F. F540 is
It will be reset.

[0014] Therefore, the external clock input period becomes shorter,
When the cycle of the match signal 525 of the compare register B524 becomes shorter than T0, the pulse output 0 set by the match signal 525 is not necessarily output for T0, so the cycle of the match signal 525 becomes the external output pulse width T0.
It needed to be longer than that.

[0015] As described above, in the conventional pulse output device, when the external clock input period becomes short and the period of the match signal of the compare register connected to the event counter becomes shorter than the external output pulse period T0, Even though you want to continue outputting a high level "1" as the external pulse output, the external pulse output is suddenly reset and, for example, when used for controlling the fuel injection of a car engine, it may not continue to inject fuel. If the pulse output is suddenly reset even when it is desired, this may cause malfunctions such as sudden inability to obtain fuel injection.

[0016]

[Means for Solving the Problems] A processing device according to the present invention includes a central processing unit, an interrupt request generation circuit that asynchronously issues a processing request to the central processing unit, and a peripheral circuit,
The peripheral circuit includes an edge detection circuit for an external clock input signal, an event counter that counts based on the clock detected by the edge detection circuit, and a first compare register that performs a comparison with a counter value of the event counter. and a free-running counter counted by an internal clock, and a second comparer that compares the counter value of the free-running counter.
a first flip-flop circuit set by a match signal from the first compare register and reset by a write signal to the second compare register; and a second flip-flop circuit whose reset is controlled by the match signal from the output of the first flip-flop circuit and the second compare register.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, one embodiment of the present invention will be explained using FIGS. 1, 2, and 3.

FIG. 1 is a block diagram of a pulse generator, and the pulse generator 100 is composed of a CPU 101, an INTC 102, peripheral hardware 103, and a peripheral bus 104.

[0020] Furthermore, the peripheral hardware 103 includes an INT
Output interrupt signal 105 to C102, INTC
102 performs priority determination of these interrupt signals and outputs an interrupt request signal 106 to the CPU 101. Upon receiving the interrupt request signal, the CPU 101 performs predetermined processing according to a program preprogrammed in an internal or external memory.

FIG. 2 shows an FRC 201 that counts an internal count clock φ inside the peripheral hardware 103.
, compare registers A210 to 21n that compare with the count value of FRC201, a capture register 220 that captures the count value of FRC201, an external clock input buffer 221, and an input buffer 221.
an edge detection circuit 222 for an external clock input signal input from the edge detection circuit 222; an event counter 223 for counting the external clock detected by the edge detection circuit 222;
A compare register B224 that compares with the counter value of the event counter 223, and a compare register B2
24 match signal 225, write signal to compare registers A210 to 21n, or CP
F.F. is reset by the reset signal RESET from U101. F226 and F. Inverter (hereinafter referred to as INV) 227 and INV2 whose input is the output of F226
27 and the coincidence signals 230 to 23n (hereinafter referred to as AND) 260 to 26n, and the coincidence signal 2
F.25 and reset by the outputs of AND260-26n. F240-24n and F. F2
Output buffer 250-25n with inputs 40-24n
It consists of The match signal 225 of the compare register B 224 resets the event counter 223 and also serves as a capture trigger signal for the capture register 220 and an interrupt signal to the INTC 102.

The operation will be described with reference to the timing chart of FIG. 3, taking as an example a pulse output of 0 output from the output buffer 250.

First, a predetermined number of external clocks are input and the value becomes the value set in advance in the compare register B224, and when a match occurs with the count value of the compare register B224, a match signal 2 is output from the compare register B224.
25 is output, F. F240 is set to make pulse output 0 a high level "1". At the same time, F.
Match signals 230 to 23n are set by setting F226 to make the output of INV227 low level "0" and fixing the outputs of AND260 to 26n to low level "0".
by F. Prohibits reset of F240-24n.

The match signal 225 also serves as a capture trigger signal for the capture register 220 at that time.
The count value D0 of the RC 201 is taken into the capture register 220, and serves as a clear signal for the event counter 223 and further as an interrupt signal 105 to the INTC 102.

[0025] When the interrupt signal 105 is input, the INTC 102 performs processing to determine the priority order, etc.
An interrupt request signal 106 is output to U101.

The CPU 101 receives an interrupt request signal 107.
When input, interrupt processing is performed according to a preprogrammed program. Here, the value D0 is the sum of the count number W0 of the FRC 201 corresponding to the desired pulse output width T0 to the value D0 of the capture register 220.
Write 0 +W0 to compare register 210,
This process is performed.

Here, since the count clock is φ, T0 = W0 /φ (W0: number of counts, φ:
FRC501 count frequency) holds true.

The write signal to the compare register causes the F. F226 is reset and match signals 230-23
F. by n. Allows reset of F240-24n.

When the FRC201 counts up and reaches the value D0 +W0, the compare register A21
A match signal 230 of 0 is output. The match signal 230 is
F. Reset F240 and set pulse output 0 to low level "0".

Further, when the external clock is input and the event counter continues counting, and a match with the compare register 224 occurs again, the F.F.240 and F.F. F
226 is set, the pulse output 0 becomes high level "1" again, and F.
Prohibits reset of F240-24n.

Thereafter, if the period of the coincidence signal 225 is longer than the external output pulse width T0, that is, in FIG.
, Tb, a pulse output with a high width T0 synchronized with the external clock input can be obtained by repeating the same operation.

Furthermore, when the period of the coincidence signal 225 is shorter than the output pulse width T0, that is, during the period TC in FIG. 9, the coincidence signal 225 causes the F. F240 is set, pulse output 0 becomes high level "1", and F. F226 is set and INV227 is low.
The level becomes “0”. The value of the compare register A210 is updated by the interrupt processing by the match signal 225,
When D2 +W0 is written, F. F226 is reset and INV227 becomes high level "1", and F. Resetting of F240 to F24n is allowed, but before the match signal 230 from the compare register A210 is output, the match signal 225 is reset again.
F. is output again. F226 is set and I
The output of NV227 becomes low level "0", and F. F
Since reset of 240 to 24n is prohibited, F due to match of compare register A210 (D2 +W0)
．． The F240 is not reset, and the pulse output 0 continues to output a high level "1".

Therefore, even if the period of the external clock input becomes shorter and the period of the coincidence signal 225 becomes shorter than the pulse width T0, the pulse outputs 0 to n will not be suddenly reset, which may cause malfunction. There is no.

Next, a second embodiment of the present invention is shown in FIG. In this embodiment, F. F226, INV22
7. Match signal 225 instead of AND260~26n
is set by each compare register 210-21.
F is reset by a write signal to n.
．． F400-40n and F. AND42 of INV410-41n with F400-40n as input, respective logical products of match signals 230-23n and INV410-41n
Consists of 0 to 42n. Note that the same numbers as in FIG. 2 represent similar functions.

In the first embodiment, if any one of the plurality of compare registers A210-21n is updated, F. Although reset of F240 to F24n is permitted, in this embodiment, the corresponding pulse output is not reset unless writing to each compare register is completed. Allows for wide control.

A third embodiment of the present invention is shown in FIG. In this embodiment, compared to the first embodiment, the set register 7
10, AND710~71n, AND inverted signal (hereinafter referred to as NAND) 720~72n, AND260~26
It is configured with ANDs 730 to 73n added instead of n. Similar numbers to those in FIG. 2 represent similar functions.

In this embodiment, a case will be described in which pulse output is performed sequentially as shown in FIG. 6 for a plurality of pulse outputs.

Each bit of the set register 700 corresponds to each pulse output 0-n, and AND710-71n is the AND of each bit of the set register 700 and the match signal 225 of the compare register B224. F2
There are 40 set signals.

Match signal 2 of compare register B224
25 occurs, the set register 700 sets AN
Selected F.D710-71n. F240~24
n is set, and the pulse output corresponding to the set bit of set register 700 is set. At this time, pulse outputs corresponding to unset bits of the set register 700 are not set. Therefore, depending on the set value of the set register 700, AND710~
F.71n via F.71n. By selecting F240 to F24n, it is possible to selectively set any pulse output.

Therefore, if the n-th bit of the set register 700 is set and the contents of the set register 700 are shifted to the right every time the match signal 225 of the compare register B 224 is generated, the sequential output as shown in FIG. Pulse output can be obtained. Here, in FIG. 6, for simplicity, the number of pulse outputs is four, and the set register 7
An example is shown in which 00 is 4 bits.

If the contents of the set register 700 are not shifted, the pulse output corresponding to the set bit of the set register 700 operates in the same manner as in the first embodiment.

The operation when sequential pulse output is performed will be described with reference to the timing chart of FIG. First, the nth bit of the set register 700 is set. When a predetermined number of external clocks are input and the count value of the event counter 223 becomes the value set in advance in the compare register B224 and a match occurs, a match signal 225 is output from the compare register B224, and the output of the AND71n is becomes “1”, and F. F2
4n is set and pulse output n is set to high level “1”
Make it. At the same time, F. Set F226 and NAN
Set the output of D72n to low level “0” and AND73
By fixing the output of F.n to low level "0", even if the match signal 23n is output at this point (FRC=Dn+W0), the output of F.n. F24n is not reset. At this time, the 0th to (n-1) bits of the set register 700 are “0”.
”, the output of NAND 720 to 72 (n-1) becomes “1” and AND 730 to 73 (n-1) is selected, and F.F24 by the coincidence signal 230 to 23 (n-1)
Resetting from 0 to 24 (n-1) is permitted.

The match signal 225 also becomes a capture trigger signal for the capture register 220, and the current F
The count value D0 of the RC 201 is taken into the capture register 220, and becomes an event counter clear signal and further an interrupt signal 105 to the INTC 102.

[0044] When the interrupt signal 105 is input, the INTC 102 performs processing to determine the priority order, etc.
An interrupt request signal 106 is output to U101.

[0045] The CPU 101 receives an interrupt request signal 107.
When input, interrupt processing is performed according to a preprogrammed program. Here, the value D0 is the sum of the count number W0 of the FRC 201 corresponding to the desired pulse output width T0 to the value D0 of the capture register 220.
0 +W0 is written to the compare register 21n that sets the reset timing of the pulse output n corresponding to the set n-th bit of the set register 700,
Thereafter, the set register 700 is shifted to the right.

Here, since the count clock is φ,
T0 = W0 /φ (W0: Number of counts φ: FR
C501 count frequency) holds true.

The write signal to the compare register causes the F. F226 is reset and the output of NAND72n becomes "1", so AND73n is selected and F.226 is reset by the match signal 23n. F24n reset is permitted.

Next, the set register 700 is shifted to the right, but before that, the FRC201 is counted up and reaches the value D0 +W0, and the compare register A21 is
When the coincidence signal 23n of F.n is output, the coincidence signal 23n is passed through AND 73n, F24n is reset and the pulse output n is set to low level "0". If match signal 2
If 3n is not output, the pulse output n continues to output a high level "1".

Next, set register 700 is shifted to the right. At this time, bit n is set to 0, and the set register 700
is in a state where the (n-1)th bit is set. Then, the external clock is input again, and the count value of the event counter 223 and the compare register B2
A match of F.24 occurs and a match signal of 225 is output. F
24 (n-1) is set and the pulse output (n-1) outputs a high level "1", and at the same time, F. F226
is set again. At this time, the nth bit of the set register 700 is “0”, so the NAND 72
n is F. It becomes “1” regardless of F226, AND73n
is selected. Therefore, at this time, the pulse output n is still high.
Compare register A2 is outputting level “1”.
If a match of 1n occurs and a match signal 23n is output, F
．． F24n is reset and the pulse output n becomes low level "0".

Note that the operation for pulse output (n-1) is not particularly illustrated because it is the same as the operation for pulse output n.

Therefore, by repeating these operations, when a match occurs in the compare register B 224 and a match signal 225 is generated, the pulse output corresponding to the set bit of the set register 700 becomes high level "1". If the reset timing of these pulse outputs that are outputting high level "1" is not set, these pulse outputs will be reset, so the generation period of the coincidence signal 225 will be the external output pulse width. T0
If the length is longer than , sequential pulse outputs can be obtained by sequentially performing the same operation as in the first embodiment for a plurality of pulse outputs.

Furthermore, if the generation period of the coincidence signal 225 becomes shorter than the pulse output width T0, the coincidence signal 225
If the seventh bit of the set register 700 is set and the pulse output n is outputting a high level "1" at the time when the F. By setting F226, NAND72n becomes low level "0", and the value of compare register A21n is updated by interrupt processing by match signal 225 again.
Unless F226 is reset, it continues to output high level "1" (Figure 7, operation example 2), and the set register 7
If the 7th bit of 00 is reset to “0”, it is NAN.
AND73 because D72n becomes high level unconditionally.
F.n is selected and the generation of the match signal 225 causes F. F22
Regardless of whether 6 is set, the pulse output will be high for a specified width.
After outputting level “1”, compare register A2
1n match, F. F24n is reset and the pulse output n becomes low level "0". (Figure 7 Operation examples 1 and 2
) In other words, in the case of sequential pulse output, regardless of whether the generation cycle of the match signal 225 is longer or shorter than the pulse output width, the bits in the set register 700 are set to "1" at the time the match signal 225 is output. The pulse output corresponding to the bit that is set will continue to output a high level "1" unless the reset timing of that pulse is set in the compare register every time the match signal 225 is generated, and after the reset timing is set, the pulse output will continue to be output as high level "1". 700
Even if a match signal 225 is generated in a state where the bit of the set register 700 is reset to "0" due to the shift of , it is not affected by this match signal 225 and outputs a high level "1" for a predetermined width, and then Since it is reset to a low level "0", highly accurate sequential pulse control can be performed on a plurality of pulse outputs.

[0053]

[Effects of the Invention] As described above, in the present invention, when the period of the external input clock becomes shorter than the output pulse width, the reset of the pulse output is prohibited by the pulse output set signal, and the compare register is By allowing the pulse output to be reset by performing an update, a sudden change in the pulse output due to a compare register match occurring immediately after the pulse output's set signal but before the value in the compare register is updated can be avoided. Reset can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a pulse generator.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a timing diagram of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a timing diagram showing an example of sequential pulse output.

FIG. 7 is a timing diagram of a third embodiment.

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is a timing diagram of a conventional example.

Claims (2)

[Claims] 1. An information processing device comprising a central processing unit, an interrupt request generation circuit that asynchronously requests processing to the central processing unit, and a peripheral circuit, wherein the peripheral circuit counts external clock input signals. an event counter, a first compare register that compares the counter value of the event counter, a free running counter that is counted by an internal clock, and a second compare register that compares the counter value of the free running counter. a first flip-flop circuit that is set by a match signal from the first compare register and reset by a write signal to the second compare register;・Set by match signal from register,
An information processing device comprising: a second flip-flop circuit whose reset is controlled by the output of the first flip-flop circuit and a match signal from the second compare register. 2. The information processing device according to claim 1, comprising a plurality of said second flip-flop circuits and a selection means for selecting a predetermined flip-flop from said plurality of said second flip-flop circuits. The information processing device is characterized in that the second flip-flop selected by the selection means is set by a match signal from the first compare register with the event counter.