JPH0287821A - Programmable logic array - Google Patents

Abstract

PURPOSE:To operate a device with a one-phase clock signal easy to control and to quickly perform the data processing with multiple inputs by arranging N-channel transistors TRs in parallel for the signal supplied to an AND plane and supplying the one-phase internal clock signal. CONSTITUTION:N-channel TRs are arranged imparallel in an AND plane 3' for the signal sent out from an input register 1. Then, the device is quickly operated with multiple inputs. A clock signal is supplied from the external to internally generate first and second clock signals. With respect to clock signals 1 and 2, the output timing of the clock signal 2 supplied to an OR plane 4 is somewhat delayed behind the clock signal 1 by an AND plane dummy circuit 20. Thus, the OR plane 4 is operated after the output signal of the AND plane 3' is settled, and an erroneous signal is not sent out from the OR plane 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous programmable logic array that operates using an l-phase clock signal and operates at high speed with multiple human power.

"Prior Art" A synchronous PLA is a programmable logic array (hereinafter abbreviated as PLA) used in microprocessors and various controllers, and is used in synchronization with an internal clock signal generated within a device equipped with this PLA. , 5th
As shown in the figure, an input register 2 stores supplied data, a clock driver 2 generates a clock signal,
It includes an AND plane 3, an OR plane 4, and an output register 5 for storing output data.

The data supplied to the manual register l is transferred from the input register l to A by the clock signal sent by the clock driver 2.
It is sent to the ND plane 3. The AND plane 3 performs a logical operation on the data supplied in synchronization with the clock signal sent out by the clock driver 2, and sends the operation result to the OR plane 4. The OR plane 4 performs calculations in synchronization with the clock signal and sends the calculation results to the output register 5, and the output register 5 stores the supplied data.
When a clock signal is supplied from the clock driver 2, the stored data is sent to the outside of the PLA. Although not shown in FIG. 5, the data sent from the output register 5 may be fed back to the input register 1. still,
The input register 1 and the output register 5 are composed of transverse latch circuits or flip-flop circuits, and the performance of the PLA is the same as that of the AND plane 3 and the OR plane 4.
depends on the configuration of

Figures 6 to 8 show the conventional AND plane 3 and OR.
Various configurations of plane 4 are shown. In Figure 6, AN
The D-plane 3 includes a P-channel transistor 7 whose source is connected to a power supply 6 and whose gate is supplied with a clock signal (referred to as GK in the park) sent out from a clock driver 2, and a plurality of transistors sent out from an input register l. Input data IN.

The transistor 8 is composed of an N-channel transistor 8 to which the clock signal is supplied to each gate, and an N-channel transistor 9 to which the clock signal is supplied to the gate. are connected in series, and the drain of transistor 9 is grounded.

OR plane 3 has a source connected to N110 and
It has a configuration in which a plurality of P-channel transistors 11 are connected in parallel, in which the drain of the transistor 7 provided in the plane 3 is connected to the gate, and the drain of each transistor 11 is connected to the gate of which the inverted signal of the clock signal is connected. It is connected to the source of an N-channel transistor +2 whose drain is grounded, and also to the input terminal of the output register 5.

The AND plane 3 and OR plane 4 configured in this manner use an l-phase clock signal and operate divided into a precharge period and a manual evaluation period. That is, during the precharge period when an L-level clock signal is supplied, transistor 7 is on, and transistors 9 and 1! Since is in the off state, the AND plane 3 is precharged to H level by the power supply 6. On the other hand, OR
Since the output of the plane 4 is supplied with an inverted clock signal to the transistor 12, the transistor 12 is in an on state and is therefore precharged to an L level.

Next, during the manual evaluation period during which a 4-level clock signal is supplied, transistors 7 and 12 are turned off and transistor 9 is turned on, so the input data IN1 to INn supplied to the AND plane 3 are evaluated first. , an H or L level signal is sent to the output side of the AND plane 3, that is, to the gate of the transistor 11. Then, the transistor 11 is connected to the output signal of the AND plane 3.
turns on and off, and the OR plane 4 sends out a signal of 4 or L level.

Since FIG. 7 is configured to shorten the delay time of the OR plane 4 shown in FIG. 6, the same components as in FIG. 6 are given the same reference numerals.

The OR plane 4 shown in FIG. 7 is composed of a plurality of P-channel transistors connected in parallel, which are included in the OR plane 4 shown in FIG. Instead of 1, a plurality of N-channel transistors 13 are connected in parallel, and the gate of transistor 13 is connected to the drain of transistor 7, which is connected to inverter 14.
The drain of each transistor 13 is grounded. Further, the power supply 15 is connected to the sources of each of the transistors 13 via a P-channel transistor 16 whose gate is supplied with a clock signal. Further, the source side potential of the transistor 13 is sent to the output register 5 via the inverter 17.

The circuits shown in FIGS. 6 and 7 described above are applicable to any AN
In the D-plane 3 as well, since the N-channel transistor 8 is connected in series with the signal supplied from the input resistor l, the signal processing speed will drop significantly due to the back gate effect of the MOS FET when the number of human resources increases. The drawback was that the delay time was long. The AND plane 3 and OR plane 4 shown in FIG.
N-channel transistor + for the signal sent by
8 are connected in parallel. In FIG. 8, the same components as those shown in FIGS. 6 and 7 are designated by the same reference numerals. Further, two-phase clock signals of clock signal 1 and clock signal 2 are supplied to this AND plane 3.

In FIG. 8, the gate of the transistor 18 connected in parallel is supplied with an inverted signal of the signal sent out by the input register I, and the source of the transistor 18 is supplied with the clock signal 1 (
The inside of the cell is connected to the power supply 6 through a transistor 7 whose gate is supplied with an inverted signal of the clock signal l (referred to as CKI), and the drain of the transistor 18 is connected to the power supply 6 through a transistor 9 whose gate is supplied with an inverted signal of the clock signal l. Grounded.

In the OR plane 4, the gate of the transistor i3 connected in parallel is connected to the drain of the transistor 7, and the source of each transistor 13 is connected to the power supply 15 through the transistor 16 whose gate is supplied with the clock signal 2.
, and the drain of each transistor i3 is grounded via a transistor 19 whose gate is supplied with the clock signal 2. Further, the source side potential of the transistor 13 is supplied to the output register 5 via the inverter 17.

The AND plane 3 and OR plane 4 configured in this way are basically the AND plane 3 and OR plane 4 shown in FIG.
It operates in the same way as the R plane 4, but for the signal sent by the human resistor l and the signal supplied to the OR plane 4, the N channel transistors 18 and ! By connecting 3 in parallel, the signal processing speed is increased.

[Problems to be Solved by the Invention] In the conventional AND plane 3 and OR plane 4 shown in FIG. 8, when the AND plane 3 side is precharged, that is, when the transistor 7 is turned on, the OR plane 4 There is a drawback that the gate potential of the transistor 13 provided becomes H level. It is not possible to evaluate the input of OR plane 4 until the value of the output of AND plane 3 is completely determined.
If the input of the OR plane 4 is evaluated before the value of the output of the OR plane 4 is completely determined, the OR plane 4 will send out an incorrect signal. Therefore, the circuit shown in FIG. 8 requires clock signal overlap and two-phase clock signals having a skew longer than the evaluation time of the AND plane 3. These two clock signals, for example! Although the four-level signals may have an overlapping time, the clock signal 17! The time from when l<L level until the clock signal 2 becomes I-level needs to be at least longer than the manual evaluation time of the AND plane 3. Furthermore, when integrating a PLA on a silicon substrate, it is difficult to use a two-phase lock signal having a skew, and it is necessary to take into account allowances for temperature changes in the clock signal.

As described above, there is a problem in that it is difficult to use two-phase clock signals in terms of clock signal control.

The present invention has been made to solve the above-mentioned problems, and operates with an L-phase lock signal that is easy to control.1. The purpose of the present invention is to provide a PLA that has multiple inputs and can process data at high speed.

[Means for Solving the Problems J] The present invention comprises an AND plane that includes N-channel transistors connected in parallel and a human input signal is supplied to the gates of the transistors, and an N-channel transistor connected in parallel. and an OR plane to which an output signal of the AND plane is supplied to the gate of the transistor, the program logic array uses an internal clock signal, and is supplied with a circuit configuration similar to that of the AND plane. a dummy circuit that sends out a signal delayed from a first clock signal; and a dummy circuit that generates the first clock signal in synchronization with the supplied one-phase internal clock signal and is supplied with the signal that the dummy circuit sends out. and a clock signal generator that generates a second clock signal delayed from the first clock signal and sends the second clock signal to the OR plane.

[Operation] The clock generator generates a first clock signal based on the supplied l-phase internal clock signal, and sends the first clock signal to the AND plane and the dummy circuit. The operation starts with a clock signal of 1. By being supplied with the first clock signal, the dummy circuit sends out a signal delayed from the first clock signal to the clock generator.

By being supplied with a signal from the dummy circuit, the clock generator sends out a second clock signal delayed from the first clock signal to the OR plane, and the OR plane starts operating with the second clock signal.

[Embodiment] In FIG. 1 showing an embodiment of the present invention, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In FIG. 1, clock driver 2° is manually operated by register 1. AND plane 3°, output register 5 and AND
These components 1.3 are connected to an AND plane dummy circuit 20 to guarantee the evaluation time of plane 3°.
', 5.20, the clock signal l is sent from the clock driver 2°.

AND plane dummy circuit 20 is AND plane 3°
This circuit has a configuration similar to that of , and sends a signal corresponding to a time equal to or slightly longer than the evaluation time of the AND plane 3° to the clock driver 2. The clock driver 2° is also connected to the OR plane 4 and sends the clock signal 2 to the OR plane 4.

Furthermore, the AND plane 3' and the OR plane 4 are circuits configured as shown in FIG.
A clock signal where the signal fed to the gate of is not inverted! Other than that, it has the same circuit configuration as the AND plane 3 and the OR plane 4 shown in FIG. In FIG. 2, the same components as in FIG. 8 are designated by the same reference numerals.

In addition, in the clock driver 2' shown in FIG.
The clock signal supplied from outside A is buffered 2°a.
The output side of the buffer 2°a is connected to the input side of the NAND gate 2b. As shown in FIG. 3, the AND plane dummy circuit 20 has a circuit configuration in the case where there is one transistor 18 in the 3° portion of the AND plane shown in FIG.
The drain side of the transistor 20a is connected to an inverter 20e.
is connected to the input side of the NAND gate 2b provided in the clock driver 2°. Further, a capacitor 20d having a load capacitance C and having one end grounded is connected to the input side of the inverter 20e. The load capacitance C adds the maximum amount of the input capacitance of the transistor 13 provided in the OR plane 4 section, but as the number of transistors increases, the load capacitance C can be changed accordingly. NAND gate 2
°b sends the clock signal 2 to the output register 5 via the inverter 2°e.

In the PLA of the present invention configured in this manner, the AND plane 3° is precharged to H level by the power supply 6, and then receives, for example, an H level clock signal from the clock driver 2°, as explained in the conventional example. l is supplied,
The data sent out by the human register 1 is evaluated. That is, one of the input data IN1 to INn is L.
If the level is high, one of the transistors 18 is in the on state, so if the clock signal l at the H level is supplied, the transistor 9 is in the on state and becomes grounded.
Output side 1 of D plane 3° becomes L level. Also, if all of the human data IN or INn is at H level, it is AN.
The output of the D plane 3° (the rule remains at the precharged H level).

On the other hand, the transistor 2 of the AND plane dummy circuit 20
Since the clock signal l at the T level is also supplied to 0a and 20c, the transistor 20a is turned off and the transistor 20c is turned on and grounded, so that the potential on the drain side of the transistor 20a becomes L level. However, in order for the potential to reach the L level, the capacitor 2
This is after the load capacitance stored at 0d is discharged. Therefore, the AND plane dummy circuit 20 sends an H level signal to the NAND circuit 2'b provided at the clock drain 2° via the inverter 20e a while after the clock signal I changes to the H level.

Therefore, the NAND circuit 2°b performs a logical operation on the H level signal supplied from the buffer 2°a and the H level signal supplied from the AND plane dummy circuit 20, and sends the L level signal to the inverter 2°e. The clock signal 2 at H level is sent to the OR plane 4 from the inverter 2°e. Therefore, as shown in FIG. 4, the clock signal 2 changes to the H level after a while after the clock signal 1 changes to the H level.

In this way, when the clock signal 2 changes to the MH level, the potential on the output side of the AND plane 3' is determined to be H or L level, and when the clock signal 2 changes to the H level, the potential of the OR plane 4 is transistor 1
9 is turned on, and the signal possessed by the OR plane 4 is sent out via the inverter 17.

That is, if the output side of the AND plane 3' is at L level, all of the transistors 13 included in the OR plane 4 are in the off state. The charged H level signal is inverted to L level by inverter 17 and this L level signal is sent to output register 5.

Also, if the output side of AND plane 3° is at H level,
The transistor 13 is in the on state, the input side potential of the inverter 17 provided in the OR plane 4 changes to L level, and the OR plane 4 sends a signal at H level to the output register 5.

As described above, the PLA of the present invention operates at high speed with multiple inputs because the AND plane has N-channel transistors arranged in parallel with respect to the signal sent from the input register 1. Furthermore, the clock signal externally supplied to the PLA may be l-phase, and the first and second clock signals are generated inside the PLA. And the clock signal! In and 2, the output timing of the clock signal 2 supplied to the OR plane is somewhat delayed from the clock signal 1 in the AND plane dummy circuit, so the OR plane operates after the output signal of the AND plane is determined, No false signals are sent out from the OR plane.

Furthermore, since the AND plane dummy circuit has the same circuit configuration as the AND plane, if the data evaluation time of the AND plane changes due to changes in process or temperature, the clock signal 2 will also be sent out later than the AND plane dummy circuit. Therefore, the PLA of the present invention operates stably against various fluctuations.

[Effects of the Invention] As detailed above, according to the present invention, by arranging N-channel transistors in parallel for the signals supplied to the AND plane, the present programmable Ronok array can be realized with multiple inputs and at high speed. works. Furthermore, by being supplied with the l-phase internal clock signal, the clock generator sends out the first clock signal to the AND plane, and the clock generator sends the first clock signal to the AND plane.
OR the second clock signal delayed from the clock signal of
After the AND plane starts operating with the first clock signal, the OR plane starts operating with the first clock signal.
The operation can be started by a clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the configuration of a PLA according to the present invention, and FIG.
3 is a circuit diagram of the clock driver and AND plane dummy circuit shown in FIG. 1, FIG. 4 is a time chart of clock signals 1 and 2, and FIG. 5 is a circuit diagram of the conventional PLA. Block diagram showing the configuration, Figure 6 is the 5th
7 is a circuit diagram showing a first conventional example of the AND plane and OR plane shown in FIG. 5, FIG. 8 is a circuit diagram showing a second conventional example of the AND plane and OR plane shown in FIG. The third AND plane and OR plane shown in the figure
FIG. 2 is a circuit diagram showing a conventional example. 1... Input register, 2'... Clock driver, 3'... AND plane, 4... OR plane, 5... Output register, 13... Transistor, 18... Transistor, 20...AND plane dummy circuit. Patent applicant: Ricoh Co., Ltd. - Patent attorney: Hajime Aoyama and 1 other person Figure 3: Figure 114

Claims (1)

[Claims] (1) An AND plane comprising N-channel transistors connected in parallel and an input signal being supplied to the gate of the transistor; and an AND plane comprising N-channel transistors connected in parallel and having the gate of the transistor supplied with an input signal. A program logic array that uses an internal clock signal and has an OR plane supplied with an output signal of
a dummy circuit that sends out a signal delayed from the clock signal of the dummy circuit; a dummy circuit that generates a first clock signal in synchronization with the supplied one-phase internal clock signal; A programmable logic array comprising: a clock signal generator that generates a second clock signal delayed from a first clock signal and sends the second clock signal to an OR plane.