JPS61151771A - Non-synchronizing signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the time from the sampling of the external signal to the determination of the internal signal without fastening a clock frequency and to prevent the output of a middle value when a non-synchronizing signal is synchronized by providing plural latch circuits. CONSTITUTION:FF102-105 constitutes the first - the fourth latch circuits to transfer input data D to an output terminal Q when a control signal input C is asserted, and to hold and output an output signal Q when the input is negated. An input signal 110 inputted from an input signal 101 is latched to an FF102 by a timing clock phi1, and the output signal 120 is latched again to FF103 by a clock phi2 dislocated to 90 deg. from the clock phi1. Thus, a non- synchronizing signal is sampled by a tailing edge of the clock phi1 through FF102-FF105, and the effective value can be outputted from the tailing edge of the clock phi2. Thus, the non-synchronizing signal can be synchronized at a high speed and at the time of synchronization, the middle value can not be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a circuit system for synchronizing input signals that change without synchronization with a clock.

[Background of the invention]

In recent years, the operating speed of logic LSIs such as microprocessors has improved, and now some that operate at a clock frequency of 10-odd MHz or several tens of MHz have appeared, and the signal delay time inside the LSi has been shortened to around 1 ms. On the other hand, L.S.
Although the implementation technology has improved, the external signal delay time is on the order of several Ions. Therefore, it has become difficult to synchronously transmit and receive signals to and from the outside of the LSi in the internal circuit of the LSi. Therefore, input signals from outside the LSi must be treated as asynchronous signals,
An asynchronous signal synchronization circuit is required as a signal input circuit of the LSi.

Generally, sampling of an asynchronous signal is performed using a clock φ and 1
This can be done using a two-stage shift register controlled by an inverted signal φ□ with a phase shift of 80 degrees. However, the output of the second stage flip-flop is unstable at the leading edge of the clock ex. Therefore, this signal is
By relatching with a later clock, a fully valid signal can be created for the duration of the machine cycle.

Conventionally, φ1 with a phase shift of 18° has been used as a clock delayed from T1. An example of this is shown, for example, in FIG. 11 of US Pat. No. 4,349,873.

The circuit shown in FIG. 11 is shown in FIG.

This circuit has three sets of latch circuits 1, 2, and 3 connected in series, and the latch circuits 1 and 3 are controlled by a clock signal φ1, and the latch circuit 2 is controlled by a clock signal T1.

The clock signals φ1 and ¥ are signals having an inverse relationship to each other. Therefore, it takes half a clock cycle from sampling the external signal to obtaining the synchronization signal from the latch circuit 3.

[Purpose of the invention]

A first object of the present invention is to provide a high-speed asynchronous signal synchronization circuit that shortens the time from sampling an external signal to determining an internal signal without increasing the clock frequency.

A second object of the present invention is to provide an asynchronous signal synchronization circuit configured so as to avoid outputting an intermediate value (a value that is not determined to be High or Low) when synchronizing an asynchronous signal.

[Summary of the invention]

In the present invention, in order to achieve the above first object, the clock 4
A new lock φ with a phase shift of less than 180° from φ1,
a first latch circuit that latches an asynchronous input signal using a clock φ1, a second latch circuit that latches an output signal of the first latch circuit using a clock φ2, and an output signal of the second latch circuit. A third latch circuit that latches an output signal of the third latch circuit using an inverted signal of the clock φ1, and a fourth latch circuit that latches the output signal of the third latch circuit using an inverted signal of the clock φ2. This allows the synchronization signal to be taken out quickly without increasing the clock frequency.

In addition, in order to achieve the second objective, the present invention adds a latch controlled by clock φ2 between the clock φ1 and the latch of φ1, and clocks φ1 and φ1 are connected until the internal signal is determined by clock 7 A feedback loop was constructed with two latches of φ2 to prevent intermediate values from being latched.

In other words, the intermediate value that may be held in each feedback loop is a unique value depending on the logic threshold of the gates that make up the loop, and when a signal that deviates from this value is input, the output signal will be Must be logical “O” or “1”
Therefore, by setting the intermediate values that may be held in each feedback loop to different values, it is possible to prevent the intermediate value of the asynchronous signal from being latched.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an asynchronous signal synchronization circuit to which the present invention is applied. Flip-flops 102 to 105 are latch circuits that transmit input data D to output terminal Q when control signal C is asserted, and hold and output output signal Q when it is negated. The operation of the asynchronous signal synchronization circuit will be explained using the time chart shown in FIG. An input signal 110 input from an input terminal 101 of the LSI chip is latched by a flip-flop 102 by a timing clock φ□, and a signal 120 is output. The clock φ1 of the flip-flop 102 is High.
Since the input signal 110 is passed through during h, the output value 120 during this period varies depending on the input signal 110 and is undefined.

The signal 120 is latched again by the flip-flop 103 by the timing clock φ2, which is 90″ out of phase with the clock φ, and outputs the signal 130.
The output signal 140 latched by the inverted signal of the clock φ1 becomes a signal holding the dark value of one cycle of the clock φ□ as shown in the time chart. However, signal 140 is unstable at the chaining edge of clock φ. In other words, because there is a gate delay due to the flip-flops 103 and 104 in the second and third stages, even if the signal 120 is determined at the tailing edge of the clock φ□, it takes time for the signal 140 to be determined. It is.

Therefore, when the signal 140 is latched again with the inverted signal of the clock φ2, the output signal 150 holds the dark value of one cycle of the clock φ2, as shown in the time chart.
Moreover, a valid value can be output from the tailing edge of clock φ2.

FIG. 4 shows an example of the configuration of flip-flops 102 to 105. Logic gate 200 outputs an inverted signal of the input signal when control signal C is asserted, and outputs a high impedance state when negated. Also, logic gate 2
Conversely, when the control signal C is negated, the circuit 10 outputs an inverted signal of the output signal Q of the flip-flop, and when the control signal C is asserted, the output becomes a high impedance state. When the two types of logic gates 200 and 210 and the inverter 220 are connected as shown in FIG. 4, a flip-flop that latches input data D in response to a control signal C can be constructed.

As described above, in this embodiment, an asynchronous signal can be sampled at the tailing edge of clock φ1, and an internal signal can be enabled at the tailing edge of clock φ2. In other words, asynchronous signals can be synchronized in 174 clock cycles. here,
Clock φ1 with a 90° phase shift. φ2 can be easily generated by dividing a parent clock having twice the frequency by two.

Therefore, it is suitable for use as a synchronization input of a response signal, an interrupt request signal, etc. of an asynchronous transfer bus.

Next, a configuration for preventing the asynchronous synchronization circuit from outputting intermediate values will be described.

5th r! ! An example of a more detailed circuit configuration of a flip-flop is shown in FIG. Circuit elements 301, 302°311.3
12, 321 are P-channel MO3FETs, and 1-circuit elements 303, 304, 313, 314.degree. 322 are N-channel MO5FETs. MOSFET is 301°302
．． 303 and 304 constitute the logic gate 200 in FIG. 4, and MOSFETs 311.312°313.31
4 similarly constitutes a logic gate 210. Also, M
OSFETs 321 and 322 constitute an inverter 220. The operation of the flip-flop will be explained using FIG. First, when the control signal C is asserted (High), the circuit elements 302 and 303 are turned on, and the logic gate 200 functions like an inverter and outputs an inverted signal of the input signal. On the other hand, the logic gate 210 is the circuit element 3
Since 12°313 is in the OFF state, the output is high impedance. Therefore, the signal g330 becomes an inverted signal of the input signal, is inverted again by the inverter 220, and transmits the input signal to the output terminal Q.

Next, when the control signal C is negated (low), the circuit elements 302 and 303 are turned off, and the output becomes high impedance. On the other hand, the logic gate 210 is connected to the circuit element 312.
, 313 is turned on and works in the same way as an inverter.
Outputs an inverted signal of output signal Q. Therefore signal line 3
30 is an inverted signal of the output signal Q, and the inverter 220
is inverted again, output signal Q is output, and the value is held.

In this flip-flop, P of logic gate 210
When the gate width of MO5FET 311 is made larger than usual, the logic threshold of logic gate 210 becomes higher.

Therefore, control signal C is negated and logic gate 2
10 and an inverter 220, the logic gate 2
The value of the output signal Q, which is the input of 10, is PMO5FET
It is stable at a value higher than when the gate width of 311 is normal.

That is, when a higher than normal value is applied to the input signal while control signal C is asserted, this flip-flop will latch the intermediate value and its output signal Q will be a higher than normal value. . Conversely, the N of logic gate 210
Increasing the gate width of 05FET 314 lowers the logic threshold of logic gate 210. Therefore, when the intermediate value is latched into the feedback loop, the value of the output signal Q will be a low value. That is, when a value lower than normal is input while control signal C is asserted, this flip-flop latches the intermediate amount, and its output signal Q becomes a value lower than normal.

Further, when a value other than the intermediate value is latched in the flip-flop, the output signal Q is made to fully swing to High or Low by a feedback loop constituted by the logic gate 210 and the inverter 220.

In the asynchronous signal synchronization circuit shown in FIG.
As the first stage latch 102 that latches 0, PMO3
A flip-flop in which the gate width of FET 311 is increased is used as the second stage latch 103 that latches the output signal 120 of NMO3FII! If a flip-flop in which the gate width of T314 is increased is used, the intermediate value can always be oscillated to High or Low. In other words, even if the first stage latch 102 latches an intermediate value, the output signal 120 at that time will be a higher value than the intermediate value generated by a normal flip-flop, and only when a low value is input. There is a possibility that an intermediate value is latched, and in other cases, the output signal can be completely determined to be High by the second stage flip-flop 103 that determines the output signal. On the other hand, the intermediate value is latched in the second stage latch 103 when a lower intermediate value is input as the input signal 120, but the first stage flip-flop outputting the signal 120 In 102, the intermediate value is a high value, and in the case of other values, it is completely determined to be High or Low by the feedback loop, so that a low intermediate value is not output as the signal 120.

Therefore, each flip-flop is configured so that the value output when the first-stage flip-flop 102 latches the intermediate value is different from the input value when the second-stage flip-flop 103 latches the intermediate value. By controlling the logic threshold of the gate, when the first and second stage flip-flops 102, 103 enter the feedback state, their output signal 130 becomes completely High or Low.
The value of ow can be determined. Output signal 1 in Figure 2
50 is the signal 140 when the clock φ2 is negated.
is transmitted to the output. In other words, the first and second stage latches 1
Since the output signal 150 is output after 02 and 103 enter the feedback state, the output signal 150 is completely high.
In the above description, the N of logic gate 210 is used to control the intermediate values that the flip-flop may latch.
Although the size of the 05FET was changed, the size of the MOSFET of the logic gate 200 and the inverter 220 may also be changed.

〔Effect of the invention〕

According to the present invention, it is possible to shorten the time from sampling an asynchronous signal to determining a synchronized signal without increasing the frequency of the internal clock for sampling.

In addition, by making the first stage latch and the second stage latch feedback type, and by controlling certain intermediate values to different levels, it is possible to completely set the asynchronous signal to a high level as a synchronization signal. Alternatively, there is an effect that a signal determined to be Low can be extracted.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example, and FIG. 2 is a block diagram of an asynchronous signal synchronization circuit that is an embodiment of the present invention. Fig. 3 is an operation time chart of the asynchronous signal synchronization circuit shown in Fig. 2, Fig. 4 is a logic diagram of a flip-flop used in the circuit shown in Fig. 2, and Fig. 5 is a detailed circuit diagram of the flip-flop shown in Fig. 4. . 101... Input terminal, 110... Asynchronous input signal,
150... Synchronized output signal, 200, 210... Clocked inverter, 220... Inverter, 301
゜302.311,312,321...P channel M
O3FET, '303. 304. 313. 314
．． 322...N channel MO5FET. Kaya 4 Figure 5

Claims (1)

[Claims] 1. A first latch circuit that stores an asynchronous signal using a first clock; a second latch circuit that stores an output signal of the first latch circuit using a second clock; a third latch circuit that stores the output signal of the second latch circuit using an inverted clock of the first clock; and a fourth latch circuit that stores the output signal of the third latch circuit using an inverted clock of the second clock. a latch circuit, wherein the second clock is a clock having a timing between the first clock and an inverted clock of the first clock. 2. In the asynchronous signal synchronization circuit of item 1, the first latch circuit and the second latch circuit are latch circuits that internally feed back and hold the output signal when the control signal is negated. , such that the value of the output signal when the first latch circuit latches the intermediate value is different from the value of the input signal when the second latch circuit latches the intermediate value. This is an asynchronous signal synchronization circuit in which the logic thresholds of the logic gates constituting the second latch circuit are shifted.