JPH04206852A - Layout method for cmos integrated circuit - Google Patents

Abstract

PURPOSE:To enable the circuit element such as transistor, etc., to be arranged on the whole semiconductor substrate thereby increasing the integration degree by a method wherein the power supply lines and the signal lines are allotted to respective wiring layers of a CMOS integrated circuit. CONSTITUTION:Within a CMOS integrated circuit, Vss lines 24 and Vcc lines 25b (25a) are provided respectively on the first layer and the second layer to eliminate the wiring regions so that the circuit elements such as transistors, etc., may be arranged on the whole semiconductor substrate thereby enabling the integration degree to be increased Furthermore, the gaps between signal lines can be widened; the wiring length of the signal lines and the power supply lines can be shortened; and the wiring width of the power supply lines can be widened so that the problems such as the mutual interference between the signal lines, the timing skew between signals, the drop in power supply voltage, the floating of reference voltage, etc., may be settled.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a layout method for CMOS integrated circuits, in particular a power supply that enables circuit elements to be arranged over the entire semiconductor substrate without providing a wiring area. This invention relates to a layout method for lines and signal lines.

Conventional technology Until now, very large-scale semiconductor integrated circuits such as 64-bit MPU and 6 Mbit DRAM (by integrating as many elements as possible within a limited chip area) Conventionally, this goal of increasing the degree of integration has been achieved primarily by reducing the design rules used during layout design, and the current state of the art is that little improvement has been made to the layerer I/method.

FIG. 5 shows the top surface of a CMOS integrated circuit having two metal wiring layers laid out according to the conventional layout design process. FIG. 6 shows a cross-sectional view taken along line AB in FIG.

11 (translation) In the PMOS-FET area, from the front to the back, the source/drain region 11a, the polysilicon chip 1
□ ] ] 2MO8- consisting of b and N well llc
A group of FETs are arranged. 12 is NMO8-
In the FET region, an NMO8-FET group consisting of a source/drain region 1.2a, polysilicon chips 1-12b, and a P well 12c is arranged from the front of the transistor toward the back. Combine 11 and 12 to make M OS -, -F
ET area 13. Also, 15 is a silicon substrate,
16 is a dividing region; 17 is an interlayer insulating film between the element and the first layer metal. 21 is a power supply line (vC
C line), 22 is a power supply line for base thread voltage Vss (, Vs
(s-line), and each wire is wired from the front to the back using the same wiring layer, the first metal wiring layer.

Further, 26 is an interlayer insulating film between the first layer metal and the second layer metal.

Reference numeral 31 denotes a signal line used for signal transmission between adjacent FETs in the MOS-F E 'I'' region 13, which is connected from the front to the back or from the right using the first metal wiring layer within the region. The wiring is towards the left. 32 is M O
A signal line used for signal transmission between the S-FET region 13 and the outside;
3 and wiring area 14, wiring is performed from right to left using the second metal wiring layer.

33 is an isolated FE in the MOS-FET area 13
between T or the MO8-FET region 13 and other MO
A signal line used for signal transmission between the S-FET regions, and is wired from the front to the back using the first metal wiring layer in the wiring region 14, and is connected to the signal line 32.
connected to.

As described above, in a CMOS integrated circuit drawn by the conventional layout method (the MOS-FET area 1
3 and the wiring area 14, it is possible to create a layout with a high degree of freedom in the arrangement of elements, the routing of signal lines, and the connections between elements and signal lines and between signal lines and signal lines within each area. There are many advantages such as short layout period.

Problems to be Solved by the Invention However, with the above-described layout method, it was necessary to provide a wiring area for the signal lines (because the power supply lines (Vcc line and Vss line) were provided in the same wiring layer). Next generation device 64Mbit DRA, M
As the number of elements and signal lines increases as the integrated circuits become even larger, as typified by It has become extremely difficult to maintain. This has also caused various problems.

For example, timing deviation (skew) between signals due to an increase in signal line length due to an increase in chip area.
In order to prevent the chip area from increasing unnecessarily due to external factors such as packaging, it is not possible to secure a sufficient wiring width for the power supply line. A drop in power supply voltage or base (
ll (voltage fluctuation, etc.) Mutual interference between signal lines due to the narrowing of the spacing between signal lines due to reduction in design rules during layout design. This will be negative for integration.

In view of this point, the present invention provides a CMO that can lower the functions of MO3 integrated circuits and achieve higher integration.
The present invention aims to provide a layout method for S integrated circuits.

Means for Solving the Problems A layout method for a CMOS integrated circuit according to the present invention (for each metal wiring layer of a CMOS integrated circuit having two metal wiring layers, a power supply line with a power supply voltage Vcc is connected to one wiring layer) (VCC line) and first signal line tray The power supply line (Vss line) of the reference voltage Vss and the second signal line group are allocated to the other wiring layer, and a wiring area is not provided.

Further, in the above method, the present invention provides that one of the first and second signal line groups allocated to each metal wiring layer is a signal line between each circuit block of a CMOS integrated circuit. The other signal line group may be a group of signal lines (local signal lines) between circuit elements in each circuit block of the CMOS integrated circuit and a group of i-word lines within the circuit elements; Among the signal lines allocated to each metal wiring layer, there is a method in which the wiring layer of a group of signal lines in a circuit element is made into a polycide wiring layer, and finally, a PMOS-FET area and an NMOS-FET area are formed on the entire semiconductor substrate. (Among the power supply lines allocated to each metal wiring layer, connect the Vcc line above the PMOS-FET area.
, Vss lines are placed in the NMOS-FET region, and the signal line groups assigned to each metal wiring layer are wired to the lower layer and the -1- layer of each power supply line.

Operation The present invention allocates power supply lines and signal lines to each metal wiring layer of a CMOS integrated circuit by the method described above,
By not providing a wiring region, it is possible to arrange circuit elements such as transistors over the entire semiconductor substrate, thereby increasing the degree of integration.

Also, for the signal lines allocated to each metal wiring layer, one is used as a group of signal lines between each circuit block (global signal lines), and the other is used as a group of signal lines between circuit elements within each circuit block (local signal lines). By forming a group of signal lines in a circuit element and a group of signal lines within a circuit element, a layout with a high degree of freedom such as routing of signal lines and connection of elements and signal lines, and (i return line and signal line) becomes possible.Furthermore, as mentioned above, By using a polycide wiring layer as the wiring layer for a group of signal lines in a circuit element, a more flexible layout becomes possible.In addition, a PMOS-FET area and an NMOS-FET area are provided on the entire semiconductor substrate. Among the power supply lines allocated to the metal wiring layer, the Vcc line is placed above the PMOS-FET area.
The power supply line is strengthened by placing the ss line on the NMOIFET area, and the signal line group allocated to each metal wiring layer is wired in the lower and upper layers of each power supply line to increase the durability of the signal line. Noise resistance can be improved.

Example (Example 1) Embodiments of the present invention will be described using the drawings.

FIG. 1 shows the top surface of a CMOS integrated circuit having two metal wiring layers laid out by the layout method according to the first embodiment of the present invention. FIG. 2 shows a cross-sectional view taken along line AB in FIG. 1. be.

11 (M) P made of PMOS-FET similar to Fig. 5
This is a MOS-FET area, and PMOS-FET groups are arranged from the front to the back.

12 (N
MO8-FET area, N from front to back
A group of MOS-FETs is arranged. 11 and 1
2 are combined to form a MOS-PET region 13. Also 15
16 is a silicon-based insulating layer 17 is an interlayer insulating film 26 between the element and the first layer metal, and is an interlayer insulating film between the first layer metal and the second layer metal.

25 is a power supply line (Vcc line) of the power supply voltage Vcc, which connects the Vcc line 25a provided in the first layer metal and the second
It is composed of a Vcc line 25b provided in a metal layer.

The Vcc line 25b is wired from the front to the back using the second metal wiring layer, and connection to the FET is made via the first metal wiring layer (Vcc line 25a). In order to reduce the aspect ratio of the contact hole between the FET and the Vcc line, the Vcc line 25a is provided (it is not necessarily necessary to provide the Vcc line 25a, and only the Vcc line 25b provided in the second layer metal may be used).

Reference numeral 24 denotes a power supply line (Vss line) for the reference voltage Vss, which is wired from the front to the back using the first metal wiring layer.

34 is a group of signal lines (local signal lines) between circuit elements in each circuit block of a CMOS integrated circuit and a group of signal lines within the circuit elements. The wiring is from to the left.

35 is a signal line between each circuit block of the CMOS integrated circuit (
FET
Connection with the Vcc line is made in the same way as the Vcc line.

As described above, according to this embodiment, in the t CMOS integrated circuit, the Vss line 24 is placed in the first layer, and the VCC line 24 is placed in the second layer.
By providing the line 25b, the wiring area is not required.
It is possible to arrange circuit elements such as transistors over the entire semiconductor substrate, thereby increasing the degree of integration. In addition, the spacing between signal lines can be widened, the wiring length of signal lines and power supply lines can be shortened, and the wiring width of power supply lines can be increased, thereby reducing mutual interference between signal lines and timing deviation between signals. (skew) problems, power supply voltage drops, reference voltage fluctuations, and other problems can be solved.

In this embodiment, the Vss line 24 is provided in the first layer, and the Vcc line 25b is provided in the second layer.
5b, the Vss line 24 may be provided in the second layer. Also,
Local signal line group and signal line group 3 in circuit elements on the first layer
4. Length for providing the global signal line group 35 in the second layer It goes without saying that the global signal line group 35 may be provided in different wiring layers in the same way.

(Embodiment 2) FIG. 3 is a top view of a CMOS integrated circuit having two metal wiring layers laid out by the layout method according to the second embodiment of the present invention. FIG. 4 is taken from lines A and B in FIG. 3. A cross-sectional view is not shown.

First, the FETs are arranged in the same manner as in the first embodiment.

Reference numeral 23 denotes a power supply line (Vcc line) for the power supply voltage Vcc, which is wired using the -th and second metal wiring layers. In Example 1, the Vcc line 25a using the first metal wiring layer was used to reduce the aspect ratio of the contact hole between the FET and the Vcc line, so it was only wired on each circuit element. (In this example, in order to secure the power supply line width, both wiring layers are wired throughout the CMOS integrated circuit, and the Vcc line using the second metal wiring layer is connected to the PMOS-FET area. The wiring is routed from the front to the back so that they almost completely overlap, and the connection to the PMOS-PET is made through the first metal wiring layer.

24 is a power supply line (V'ss line) of voltage Vss to the base, using the metal wiring layer of the -th layer 1] to the NMOS-F
The wiring is done from the front to the back so that it almost completely overlaps the ET area.

Reference numeral 36 denotes a group of signal lines within the circuit elements in each circuit block of the CMOS integrated circuit, which are wired from the front to the back or from the right to the left using a polyzide wiring layer. Reference numeral 37 denotes a local signal line, which is wired from the front to the back below the Vcc line using the first metal wiring layer. Reference numeral 38 denotes a global signal line, which is wired above the Vss line from the front to the back using the second metal wiring layer, and is connected to the NMOS-FET or the signal line 36 (1iVss line). A hole is opened for the hole, and a first metal wiring layer is placed in the hole. Furthermore, since three wiring layers are used, the interlayer insulation film is also an interlayer insulation film 18 between the element and the voidized wiring layer, and an interlayer insulation film 19 between the polyzide wiring layer and the first metal wiring layer.
, and an interlayer insulating film 26 between the first metal wiring layer and the second metal wiring layer.

Furthermore, a CMOS integrated circuit having two metal wiring layers laid out by the conventional layout method shown in FIG. Comparing CMOS integrated circuits with metal wiring layers, the number of MO, 5FETs that can be placed within the same layout area (conventionally 4
However, in this embodiment, the number is twice as high as eight.

Conversely, if 8 MOS-FETs of the same size are arranged,
If the layout area is 1.00 in the conventional case, it is 0.55 in this embodiment, which can be reduced by 45%. Also, the Vss line and V
The wiring widths of the cc lines are respectively 1.0 in the conventional case, and in this embodiment they are 5 and 6', respectively, with a difference of 7 and 5 times.

As described above, according to this embodiment, it is possible to increase the degree of integration by making it possible to arrange circuit elements such as transistors over the entire semiconductor substrate in a cMOS integrated circuit without requiring a wiring area. In addition, the spacing between signal lines can be widened, the wiring length of signal lines and power supply lines can be shortened, and the wiring width of power supply lines can be increased, so mutual interference between signal lines can be avoided.
It can solve problems such as timing deviation (skew) between signals and problems such as power supply voltage drops and reference voltage fluctuations. Furthermore, by using a polycide wiring layer for the signal line group 34, flexibility in element placement, signal line routing, and connections between elements and signal lines and between signal lines and signal lines can be achieved. Becomes J Noh. Further, by wiring the signal line in the lower layer and the upper layer of each power supply line, the noise resistance of the signal line can be improved.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a very large C
In MOS integrated circuits, it is possible to place circuit elements such as transistors on the entire semiconductor substrate, which reduces the need for wiring area, thereby increasing the degree of integration. On the other hand, by using one side as a signal line between each circuit block (global signal line) and the other as a signal line within each circuit block (local signal line), and in addition, using a polycide wiring layer for the signal line within the circuit element, A layout with a high degree of freedom in routing of signal lines and connections between elements and signal lines and between signal lines becomes possible. Furthermore, among the power supply lines, the CC line is PMOS-FE.
The power supply line is strengthened by placing the Vss line on the NM○5-PET area, and the noise resistance of the signal line is improved by wiring the signal line in the lower and upper layers of each power supply line. It can provide a layout method that can be improved, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 shows a layout of a CMOS integrated circuit according to the first embodiment of the present invention.
3 is a cross-sectional view taken along line B. FIG.
The figure shows a cross section taken along line AB in Figure 3. Figure 5 shows a top view of a CMOS integrated circuit having two metal wiring layers laid out using this conventional layout method. Figure 6 shows a cross section taken along line AB in Figure 5. It is a diagram. 11...PMOS-FET area 12...
NMO8-FET region 13... MOS-FET region 14... Wiring region 23... Power supply line (Vcc line) of power supply voltage Vcc by the -th and second metal wiring layers, 24... First A power supply line (Vss line) for the base L voltage Vss by the metal wiring layer of 25a, a power supply line for the power supply voltage Vcc by the first metal wiring layer (V c
c line), 25b... Power supply line (Vcc line) of power supply voltage Vcc by the second metal wiring layer, 34... Connection between circuit elements in each block of the CMOS integrated circuit by the first metal wiring layer (Local signal line) group and signal line vein within circuit element 35...CMO by second metal wiring layer
Group of signal lines (global signal lines) between each circuit block of S integrated circuit, 36...CMO using polycide wiring layer
S Signal line group within circuit elements in each block of integrated circuit, 3
7.Local signal wind by first metal wiring layer 38.
・Global signal desk with second metal wiring layer

Claims (4)

[Claims] (1) For each metal wiring layer of a CMOS integrated circuit having two metal wiring layers, a power supply voltage Vc is applied to one wiring layer.
By allocating the power supply line (Vcc line) of c and the first signal line group, and the power supply line (Vss line) of reference voltage Vss and the second signal line group to the other wiring layer, the semiconductor A layout method for a CMOS integrated circuit, characterized in that circuit elements can be placed over the entire board. (2) Among the first and second signal line groups according to claim 1, one of the signal line groups is a group of signal lines (global signal lines) between each circuit block of a CMOS integrated circuit, and the other signal line group is a group of signal lines between each circuit block of a CMOS integrated circuit. is C
A layout method for a CMOS integrated circuit characterized by forming a group of signal lines (local signal lines) between circuit elements in each circuit block of the MOS integrated circuit and a group of signal lines within the circuit element. (3) A layout method for a CMOS integrated circuit, characterized in that the wiring layer of the signal line group in the circuit element according to claim 2 is a polycide wiring layer, and wiring is performed using three wiring layers. (4) In a CMOS integrated circuit with two metal wiring layers, the PMOS-FET region and NM
An OS-FET area is provided, and of the power supply lines allocated to each metal wiring layer, the Vcc line is connected to the PMOS-FET area.
The power supply line is strengthened by arranging the Vss line on the FET region and the NMOS-FET region, and the signal line group allocated to each metal wiring layer is connected to the lower and upper layers of each power supply line. 4. The CMOS integrated circuit layout method according to claim 1, wherein the noise resistance of the signal line is improved by wiring the signal line.