JPH04205894A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress an increase in erasing time even when the number of repeated rewriting times increases so as to improve the usability of on-board rewriting carried out under the control of a CPU by raising an erasure voltage for extracting electrons from a floating gate following the increase in the repeated rewriting times. CONSTITUTION:When the number of repeated rewriting times, namely, the value of a counter 20 is small, a booster circuit 21 does not work and external power supply VPP or an erasure voltage which is dropped in level by several volts from the power supply VPP is outputted to a source line switch 3. When the number of repeated rewriting times increases to such a degree that the erasing time starts to become longer, the circuit 21 works to raise the erasure voltage. As the value of the counter 20 increases further, the circuit 21 further raises the erasure voltage. Therefore, an increase in the erasing time can be prevented after the number of repeated rewriting times increases and the usability of on-board rewriting can be improved under the control of a CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to electrically programmable and batch erasable non-volatile semiconductor memory devices, particularly flash EEPROMs (El
electrically Erasable and P
rogrammabIe Read 0nly Mem
ory).

[Conventional technology]

FIG. 4 is a block diagram of a conventional flash EEFROM write and read circuit. The flash EEFROM shown in FIG. 4 is IEEE Journal or 5
olid-5tate C1rcuits, vol.
23. No, 50ctober 1988. 115
This is shown on pages 7 to 1163. Referring to FIG. 4, a Y gate 2, a source line switch 3, an X decoder 4, and a Y decoder 5 are provided around the memory cell array.

A stress clock is connected to the X decoder 4 and the Y decoder 5, and an address signal input from the outside is input thereto. A write circuit 7 and a sense amplifier 8 are connected to the memory cell array 1 via a Y gate 2. Write circuit 7 and sense amplifier 8 are connected to input/output buffer 9.

゛ A program voltage generation circuit 10 and a verify voltage generation circuit 11 are provided, and a power supply V supplied from the outside is provided.
A voltage different from ec and Vs is generated, and the voltage of ec is applied to the Y gate 2, the X decoder 4, etc. A command register 12 and a command decoder 13 are provided to set the operating mode according to data input from the outside, and the control circuit 14 receives control signals W and " from the outside.
E is given by σ1-2.

FIG. 5 is a sectional view of the memory cell shown in FIG. 4. With reference to FIG.
1.17 and source expansion? Area 18 and do, diffusion area 1
9. The thickness of the oxide film between the floating gauge 1/16 and the substrate 15 is as thin as, for example, about 100 mm).
This makes it possible to move electrons in the Floating Noggles 4...16 using the 7 failure phenomenon.

The operation of memory cell 1 is as follows. That is, during programming, a program voltage of about 6.5V is applied to the driver J19, Vpp (12V) is applied to the control gate I17, and the source 18 is grounded. Therefore, memory cell 1 is turned on and current flows. At this time, Avalanche breakdown occurs near the input 19, and pairs of electrons and holes are generated. These hole pairs flow to the ground potential through the substrate 15, and electrons flow toward the channel and are drained.

Flows into 19. Then, some electrons are accelerated by the electric field between the float 1.16 and the FL 19 to become 70-son 1.6'ge:・16? Be the master. In this way, increase the threshold voltage of memory cell 1. This is defined as recording of information ゛′φ゛′.

On the other hand, erasing is performed by setting the input 19 to 0, grounding the control gate 17, and applying Vpp to the north 18.・North 18 and Floaty, Gugate 16
Because of the potential difference between

In this way, the threshold value of memory cell 1 is lowered. This is defined as the storage of information ゛°1゛.

FIG. 6 is a diagram showing the configuration of memory cell A-I shown in FIG. 4. Referring to FIG. 6, the memory cell array has its drain connected to a bit line 24 and its control gate connected to a word line 25. The word line 25 is connected to the X decoder 4, and the bit line 24 is connected to the Y decoder 5.
The output of is input to its gate and is connected to the I10 line 27 via the Y gate transistor 26. ■70 line 27
The Senos amplifier 8 and the write circuit 7 are connected to the source line 28, and the source line 28 is connected to the source line switch 3.

Next, the operation of the conventional flash EEFROM will be explained with reference to FIGS. 4 to 6.

First, the operation when writing data to the memory cell 1 surrounded by the dotted line shown in FIG. 6 will be described.

In response to externally input data, write circuit 7 is activated and a program voltage is supplied to I10 line 27. At the same time, Y gate 26 and word line 25 are selected by the address signal via Y decoder 5 and X decoder 4, and vpp is applied to memory cell 1. source line 28
is grounded by the source line switch 3 during programming. In this way, current flows through only one cell in FIG. 6, a hot electron is generated, and its threshold voltage increases.

On the other hand, delete it as follows. First, X decoder 4 and Y decoder 5 are deactivated, and only memory cell 1 is made unselected.

That is, the word line 25 of each memory cell is grounded,
- Shiino is made open. On the other hand, a high voltage is applied to the source line 28 by the source line 3. In this way, the memory cell array 1 is
The threshold value is the lower one. Since the source line 28 is common, erasing should be performed for all memory cells at once.

Next, the read operation will be explained. In the same way as the write operation, reading of the memory cells surrounded by dotted lines in FIG. 6 will be described. First, the address signal is sent to Y decoder 5 and
It is decoded by the decoder 4, and the selected Y boo 1-2 and word line 25 become "H". At this time, the source line 28 is grounded by the source line switch 3. In this way, if data is written to the memory cell and its threshold value is high, the control gate of the memory cell
- Even if the "H" level signal is applied from the word line 25 to the word line 25, the memory cell does not turn on, and from the pit line 24 to the source line
No current flows through.

On the other hand, when the memory cell 11/L is erased, the memory cell is turned off, so a current flows from the line 24 to the source line 28. The controller 8 detects whether or not current flows through the memory cell, and reads the read data '1'.
", get "0". In this way, Furano, YuE
Data is written and read from the EPROM.

Another example of ROM is EFROM, which erases data by irradiating it with ultraviolet light. This kind of EPR
In OM, when the floaty, guge) becomes electrically neutral, no more electrons are extracted from the floaty, guge), and the threshold value of the memory transistor does not fall below about IV. On the other hand, when electrons are extracted using the )・channel phenomenon, electrons are excessively extracted from the floating gate, and the floating gate (・ becomes positively charged.This phenomenon is called over-erasure or over-erasure. (Memory) If the threshold value of Lanodisk becomes negative, subsequent reading and writing will be hindered. That is, words w, L are unselected during reading.
Beno L is ° “L” L- Beno, memory j・u...
Even if the level of the signal applied to the Roll Game 1 line is “L”, the memory 1-L J
, the current flows from the wire 24 through the wire 24, so the same wire is passed through the wire 24. -The memory cell that you are trying to read the line from is in the write state and has a high threshold value (both read °'1''.Also, even during writing, leakage current flows through the two over-erased memory cells). As a result, the write characteristics deteriorate and furthermore, it becomes impossible to write.

Therefore, after erasing, read data to check whether the erase was performed correctly (hereinafter referred to as "erase verify"), and if there are bits that are not erased, perform the erase again. A method is taken to prevent the application of erase pulses.

In this way, during erasing, erasing is performed by applying an erasing pulse several times. Figure 7 shows a flash EEPROM memory cell (
FIG. 4) shows a characteristic curve of the number of erase pulses for completing erasure with respect to the number of repeated rewrites. As the number of repeated rewrites increases, the number of erase pulses increases rapidly. This is because by repeating erasing, electrons are gradually trapped in the oxide film, and the electric field during erasing is relaxed by these electrons.

[Problem to be solved by the invention]

Since the conventional flash EEPROM was constructed as described above, there was a problem in that the erasing time increased as the number of repeated rewrites increased.

This invention was made to solve the above-mentioned problems, and by changing the memory erase voltage, the erase time after increasing the number of repeated rewrites can be made almost constant.
An object of the present invention is to obtain a nonvolatile semiconductor memory device that is easy to rewrite on-board, especially CPU@a.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention is an electrically writable/erasable nonvolatile semiconductor memory device in which a memory having a charge storage layer on a semiconductor substrate is arranged in a play shape in the row and column directions. The erasing voltage used to extract electrons from the charge storage layer is changed depending on the number of times of writing and erasing.

[Effect]

In the present invention, the erase voltage of the memory cell is changed by the counter I-value of the number of write/erase times to prevent the erase time from increasing after the number of repeated rewrites is increased, and is used on-board under CPU control. Sexuality improves.

Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a write/read circuit of a non-volatile semiconductor memory device which is an embodiment of the present invention. In the figure, the same reference numerals as in the conventional device are the same, and the explanation thereof will be omitted. In the figure, 20 is a counter that counts the number of write/erase times;
21 is a booster circuit. The booster circuit 21 performs a desired charge transfer operation using a plurality of diodes or circuits equivalent to diodes connected in series between the power supply input terminal and the booster output terminal, and capacitors connected to their mutual connection points. This is to obtain a boosted voltage.

When the number of repeated rewrites is small, that is, when the value of the counter (20) is small, the booster circuit 21 does not work.
The source line switch (3) is outputted with an external power supply Vpp or an erase voltage which is lowered. However, when the number of repeated rewrites increases further and the erasing time starts to rise to about the number of times (for example, point A in FIG. 7), the booster circuit (21) operates to increase the erasing voltage. Furthermore, when the counter (20) value increases, increase the voltage increase by the booster circuit to increase the erase voltage. FIG. 2 is a curve diagram showing how the erase voltage changes with respect to the number of times of repeated rewriting according to an embodiment of the present invention. Can compensate for relaxation. Therefore, the relationship between the number of repeated rewrites and the erasing time according to this embodiment is as shown in FIG.

[Effects of the Invention] As described above, according to the present invention, by increasing the erase voltage for extracting electrons from the floating knob gate as the number of repeated rewrites increases, the erase time does not increase even if the number of repeated rewrites increases. This has the effect of making it smaller and making it easier to rewrite the board under CPU control.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a write/read circuit of a non-volatile conductive memory device which is an embodiment of the present invention, and Fig. 2 shows the change in erase voltage with respect to the number of repeated rewrites which is an embodiment of the invention. FIG. 3 is a curve diagram showing the change in erase time with respect to the number of repeated rewrites and rewrites according to an embodiment of the present invention. FIG. 4 is a block diagram of a conventional flash EEPROM writing and reading circuit. The figure is a cross-sectional view of the memory cell in Figure 4, Figure 6 is a circuit diagram of the write/read circuit of the memory array in Figure 4, and Figure 7 shows the change in erase time with respect to the number of repeated rewrites of a conventional flash EEPROM. FIG. In the figure, 2 and 26 are Y gates, 3 is a source line switch, 4 is a χ decoder, 5 is a Y decoder, 7 is a write circuit, 8 is a setup, and 20 is a color. 21 indicates a booster circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claim] An electrically writable and erasable nonvolatile semiconductor memory device in which memory transistors each having a charge storage layer on a semiconductor substrate are arranged in an array in the row and column directions, comprising: A nonvolatile semiconductor memory device characterized in that an erase voltage for extracting electrons is written and changed according to a count value of the number of erases.