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JPH04199759A - Printed board - Google Patents

Printed board

Info

Publication number
JPH04199759A
JPH04199759A JP33392290A JP33392290A JPH04199759A JP H04199759 A JPH04199759 A JP H04199759A JP 33392290 A JP33392290 A JP 33392290A JP 33392290 A JP33392290 A JP 33392290A JP H04199759 A JPH04199759 A JP H04199759A
Authority
JP
Japan
Prior art keywords
circuit pattern
solder
main material
soldering part
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33392290A
Other languages
Japanese (ja)
Inventor
Seiji Sakami
省二 酒見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP33392290A priority Critical patent/JPH04199759A/en
Publication of JPH04199759A publication Critical patent/JPH04199759A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To enable a lead to be adhered by allowing it to land at a soldering part securely by laminating a circuit pattern and a soldering part and burying them and by making lower a surface of the soldering part which is exposed on the surface as compared with the surface for providing a stage difference. CONSTITUTION:A resist 2 corresponding to a shape of a circuit pattern is formed on a carrier 1 and a circuit pattern 3 is formed. Then, the resist 2 is released and the circuit pattern 3 is buried at a substrate main material 4 by a lamination press means. Then, the carrier 1 is released from the circuit pattern 3, the circuit pattern 3 is transferred to the main material 4, a surface part of the circuit pattern 3 is eliminated by etching, and a recessed part 5 is formed on an upper surface of the circuit pattern 3. A soldering part 6 is formed in lamination and a surface of the soldering part 6 which is exposed on a surface of the main material 4 is lowered as compared with a surface of the main material 4 by a stage difference d, thus enabling a recessed part 5 to remain partially for preventing a lead from being slid from the soldering part and enabling it to land at the soldering part positively.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はプリント基板に係り、電子部品のリードが、基
板の半田部に確実に着地できるようにしたものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a printed circuit board, and is designed to ensure that the leads of electronic components land on the solder portions of the circuit board.

(従来の技術) 電子部品をプリント基板に実装する手段として、基板主
材にエツチング手段などにより回路パターンを形成し、
更にこの回路パターンの電極部に半田レベラーや半田メ
ツキなどにより半田部を形成し、この半田部上に、電子
部品のリードを着地させた後、半田部を加熱溶融して、
リードを回路パターンの電極部に接着することが行われ
ている。
(Prior art) As a means of mounting electronic components on a printed circuit board, a circuit pattern is formed on the main material of the board by etching, etc.
Furthermore, a solder part is formed on the electrode part of this circuit pattern using a solder leveler or solder plating, and after landing the lead of the electronic component on this solder part, the solder part is heated and melted.
The leads are bonded to the electrode portions of the circuit pattern.

(発明が解決しようとする課題) ところが半田部は基板の表面よりも高いことから、リー
ドを半田部に着地させた際に、リードが半田部から滑り
落ちやすい問題があった。
(Problems to be Solved by the Invention) However, since the solder portion is higher than the surface of the board, there is a problem in that the lead easily slips off the solder portion when the lead lands on the solder portion.

殊に近年は、高密度、高集積化の要請から、リードi′
L益々狭ピンチ化する傾向にあることから、リー1の滑
りによる僅かな位置ずれでも、実装不良になりやすいも
のであった。
Especially in recent years, due to the demand for high density and high integration, lead i'
Since there is a tendency for L to be pinched more and more narrowly, even a slight positional deviation due to slipping of L 1 tends to cause mounting defects.

そこで本発明は、リードの滑りを防止できるプリント基
板を提供することを目的とする。
Therefore, an object of the present invention is to provide a printed circuit board that can prevent the leads from slipping.

(課題を解決するための手段) 本発明は、基板主材の表面に、回路パターンと半田部を
積層して埋設し、この基板主材の表面に露呈する半田部
の表面を、基板主材の表面と同一レベル、若しくはこの
表面よりも低くして段差を付与したものである。
(Means for Solving the Problems) The present invention laminates and embeds a circuit pattern and a solder part on the surface of a main board material, and the surface of the solder part exposed on the surface of the main board material is A step is provided at the same level as or lower than the surface.

(作用) 上記構成によれば、リートは半田部から滑り落ちること
はなく、半田部に確実に着地できる。
(Function) According to the above configuration, the leat does not slip off from the solder portion and can reliably land on the solder portion.

(実施例1) 次に、図面を参照しながら本発明の詳細な説明する。(Example 1) Next, the present invention will be described in detail with reference to the drawings.

第1図はプリント基板の製造工程を示している。同図(
a)において、1はS U Sなどの金属薄板から成る
担体であり、この担体1上に回路パターンの形状に対応
するレジスト2を形成しく同図(b)) 、次いでこの
担体1上に、銅メツキ手段により回路パターン3を形成
する(同図(C)参照)。
FIG. 1 shows the manufacturing process of a printed circuit board. Same figure (
In a), 1 is a carrier made of a thin metal plate such as SUS, and a resist 2 corresponding to the shape of the circuit pattern is formed on this carrier 1 (FIG. 2(b)), and then on this carrier 1, A circuit pattern 3 is formed by copper plating means (see (C) in the same figure).

次いでレジスト2を剥離しく同図(d))、回路パター
ン3を、積層プレス手段により基板主材4に埋設する(
同図(e))。この主材4は、例えばガラス繊維にエポ
キシ樹脂を含浸させたものであって、若干の柔らかさを
有している。
Next, the resist 2 is peeled off (FIG. 2(d)), and the circuit pattern 3 is embedded in the substrate main material 4 by lamination press means (
Figure (e)). The main material 4 is, for example, glass fiber impregnated with epoxy resin, and has some softness.

次いで担体Iを回路パターン3から剥離し、回路パター
ン3を主材4に転写する(同図(f))。次いでエツチ
ングにより、回路パターン3の表層部を除去し、回路パ
ターン3の上面に凹部5を形成する(同図(g))。こ
のエツチングは、回路パターン3の全面について行って
もよく、あるいは次工程で半田部が形成されて電極部と
なる部分だけ行ってもよい。
Next, the carrier I is peeled off from the circuit pattern 3, and the circuit pattern 3 is transferred to the main material 4 (FIG. 4(f)). Next, the surface layer of the circuit pattern 3 is removed by etching to form a recess 5 on the upper surface of the circuit pattern 3 (FIG. 3(g)). This etching may be performed on the entire surface of the circuit pattern 3, or may be performed only on the portions where solder portions will be formed in the next step to become electrode portions.

次いで回路パターン3上にメツキ手段などにより半田部
6を積層形成する(同図(h))。
Next, a solder portion 6 is laminated on the circuit pattern 3 by plating means or the like (FIG. 6(h)).

この場合、主材4の表面に露呈する半田部6の表面上主
材40表面よりも段差dだけ低くなるようにし、上記凹
部5を部分的に残存させる。
In this case, the surface of the solder portion 6 exposed on the surface of the main material 4 is made to be lower than the surface of the main material 40 by the step d, so that the recessed portion 5 is partially left.

以上の工程によりプリント基板10が形成される。The printed circuit board 10 is formed through the above steps.

このプリント基板10にQFPのようなり一ト付電子部
品を実装するにあたっては、半田部6にフラツクスを塗
布し、リードLを半田部6に着地させる(第2図参照)
。上記のように、半田部6は凹部5に形成されているの
で、リー)Lば凹部5に嵌合して位置決めされ、半田部
6に確実に着地でき、次いで半田部6を加熱溶融させる
ことにより、リードしは半田部6に接着される。
When mounting an electronic component such as a QFP on this printed circuit board 10, flux is applied to the solder portion 6, and the leads L are landed on the solder portion 6 (see Fig. 2).
. As described above, since the solder part 6 is formed in the recess 5, the solder part 6 can be fitted into the recess 5 and positioned, and can securely land on the solder part 6, and then the solder part 6 can be heated and melted. As a result, the leads are bonded to the solder portion 6.

(実施例2) 第3図において、担体1上にレジスト2を形成した後、
非レジスト面に半田部6を形成し、次いで回路パターン
3を半田部6に積層形成する(同図(a)〜(d))。
(Example 2) In FIG. 3, after forming the resist 2 on the carrier 1,
A solder portion 6 is formed on the non-resist surface, and then a circuit pattern 3 is laminated on the solder portion 6 (FIGS. 3(a) to (d)).

次いでレジスト2を剥離した後、半田部6と回路パター
ン3を基板主材4に埋設する(同図(e)、(f))。
Next, after peeling off the resist 2, the solder portion 6 and the circuit pattern 3 are embedded in the substrate main material 4 (see (e) and (f) in the same figure).

次いで担体1を剥離して、半田部6と回路パターン3を
主材4に転写しく同図(g)) 、次いでエツチングに
より半田部60表層部を除去して凹部5を形成し、段差
dを付与する(同図(h)。したがって本方法によって
も、リードしは凹部5に嵌合して位置決めできる。
Next, the carrier 1 is peeled off, and the solder portion 6 and the circuit pattern 3 are transferred to the main material 4 (FIG. 1(g)). Next, the surface layer of the solder portion 60 is removed by etching to form the recess 5, and the step d is removed. ((h) in the same figure. Therefore, also by this method, the lead can be fitted into the recess 5 and positioned.

なお上記実施例は、半田部6は基板主材4の表面よりも
段差dを付与して低くしているが、半田部6が基板主材
4の表面と同一レベルであっても、リードLの半田部6
からの滑り落ちは防止できるので、同一レベルにしても
よい。
In the above embodiment, the solder part 6 is lower than the surface of the main board material 4 by providing a step d, but even if the solder part 6 is at the same level as the surface of the main board material 4, the lead L solder part 6
It is also possible to keep them at the same level since this will prevent them from slipping off.

(発明の効果) 以上説明したように本発明は、基板主材の表面に、回路
パターンと半田部を積層して埋設し、この基板主材の表
面に露呈する半田部の表面を、基板主材の表面と同一レ
ベル、若しくは表面よりも低くして段差を付与している
ので、半田部に着地したリードが滑って位置ずれするよ
うなことはなく、リードを半田部に確実に着地させて傍
ら゛することができる。
(Effects of the Invention) As explained above, the present invention laminates and embeds a circuit pattern and a solder part on the surface of a main board material, and the surface of the solder part exposed on the surface of the main board material is Since the step is provided at the same level as the surface of the material or lower than the surface, the lead that lands on the solder area will not slip and become misaligned, and the lead will land securely on the solder area. You can stand by.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示すものであって、第1図はプリ
ン1一基板の製造工程図、第2図は実装中の要部断面図
、第3図は他の実施例のプリント基板の製造工程図であ
る。 3・・・回路パターン 4・・・基板主材 6・・・半田部 10・・・プリン1一基板
The drawings show an embodiment of the present invention, in which Fig. 1 is a manufacturing process diagram of the printed circuit board 1, Fig. 2 is a sectional view of the main part during mounting, and Fig. 3 is a printed circuit board of another embodiment. FIG. 3...Circuit pattern 4...Board main material 6...Solder part 10...Print 1-board

Claims (1)

【特許請求の範囲】[Claims] 基板主材の表面に、回路パターンと半田部を積層して埋
設し、この基板主材の表面に露呈する半田部の表面を、
基板主材の表面と同一レベル、若しくはこの表面よりも
低くして段差を付与したことを特徴とするプリント基板
The circuit pattern and the solder part are layered and buried on the surface of the main board material, and the surface of the solder part exposed on the surface of the main board material is
A printed circuit board characterized in that a step is provided at the same level as or lower than the surface of the main board material.
JP33392290A 1990-11-29 1990-11-29 Printed board Pending JPH04199759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33392290A JPH04199759A (en) 1990-11-29 1990-11-29 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33392290A JPH04199759A (en) 1990-11-29 1990-11-29 Printed board

Publications (1)

Publication Number Publication Date
JPH04199759A true JPH04199759A (en) 1992-07-20

Family

ID=18271469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33392290A Pending JPH04199759A (en) 1990-11-29 1990-11-29 Printed board

Country Status (1)

Country Link
JP (1) JPH04199759A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332821A (en) * 2000-05-25 2001-11-30 Matsushita Electric Ind Co Ltd Circuit board and its manufacturing method
KR101009110B1 (en) * 2008-11-12 2011-01-18 삼성전기주식회사 Printed circuit board with buried solder bumps and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332821A (en) * 2000-05-25 2001-11-30 Matsushita Electric Ind Co Ltd Circuit board and its manufacturing method
KR101009110B1 (en) * 2008-11-12 2011-01-18 삼성전기주식회사 Printed circuit board with buried solder bumps and manufacturing method thereof

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