JPH04199658A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a transistor to be enhanced in performance and an element isolating region to be micronized by a method wherein a region just under a semiconductor substrate shield and a channel region are set different from each other in impurity concentration. CONSTITUTION:An insulating film is formed on the primary surface of a semiconductor substrate, a shield 110 fixed at the same potential as the semiconductor substrate is formed through the intermediary of an insulating film 103', a gate insulating film 108 is formed on a channel region which is sandwiched between a source and a drain formed on the semiconductor substrate and different in impurity concentration from a semiconductor substrate region just under the shield 110, a gate electrode 109 is provided, and a first and a second MOS type transistor are provided, where a shield is formed between them. An Si substrate region is controlled in impurity concentration so as to enable the transistors to be enhanced enough in characteristics to meet requirements and an element isolation region to be enhanced enough in breakdown strength to meet requirements, and furthermore the insulating film 103' just under the shielding material 110 and the gate oxide films 108 of the transistors are separately controlled. By this setup, not only a transistors can be enhanced enough in performance but also an element isolation region can be micronized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to an element isolation structure on a semiconductor substrate on which a plurality of transistors are formed.

(Prior Art) There are many semiconductor devices in which a plurality of transistors are formed on a semiconductor substrate, and in these types of devices, it is an important issue to reliably isolate the transistors.

Element isolation of a semiconductor device will be explained with reference to a row decoder in a semiconductor memory. An example of this is shown in Figure 6(a).
Shown in (b). The well-known L
Thick field oxide film 56 formed by OCO3 method
separated by An impurity for preventing field inversion is doped 57 directly under the field oxide film. Generally, when forming a thick field oxide film by the LOCO8 method, consideration must be given to the occurrence of bird's peaks and the seepage of impurities for preventing field inversion into the channel portion. Furthermore, in the case of fine isolation, in addition to processing the field oxide film, it is necessary to increase the concentration of impurities to prevent field reversal, but this increases the diffusion of impurities into the channel regions of transistors located on both sides, increasing the effective channel width of the transistor. As it becomes narrower, the narrow channel effect/back bias effect worsens. Particularly in devices where the potential difference between separated elements is high, when the concentration of the impurity for preventing field reversal increases, the impurity for preventing field reversal will enter the concentration of the drain diffusion layer of the transistor located on both sides of the field oxide film. This oozing creates a steep PN junction, which significantly deteriorates the junction breakdown voltage between the Si substrate where the transistors located on both sides of the field oxide film are formed and the drain diffusion layer of the transistor.

This made fine separation difficult. Therefore, there is an element isolation formed by the method shown in FIGS. 7(a) and 7(b). An impurity 62 for controlling the channel of a transistor is introduced onto the Si substrate 61, and after a gate oxide film 71 is formed, polycrystalline silicon that will become a gate electrode 68 and a shield 67 is formed. In the second step of processing the polycrystalline silicon, a gate electrode 68 and a shield 67 are formed, and the shield is wired to the same potential as the semiconductor substrate at the same time as the transistor wiring. When elements are separated using such a method, perspective peaks do not occur. Furthermore, the area directly under the shield is doped only with impurities for channel control of the transistors located on both sides, and this concentration is much lower than the impurity used for field reversal prevention used in LOGO8 isolation, so that it does not diffuse into the channel area. can be ignored, and deterioration in the junction breakdown voltage between the Si substrate and the diffusion layer of the transistor located on both sides of the shield can also be ignored to some extent.

The shield 67 is bonded to a P diffusion layer 70 of the same conductivity type as the Si substrate provided on the Si substrate through a contact hole 69 in an insulating film separating the two.

In the element isolation formed by the conventional technique, the transistors located on both sides and the Si substrate directly under the shield are doped with the same impurity pillar or at the same concentration. Further, the insulating film directly under the shield has the same thickness as the gate oxide films of the transistors located on both sides. Since the impurity concentration directly under the shield and the channel impurity concentration of the transistors located on both sides are not individually optimized, the element isolation ability and (
(junction, surface) playdown breakdown voltage is equivalent to the transistors located on both sides of the shield. Therefore, the separable width is limited to the punch-through limit of the transistors located on both sides, which limits miniaturization. Furthermore, if a reduction in element isolation width is prioritized for the purpose of reducing the chip size, this becomes a limiting factor in transistor element design.

In other words, by finely adjusting the V'' of the transistor, the element isolation ability and junction and surface breakdown voltage of the transistor diffusion layers located on both sides of the shield will be sensitively changed.Conversely, element isolation by the shield will vary. When the impurity concentration and oxide film pressure are controlled in order to increase the performance or surface breakdown voltage, the channel impurity concentration and oxide film pressure of the transistors located on both sides will change accordingly, changing the transistor characteristics. This makes it difficult to design.

(Problems to be Solved by the Invention) As described above, as the miniaturization of semiconductor devices progresses, prioritizing element isolation has traditionally limited transistor element design, and conversely, improving transistor design has limited element isolation. There was a problem that had to be solved in that the miniaturization of the width was restricted.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device that can be miniaturized without having element isolation and transistor element design influenced by each other, and a method for manufacturing the same.

[Configuration of the Invention (Means for Solving the Problems) In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate on which an insulating film is formed on the main surface, and a semiconductor substrate on which an insulating film is formed on the main surface. , a shield formed via an insulating film formed on the main surface of the semiconductor substrate and fixed to the same potential as the semiconductor substrate, a source and drain region formed on the semiconductor substrate, and a shield sandwiched between these regions. a channel region whose impurity concentration is different from the impurity concentration of the semiconductor substrate region immediately below where the shield is formed, a gate insulating film formed on this region, and a gate formed on the gate insulating film. The first feature is that the device includes first and second MOS type transistors having an electrode and a shield formed between them. A second feature is that the insulating film directly under the shield is thicker than the gate insulating film of the transistor.

The third feature is a semiconductor substrate having an insulating film formed on the main surface thereof, and a semiconductor substrate formed on the semiconductor substrate via the insulating film formed on the main surface of the semiconductor substrate, and having the same potential as the semiconductor substrate. A fixed shield, a source and drain region formed on the semiconductor substrate on both sides of the shield on the semiconductor substrate, a channel region sandwiched between these regions, and a film thickness formed on this region. comprises a gate insulating film thinner than the insulating film directly under the shield, a gate electrode formed on the gate insulating film, and first and second MOS transistors with a shield formed therebetween. It is in the fact that

A fourth feature is that the drain regions of the first and second MOS transistors have an LDD structure.

Further, the method for manufacturing a semiconductor device of the present invention includes a step of introducing an impurity into a region where a transistor is to be formed of a semiconductor substrate having an insulating film formed on the main surface, and a step of introducing an impurity into a region where a shield is to be formed of the semiconductor substrate. a step of introducing an impurity at a concentration different from the impurity concentration in , and a step of forming a shield fixed to the same potential as the semiconductor substrate on the semiconductor substrate via an insulating film formed on the main surface of the semiconductor substrate. , a source and drain region formed in the semiconductor substrate; a channel region sandwiched between these regions and having an impurity concentration different from that of the semiconductor substrate region directly below where the shield is formed; First and second MO8s each having a gate insulating film formed on the region and a gate electrode formed on the gel insulating film.
The first feature is that the gate electrode and the shield are made of the same material, and the second feature is that the gate electrode and the shield are made of the same material. There is.

(Function) An element isolation region is formed with a silicon oxide film formed by the LOCO3 method on a semiconductor substrate, and a gate insulating film is formed above the element isolation, and a film thickness between the gate insulating films or a thick film is formed between the gate insulating films and the element isolation region. An insulating film that is thinner than the silicon oxide film in the isolation region is formed, and impurities are introduced into the region where the transistor is to be formed and the region where the shield is to be formed at different concentrations, so that the characteristics of the transistors located on both sides of the shield and the element isolation are improved. By controlling the impurity concentration in the Si substrate region so as to satisfy both the breakdown voltage in the region, and by individually controlling the insulating film directly under the shield material and the gate oxide film of the transistor, it is possible to improve the transistor characteristics. Improved performance and fine element isolation can be achieved at the same time.

Furthermore, when controlling the introduction of impurities into the Si substrate directly under the shield for the purpose of fine separation, the diffusion layers located on both sides of the shield can be made into an LDD structure, although the junction breakdown voltage tends to deteriorate. Therefore, the junction becomes looser and the junction breakdown voltage is greatly improved.

The shield used in the present invention is characterized in that it is made of the same material as the gate electrodes of the transistors located on both sides, so that the shield can be formed at the same time as the material for the gate electrodes of the transistors is formed. Therefore, the increase in the number of steps can be kept to a minimum.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

Embodiment 1 First, a P-type silicon substrate 101 is shown in FIG.
A field oxide film 102 with a thickness of 500 nm is formed on the
A 20 nm thick oxide film 103 is formed on the surface of the silicon substrate 101 by thermal oxidation. In the area where the transistors that constitute the row decoder circuit and are located approximately in parallel are to be formed,
A resist pattern 104 is formed in a region that separates the transistors located substantially parallel to each other, and using this as a mask, "boron" for controlling the yTH of the transistor is implanted using well-known ion implantation technology at an acceleration voltage of 50 keV and a dose amount. Doping with 4 x 1012 cm2 (Fig. 1(a)
)). Next, using the resist pattern 104 as a mask, the resist pattern 11103 is oxidized and removed by etching using NH4F. (Figure 1(b)). Next, after removing the resist pattern 104, a resist pattern 104 is formed in the region excluding the element isolation regions of the transistors located substantially parallel to each other.
Then, using the resist pattern 106 as a mask, "boron" is implanted using a well-known ion implantation technique at an acceleration voltage of 80 keV and a dose of 8X IQ 12/cm.
2 (FIG. 1(C)). Next, after removing the resist pattern 106, the silicon substrate 10
At the same time, an oxide film 108 with a thickness of 20 nm is formed on one surface by thermal oxidation, and at the same time, an oxide film 108 is formed on the element isolation region of the transistors located almost parallel to each other in the row decoder circuit.
3 activates "boron" ions 105 and 107 introduced into the channel portion at the same time as 103- grows into a 30 nm oxide film. After that, 40
After forming a 0 nm polysilicon film, a gate electrode 109 and a shielding polysilicon wiring pattern 110 are formed using well-known ring graphie technology and RIE technology, and then an acceleration voltage of 40 ke is applied using ion implantation technology.
Dope "phosphorus" ions into the source/druin formation area at a dose of 5 x 10"/cm2 (
Figure 1(d)). Next, at least the region where the toluin is to be formed is 0.0 mm from the edge of the gate electrode 109 and the polysilicon wiring pattern 110 for shielding. 5 [um] Resist pattern 1 covers the surface of the silicon substrate 101
After forming 11, the accelerating voltage 4 is applied using ion implantation technology.
A part of the region where the source train is to be formed is doped with "arsenic" ions at 0 keV and at a dose of 7.times.10.sup.15/cm.sup.2 (FIG. 1(e)). Next, a 40 nm post-oxidation film 112 is formed by thermal oxidation at 900° C., and at the same time, the "phosphorus" and "arsenic" ions doped in the source/drain formation regions are activated, and then a laminated film 115 of SiO2/BPSG is formed as a passivation film. LPCVD
After deposition by a method, a wiring pattern 116 having a contact hole opening diameter A1 is formed. A part of the A1 wiring pattern 116 was wired to a P diffusion layer provided on the same substrate as the polysilicon wiring 110 for shielding (FIG. 1(r)).

In the case manufactured by the method shown in Fig. 1, the thickness of the silicon oxide film directly under the polysilicon wiring pattern for shielding is
Since it is thicker than transistors existing on the same substrate, it is possible to separate at least a larger potential difference than the potential difference applied to transistors existing on the same substrate. Therefore, the desired element isolation ability can be obtained without increasing the doped impurity "boron" concentration of the silicon substrate directly under the polysilicon wiring pattern, and the junction and surface breakdown voltage can be increased.
High reliability can be obtained.

Example 2 The embodiment shown in FIGS. 2(a) to 2(c) will be described.

First, a field oxide film 202 with a thickness of 500 nm is formed on a P-type silicon substrate 201, and an oxide film 203 with a thickness of 20 nm is formed on the surface of the silicon substrate 201 by thermal oxidation. A resist pattern 204 is formed in a region where transistors located substantially parallel to each other constituting a row decoder circuit are to be formed, and a resist pattern 204 is formed in a region separating the transistors located substantially parallel to each other. Using ion implantation technology, the acceleration voltage is 80 keV and the dose is 2.
Doping with X 1012/cm2 (Fig. 2(a)
)).

Next, the oxide film 203 is removed by etching with NH4F using the resist pattern 204 as a mask (FIG. 2(b)).
). Next, after removing the resist pattern 204,
Using well-known ion implantation technology, “boron” is accelerated at a voltage of 8
Doping is performed at 0 keV and at a dose of 8 x 1.012/cm2 (FIG. 2(c)).

In addition to the effects explained in FIG. 1, the product manufactured using the method shown in FIG. increased and reduced manufacturing costs. In addition, the "arsenic" ion-implanted in FIG. 2(C) is used for VTH control of the D-type transistor formed on the same substrate, although it is not shown in FIG. 2(C). Since this process was also used as an ion implantation process, the addition of a process resulting from the technique related to the present invention was only a small one, such as removing the oxide film 203 by NH4F etching as explained in FIG. 2(b).

Example 3 The embodiment shown in FIGS. 3(a) to 3(c) will be described.

First, a film thickness of 500 nm is formed on a P-type silicon semiconductor substrate 301.
A field oxide film 302 is formed on the silicon substrate 30.
A 20 nm thick oxide film 30B is formed on one surface by thermal oxidation. A resist pattern 304 is formed in the region where the transistors located substantially parallel to each other constituting the row decoder circuit are to be formed, and the resist pattern 304 is formed in the region separating the transistors located substantially parallel to each other. "Boron" is doped using a well-known ion implantation technique at an accelerating voltage of 50 keV and a dose of 4 x 1012/gloss 2 (Fig. 3(a)).

Next, after removing the resist pattern 304, in the row decoder circuit, a resist pattern 304 is applied to the region excluding the element isolation regions of the transistors located substantially parallel to each other.
Then, using the resist pattern 306 as a mask, "boron" was implanted using a well-known ion implantation technique at an acceleration voltage of 80 keV.

Doping is performed at a dose of 8×10 12 /(1) 2 (FIG. 3(b)). Next, after removing the resist pattern 306 and removing the oxide film 303 with NH4F, a 20 nm thick oxide film 308 is formed on the surface of the silicon substrate 101 by thermal oxidation, and at the same time "boron" ions 305 introduced into the channel part are removed. and activate 307.

Thereafter, a 400 nm thick polysilicon film 309 is formed by the LPCVD method (FIG. 4(C)). Thereafter, the gate electrode 3 is formed using well-known lithography technology and RIE technology.
17 and polysilicon wiring pattern 31 for shielding
After forming 8, the same steps as shown in FIGS. 1(d) to 1(e) were carried out to produce the product shown in FIG. 3(f).

Example 4 The embodiment shown in FIGS. 4(a) to 4(b) will be described.

First, a field oxide film 402 with a thickness of 500 nm is formed on a P-type silicon substrate 401, and an oxide film 403 with a thickness of 20 nm is formed on the surface of the silicon substrate 401 by thermal oxidation. A resist pattern 404 is formed in the area where the transistors located substantially parallel to each other constituting the row decoder circuit are to be formed, except for the region separating the transistors located substantially parallel to each other. ” using well-known ion implantation technology at an accelerating voltage of 50ke.
Doping with V18×1012/cIT12 (4th
Figure (a)). Next, after removing the resist pattern 404, "boron" for controlling V7H of the transistor is doped using a well-known ion implantation technique at an acceleration voltage of 80 keV and a dose of iL4 x 10''/cm2 (see FIG. 4(b)). )).The subsequent steps were the same as those shown in Figure 3.

The above-mentioned N-channel MOS type memory device has achieved fine element isolation in the row decoder section, and has been able to significantly reduce the size of the semiconductor chip.

In the devices manufactured by the method shown in FIGS. 3 and 4, the thickness of the oxide film directly under the polysilicon for shielding and the thickness of the gate oxide films of the transistors on both sides are the same. For this reason, although the oxide film directly under the shielding polysilicon is manufactured using the method shown in FIGS. 1 and 2, the improvement in element isolation ability is relatively small; Although the device isolation ability is lower than that manufactured by the method shown above, the use of the gate oxide film of the transistor existing on the same substrate and the shielding shown in FIGS. 3(b) and 4(a) The doping process into the substrate directly below the polysilicon used for this purpose also served as the ion implantation process for controlling the VT□ of transistors on the same substrate other than the transistors separated using this technology. There was no increase at all.

Although not shown as an embodiment, the present invention can also be applied to the PMO3 side of a CMOS memosa memory device.

In addition, the ion species doped into the silicon substrate directly under the polysilicon wiring pattern for shielding is not limited to boron, but may also be phosphorus, arsenic, etc.
Several ion species may be combined, especially CM
For application to the PMOS side of OS-type memosa memory devices, a design that improves isolation ability is achieved by combining ion implantation of phosphorus, arsenic, etc. for doping into the silicon substrate directly under the polysilicon wiring pattern for shielding. In addition, when applied to the PMOS side, the isolation ability is improved by combining ion implantation of "phosphorus", "arsenic", etc. to dope the silicon substrate directly under the polysilicon wiring pattern for normal shielding. In addition, VTH control of a normal PMOSh transistor is performed by implanting boron 2 ions into the silicon substrate directly under the polysilicon wiring pattern for shielding.
Since doping with boron tends to reduce the isolation ability, good results can be obtained even if the silicon substrate directly under the shielding polysilicon wiring pattern is not doped.

In a device using the element isolation technology described above, the row decoder of a memory device, which has a large influence on the semiconductor chip size, can be miniaturized, the semiconductor chip can be downsized, and manufacturing costs can be reduced.

Impurities doped for VT)1 control of the silicon substrate directly under the polysilicon wiring pattern for shielding and the transistors on both sides are not performed in the same process, so they can be controlled with different impurity concentrations or different impurity types. This is possible because it can be designed separately from transistor characteristics.

In addition, because the edge of the polysilicon shield is formed with a low concentration drain or train and source, the electric field relaxation effect significantly increases the junction and surface breakdown voltage. As a result, the potential difference between the elements separated by the shield may be a high potential, and the potential difference between the diffusion layers (source and drain of the transistor) on both sides of the shield is reduced by the field (LOCO5) that exists on the same substrate. By adopting a circuit configuration that is larger than the potential difference between the source and drain regions of the transistor that are separated by the thickness of the silicon oxide film (formed by the method), the chip size can be reduced without deteriorating reliability.

In addition, the impurity concentration of the silicon substrate directly under the polysilicon wiring pattern for shielding depends on the junction and surface breakdown voltage, but due to the high breakdown voltage, the impurity concentration of the silicon substrate directly under the polysilicon wiring pattern for shielding The concentration design can be chosen within a wide range. In other words, if there is a region separated by polysilicon for shielding, not only the transistor design but also the impurity concentration of the silicon substrate directly under the polysilicon wiring pattern for shielding, which increases only the isolation ability to some extent without worrying about breakdown voltage. It will be a good thing if you do.

Embodiment 5 FIGS. 5(a) to 5(d) are cross-sectional views of the manufacturing process of a semiconductor device according to Embodiment 5 of the present invention. First, a field oxide film 502 with a thickness of about 500 nm is formed on a P-type semiconductor substrate (silicon) 501, and an oxide film 503 with a thickness of 20 nm is formed on the surface of the silicon substrate 501 by thermal oxidation. Boron, for example, for transistor channel control is doped using a well-known ion implantation technique at an acceleration voltage of 50 KeV and a dose of 8×10 12 /Cm 2 (FIG. 5(a)). In the region where the substantially parallel transistors constituting the row decoder path are to be formed, a resist pattern 504 is formed in a region separating the substantially parallel transistors from each other (FIG. 5(b)). Using this as a mask and using NH4F, the resist pattern 5
The silicon oxide film except directly under 04 is removed by etching (FIG. 5(C)). Next, after completely removing the resist pattern, a 20 nm thick oxide film 503 is formed in the area where the transistor is to be formed by thermal oxidation, and at the same time, the oxide film 503 in the area where the resist pattern 504 was present has a thickness of 30 nm. The oxide film 506 of the film grows (
Figure 5(d)). The following steps are performed in the same manner as the steps shown in FIG. 1(d) and subsequent steps to form a row decoder circuit. In products manufactured using this method, the impurities directly under the shielding polysilicon wiring pattern are equivalent to the channel impurities of the transistors on both sides of the shield, so the isolation is the same as in the conventional method (see Figure 7). Width is the limit.

Therefore, although it is not possible to achieve as fine separation as in Examples 1 to 4, since the silicon oxide film directly under the shield is thicker than the transistors existing on the same substrate, it is possible to separate potential differences greater than the surface breakdown voltage of the transistors. can. In this example, it increases by about 20%. Therefore, high reliability can be guaranteed, and high voltage can be used in testing at the time of shipment and during device development, reducing test time by about 20% and lowering test costs. To show concrete numerical values of how the semiconductor device of the present invention has progressed in miniaturization, it can be seen that the apparent size of the semiconductor device using a conventional field oxide film for element isolation is higher than that of the above transistor punch-through limit. 1.
3 μm, 1.1 for PMO3, czm, the punch-through limit of a semiconductor device using element isolation using a shield is 0.7 μm for NMOS, 0.8 for PMO3
μm, but in the case of the present invention, NMO3 is 0.5 μm.
The result was that m1PMO3 was 0.4 μm.

As described above, in the embodiment, P-type silicon was used as the semiconductor substrate, but the present invention is not limited to this, and for example,
It is of course possible to apply the present invention to existing materials such as Ge and InPSGaAs. Further, the row decoder described in the embodiment is just one example, and can be applied to a semiconductor device in which elements of the same structure are repeatedly arranged with element isolation in between.

The shield according to the present invention does not need to be located at the center of the first and second transistors, and may be located closer to either one, or even if it is slightly off the line connecting both transistors, the element isolation effect can still be achieved. It is within the scope of the present invention as long as the

[Effects of the Invention] With the above-described structure, the present invention improves the transistor characteristics by varying the impurity concentration in the region directly under the shield and the channel region of the semiconductor substrate, and by increasing the thickness of the insulating film directly under the shield. It is possible to achieve high performance and miniaturization of element isolation at the same time.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views of a semiconductor device and its manufacturing process according to Example 1 of the present invention, and FIGS. 2(a) to (c) are
3(a) to 3(d) are sectional views of a semiconductor device according to a third embodiment of the present invention and its manufacturing process, and FIG. a),
(b) is a sectional view of a semiconductor device according to a fourth embodiment of the present invention and its manufacturing process; FIG. 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention and its manufacturing process; FIG. 5(a) ~(d
) is a cross-sectional view of the semiconductor device and manufacturing process of Example 5 of the present invention, FIG. 6(a) is a plan view of an element isolation structure according to the prior art, and FIG. 6(b) is a cross-sectional view of the semiconductor device and manufacturing process of Example 5 of the present invention. 7(a) is a plan view of an element isolation structure according to the prior art; FIG. 7(b) is a sectional view taken along line BB- of FIG. 7(a). 101.201..301.401.501,58.6
]...P-type semiconductor substrate, 120.220,32
0,420,420.57...P-layer for preventing field inversion 102.202,302,402,502.56...
...Field oxide film, 103.203,303,4
03,503. ...Silicon oxide film, 103'
...103 is a thickened silicon oxide film, 1
04.106,111,204. ．． 304,306,4
04,504...Resist, 1 (17,205
,206,305,307,4f)5,408...
...Impurity ions 108.308, 505, 59.71
...Gate oxide film, 309...Polysilicon film, 109.31.7,54,55.68...-Gate electrode (polysilicon) 110.318.67. ...
・・Shield (polysilicon), 1.12,313,5
0,51,63.64. Ei5. Ei8...N
-diffusion layer, 11.3,312...~N-diffusion layer,
114.316.70...P'diffusion layer, 11.
2,311... Post oxidation film, 05.314...
...SiO2/BPSG multilayer film, 1.1B, 315.
...Aluminum wiring, 69...Contact hole. Applicant's representative Patent attorney Hisashi Takemura Figure 1 (tL) 1st m (C) Houki 1 Figure (d + 1! I (e) Figure 1 (f) Figure 2 ((1) Multiple cases 2 Figure (b) 2nd stroke (C) ;-1 3 @(dn*tshi 4 ('ff1 (αn) Figure 4 (shi) B4λ and Figure 5 beak 5 6 Figure (α) Figure 6 Cb)

Claims (1)

[Scope of Claims] (1) A semiconductor substrate having an insulating film formed on its surface; A shield fixed at a potential, a source and drain region formed on the semiconductor substrate, sandwiched between these regions, the impurity concentration of which is equal to the impurity concentration of the semiconductor substrate region directly below where the shield is formed. have different channel regions, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, and the first and second gate electrodes are formed such that the shield is disposed therebetween. 2. A semiconductor device comprising: 2 MOS type transistors. (2) The semiconductor device according to claim 1, wherein the insulating film directly under the shield is thicker than the gate insulating film of the transistor. (3) a semiconductor substrate having an insulating film formed on its surface; and a shield formed on the semiconductor substrate via the insulating film formed on the surface of the semiconductor substrate and fixed to the same potential as the semiconductor substrate. and a source and drain region formed on the semiconductor substrate, a channel region sandwiched between these regions, and a gate insulating film formed on the channel region and whose film thickness is thinner than the film thickness of the insulating film directly under the shield. and a gate electrode formed on the gate insulating film, and first and second MOS transistors formed such that the shield is disposed therebetween. Device. (4) The semiconductor device according to claim 1 or 3, wherein the drain regions of the first and second MOS transistors have an LDD structure. (5) A step of introducing an impurity into a region where a transistor is to be formed of a semiconductor substrate having an insulating film formed on its main surface, and introducing an impurity into a region where a shield is to be formed of the semiconductor substrate at a concentration different from the impurity concentration in the previous step. forming a shield fixed to the same potential as the semiconductor substrate via an insulating film formed on the main surface of the semiconductor substrate; , the drain region, sandwiched between these regions,
A channel region whose impurity concentration is different from the impurity concentration of the semiconductor substrate region immediately below where the shield is formed, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film. 1. A method of manufacturing a semiconductor device, comprising: forming first and second MOS transistors each having a structure such that a shield on the semiconductor substrate is disposed between the first and second MOS transistors. (6) The method of manufacturing a semiconductor device according to claim 5, wherein the gate electrode and the shield use the same material.