JPH04189005A - Pwm amplifier - Google Patents

Abstract

PURPOSE:To reduce the signal distortion when the PWM amplifier is used for amplifying an audio signal especially by selecting a proper simultaneous OFF period at an output stage so as to keep a high efficiency and a stable operation and cancelling the distortion generated in the output stage through the use of a sound signal deformed in advance. CONSTITUTION:An operational amplifier IC3 forms an adder adding an input signal from an input terminal 100 and a distortion compensation voltage given to an output of an operational amplifier IC2 and an operational amplifier IC4 amplifies the output inversely and gives the result to an output terminal 101. When an output of the operational amplifier IC2 is zero, that is, the output is at a ground level, the input output characteristic of a distortion compensation circuit 8 is linear. A transistor(TR) Q101 acts like a 1st switching means to interrupt the input to the amplifier IC. when an input signal voltage from the terminal 100 is lower than Vb1+Vth1 and a TR Q102 acts like a 2nd switching means to interrupt the input to the amplifier IC1 when the input signal voltage from the terminal 100 is higher than -Vb1-Vth2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a circuit configuration of a PWM amplifier, and particularly to reducing signal distortion when used for amplifying audio signals.

[Conventional technology]

FIG. 5 is a block diagram of a conventional PWM amplifier disclosed in, for example, Japanese Patent Publication No. 62-22484, where l is P
WM modulator, 2 is driver, 3 is MO3FET on positive power supply side
, 4 is a MO3FET on the 1jitlI side, 5 is a coil, 6 is a capacitor, and 7 is a load. In addition, MOSFET3.
4 is a diode that exists parasitically due to its structure, Dl,
For convenience of explanation, it is shown as Dz.

In the configuration shown in Figure 5, the analog audio signal is
A WM modulator 1 generates a PWM signal, which is amplified by a driver 2, and a pair of switching elements MOSFET 3.
After driving 4 and amplifying the power, coil 5 and capacitor 6
The carrier wave component is removed by a low-pass filter composed of , and only the audio signal is supplied to a load 7 such as a speaker.

Here, MOSFET3.4 performs push-pull operation,
Turns on alternately by PWM signal. At this time, generally M
To avoid OSFET3.4 from turning on at the same time,
After one MOSFET turns off, the other MOSFET
There is an appropriate amount of time before the ET turns on (ie, a period during which both MOSFETs are considered to be off).

The driver 2
Timing of a pair of outputs is performed.

Further, the load for the switching operation of MOSFET 3.4 is usually dominated by the inductivity of coil 5.

Hereinafter, the causes of distortion caused by the output switching operation of this type of PWM amplifier will be explained with reference to the drawings.

FIG. 6 shows the output switching operation waveform when the duty ratio of the PWM signal is approximately 50%, that is, the output voltage to the load 7 is approximately 0. ■. is the voltage at the connection point of MOSFET 3.4, Io is the current in the coil 5, and the direction flowing from this connection point into the coil 5 is positive. In addition, Tel is the simultaneous off period from when MOSFET4 turns off until MOSFET3 turns on, and T + , T
z is the ON period of MOSFET 3゜4, Toz is the MOSFET
This is the simultaneous off period from when ET3 is turned off until MOSFET4 is turned on. Immediately before entering the simultaneous off period Tel, the coil current 1 a changes from the coil 5 to the MOSFET 4.
It flows out to the negative '@is Vcc through the MOS
When FET4 turns off, Va becomes V(c+Va+(■a+
is the forward voltage drop of the parasitic diode D of MOSFET 3), and the coil current I0 flows through the parasitic diode D toward the positive power supply. Next, when MOSFET3 is turned on, 1° begins to flow through it, and the MOSFET3 turns on.
V if the on-resistance of SFET3 is sufficiently low. is almost VCC
becomes. Tel and T+ period V.

is almost ■. , so ■. increases linearly as shown in the figure, and finally from MOSFET 3 to coil 5
It starts to flow into. Next, when MOSFET3 turns off and enters period T02, ■.

becomes -Vcc Vat (Vd2 is the forward voltage drop of the parasitic diode D2 of MOSFET 4), and I.

flows from the negative supply via D2. Next, MOSFET
When 4 turns on, 10 will flow through it,
■ If the on-resistance of MOSFET4 is sufficiently low. is almost-
It becomes VCC. T oz and T2 period, ■. is almost -
Since the voltage becomes VCC, Io decreases linearly as shown in the figure, and finally begins to flow from the coil 5 to the MOSFET 4.

In this way, the simultaneous off periods Tel and Ta2 belong to the positive period and negative period of the output voltage v0, respectively, and their effects on amplification cancel each other out. Note that Ql and Q2 are the symbols assigned to MO3FET3.4 for convenience of explanation.

FIG. 7 shows the switching operation waveform when the duty ratio of the PWM signal is small and the output voltage to the load 7 is negative.
Current■. is negative throughout the entire period, that is, in the direction of flowing out from the coil 5. For each period, the period Te
The current flows to the positive power supply through the parasitic diode D1 of MOSFET 3 in l, and the flow also flows towards the positive power supply through MOSFET 3 between TIM, and again to the positive power supply through Dl during the Tox period. During the T2 period, the current flows toward the negative power supply via MOSFET4. In this way, the simultaneous off period T01°Tel is both at the output voltage ■. Since it belongs to the regular period of , the duty ratio of vo is slightly larger than that of the PWM signal.

FIG. 8 shows switching operation waveforms when the duty ratio of the PWM signal is large (and the output voltage to the load 7 is positive).

The current I0 is positive throughout the period, i.e. MOSFET 3.4
This is the direction from which it flows into the coil 5. Regarding each period, during the T O1 period, it flows from the negative power supply via the parasitic diode Da of MOSFET4, between 71'#JI, it flows from the positive power supply via MOSFET3, and during the Tax period, it flows again through D2. It flows from the negative power supply, and also flows from the negative power supply to the coil 5 via the MOSFET 4 during the T2 period. In this way, the simultaneous off period T. I.

Since both TD2 belong to the negative period of the output voltage v0, the duty ratio of Vo is slightly smaller than that of the PWM signal.

FIG. 9 shows the relationship between the duty ratio of the input PWM signal and the duty ratio of the output PWM signal in the output stage operation described above. In the figure, points a and b are thresholds at which the current in the coil 5 becomes positive or negative throughout one cycle of the PWM modulated wave, as described above. Here, assuming that the resistance value of the load 7 is R3, its terminal voltage is 1, and the current flowing through the load 7 is 11, the duty ratio of the PWM wave corresponding to each point can be determined by the following calculation.

However, V,,1. Assume that the ripple is negligible due to the action of the capacitor 6. First, consider point a.

The amount of change dr in the current I0 flowing through the coil 5. is dlo=(Vcc-V+), Tz/L (1
) Here, T is approximately the period during which the MOS FET 3 is on, and L is the inductance of the coil 5.

At point a, the current I0 increases approximately linearly from zero to dl.

Since the load current ■1 will be the average value, r, -(VCC-V,)-T,, /2L (
2) On the other hand, this load current I, is 11 = V I / RI
The relationship (3) must be satisfied, and furthermore, V+-(Tz Tit)'Vcc/(Tz Tit
) The relationship (4) holds true. , T21 is almost MOS
This is the period during which FET4 is turned on. From formulas (2) to (4), R1・T l l・T, , = L, (T, , −T, l)
The relationship (5) is obtained. Here, T =
T, , + Tt, and setting D3=T, , /T, the following relationship is obtained for the duty ratio of the PWM wave at point a.

On the other hand, the duty ratio of the PWM wave at point b is D4
Since it is clear that =I D2, (6)
The relationship can be obtained from Eq.

From the above, the signal distortion of PWM amplifiers is related to the simultaneous OFF period of the output stage switch elements, and it is important to shorten and ideally eliminate this simultaneous OFF period in order to reduce signal distortion. is clear. However, since there is always a time delay in the actual on/off operation of a switch element, if you try to shorten this simultaneous off period, the on/off transition regions of the switch elements on the positive power supply side and the negative power supply side will overlap, causing both A through current flows through the switch element. Since all of this through current becomes a loss, it not only impairs the high efficiency feature of the PWM amplifier, but also causes waveform disturbances such as overshoot and ringing in the output waveform because it is a sharp pulse current. This results in an increase in output distortion. Further, since the loss due to this through current mainly occurs in the output inch element, it is necessary to take measures such as heat dissipation from the element. Furthermore, if this simultaneous off period is shortened, the through current will change significantly due to slight changes in operating conditions due to temperature characteristics of circuit elements or changes over time, making it difficult to stably manage the characteristics of the amplifier. It's getting difficult.

Because of these many problems, actual PWM amplifiers are provided with a simultaneous OFF period to the extent that this through current does not flow.

[Problem to be solved by the invention]

As described above, in conventional PWM amplifiers, in order to maintain stable operation and obtain high efficiency, both elements are turned off when switching the operation of the switching elements on the positive power supply side and the negative TFI side in the operation of the output stage. There was a problem in that this period caused distortion in the output signal.

The present invention has been made to solve the above-mentioned problems, and aims to provide a PWM amplifier that operates stably, has high efficiency, and has low signal distortion.

[Means to solve the problem]

The PWM amplifier according to the present invention has inflection points at two points, positive and negative, with respect to the average level of an input audio signal, and a positive signal exceeding the inflection point level on the positive side and an inflection point level on the negative side. A distortion compensation circuit is provided which provides a substantially constant Bell deformation for negative signals below the .

[For production]

The distortion compensation circuit according to the present invention applies a modification to an input audio signal so that the distortion generated at the output stage of the amplifier is canceled out by this modification.

[Embodiment] Hereinafter, in Fig. 0, which describes an embodiment of the present invention with reference to the drawings, 1 is a PWM modulator, 2 is a driver, 3 is a positive power supply side MOSFET (also referred to as Q 1), 4
is a negative power supply side MO3FET (referred to as Qz), 5 is a coil, 6 is a capacitor, 7 is a load, 8 is a distortion compensation circuit, and the parts indicated by symbols 1 to 7 are the same as the conventional one and operate in the same way. . The distortion compensation circuit 8 cancels the distortion generated at the output stage by modifying the audio signal in advance. The characteristics necessary for this distortion cancellation are those shown in FIG. 2, which compensate for the input/output characteristics regarding the duty ratio of the output stage PWM signal shown in FIG. In Fig. 2, input and output are expressed by the voltage of the audio signal, but this can be made to correspond completely to the duty ratio of the PWM signal by multiplying each voltage by the modulation gain of the PWM modulator 1.
There is no problem.The inflection points of point 0 and point d in Figure 2 correspond to points a and b in Figure 9, respectively, and the deviation from the straight line beyond the inflection points c and d. is in the opposite direction and has the same magnitude as the duty ratio shift in FIG.

FIG. 3 shows a circuit diagram of the distortion compensation circuit 8, in which the operational amplifier Ic
y is the input signal from the input terminal 100 and the operational amplifier IC1
It constitutes an adder that adds and synthesizes the distortion compensation voltages given to the outputs of the operational amplifier IC.

inverts and amplifies this output and supplies it to the output terminal 101. When the output of the operational amplifier ICz is zero (ground potential), the input/output characteristic of the distortion compensation circuit 8 becomes a straight line. Here, the transistor Q lo + operates as a first switching means to cut off the input to the operational amplifier IC when the input signal voltage from the input terminal 100 is lower than Vb++Vth+, and the transistor Q lo + operates as a first switching means to cut off the input to the operational amplifier IC. 2 is input terminal 100
When the input signal voltage from the circuit is higher than -V, -V, it operates as a second switch means to cut off the input to the operational amplifier IC. V bl and V bt are the base voltages of the transistor Q + O + + Q + 112, and I + V2 is the threshold voltage.

As a result, the input signal voltage from input terminal]0[) is V,
, 10 V, lower and -V bl V tk! If it is higher, the input to the operational amplifier IC, will be cut off and its output will be zero. Since the operational amplifier ICz is simply an inverting amplifier, its output is also zero.

Next, the input signal voltage of the input terminal 100 is set to ■1. ＋■I,
When higher and transistor Q + 61 conducts,
The operational amplifier IC, operates as an inverting amplifier with a gain of -R, /R, and outputs a negative output, but when this output voltage becomes lower than -1, the transistor Q104
Since V is conductive, the gain is suppressed and the output voltage is limited to approximately this value V b a V . Therefore, transistor Q1.4 operates as a first amplitude limiting means. Also, when the input signal voltage is lower than -V4z Vth2 and the transistor Q + oz becomes conductive, the operational amplifier IC operates as an inverting amplifier with a gain of -Rs/R4 and outputs a positive output. ,,10V
When the voltage becomes higher, the transistor Q1 becomes conductive, so the gain is suppressed and the output voltage becomes approximately this value Vbs+Vt.
limited to hz. Therefore, transistor Q1° operates as second amplitude limiting means. Since the operational amplifier ICz inverts and amplifies the output of the operational amplifier IC obtained as described above, the output from the operational amplifier ICz becomes as shown in FIG. In addition, ■1. .

■1 is the base voltage of transistor Q1゜3 + Qloa, ■i, 2 is the threshold voltage, R,
-R,.

is a resistor, and C1 to C4 are capacitors. The output of the operational amplifier 1c2 shown in FIG. 4 is added to the input signal by the operational amplifier IC3, and after being inverted by the operational amplifier
11, the input/output characteristics of the distortion compensation circuit 8 are in phase with the characteristics shown in FIG. 2, and the base voltage Vbl~
■By appropriately setting the value of 14 and the level of the distortion compensation signal added by operational amplifier IC3, the inflection points c and d can be adjusted.
, the amount of deviation from the straight line above the positive inflection point C, and below the negative inflection point d can be made to match the desirable characteristics shown in FIG. Therefore, by providing the distortion compensation circuit 8, it is possible to reduce the distortion factor while providing an appropriate simultaneous off period in the output stage.

Note that in the above embodiment, MO is used as the output switching element.
3FET3.4 was used, but a transistor with a flywheeling diode connected in parallel or an IGBT
(Insulated-gate Bipolar T
The same effect can be obtained with other switch elements such as a transistor (transistor). Also, the output stage format is S E P
P (Single-ended Pu5h-pul
l ), but 5 gives audio outputs with opposite phases, respectively.
BTL (Balanc) using two sets of EPP output stages
edTransformer Less) output format.

〔Effect of the invention〕

As described above, according to the present invention, an appropriate simultaneous off period is taken in the output stage to maintain high efficiency and stable operation, and distortion generated in the output stage can be canceled by transforming the audio signal in advance. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PWM amplifier according to the present invention, FIGS. 2 and 3 are input/output characteristic diagrams and circuit diagrams of a distortion compensation circuit according to the present invention, and FIG. 4 is a distortion compensation signal in the distortion compensation circuit according to the present invention. , Figure 5 is a configuration diagram of a conventional PWM amplifier, Figures 6 to 8 are operating waveform diagrams with different duty ratios of PWM signals in a conventional PWM amplifier, and Figure 9 is an output of a conventional PWM amplifier. FIG. ■...PWM modulator, 3.4...MOS FET
, 5... Coil, 6... Capacitor, 7... Load, 8... Distortion compensation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 4 Figure 5 VCC Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] It has inflection points at two points, positive and negative, with respect to the average level of the input audio signal, and for positive signals exceeding the positive inflection point level and negative signals below the negative inflection point level. A distortion compensation circuit that gives deformation at a substantially constant level, a PWM modulator that converts the output of the distortion compensation circuit into a PWM signal, and this PWM signal.
A PWM characterized by comprising an output switching element for power amplifying the M signal, and a low-pass filter that removes a carrier wave component from the output of the output switching element and supplies it to a load.
amplifier.