JP4744686B2

JP4744686B2 - Operational amplifier

Info

Publication number: JP4744686B2
Application number: JP2000371904A
Authority: JP
Inventors: 文彦加藤
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2000-12-06
Filing date: 2000-12-06
Publication date: 2011-08-10
Anticipated expiration: 2020-12-06
Also published as: US6424219B1; US20020067207A1; JP2002175052A

Description

【０００１】
【発明の属する技術分野】
本発明は液晶パネル駆動装置に関し、特に入力信号を演算増幅する演算増幅器及びそれを用いた液晶パネル駆動用回路に関する。
【０００２】
【従来の技術】
一般に、液晶パネルは、毎秒数十フレーム（数十枚）の書き込みを行う必要がある。このため、液晶パネル駆動用回路からの出力信号は、液晶パネルの対向電極の電位に対し、走査ライン毎あるいはフレーム毎に交流駆動を行っている。この液晶パネルの対向電極の電位に対し交流駆動を行う液晶パネル駆動用演算増幅器及び液晶パネル駆動用回路について、図７及び図８を参照して説明する。
【０００３】
図７は従来の液晶パネル駆動用演算増幅器の一例を示す構成図である。図７に示すように、従来の液晶パネル駆動用演算増幅器１ａは、高位側電源（ＶＤＤ）８および低位側電源（ＶＳＳ）９間に接続され、それぞれ正入力端子ＶＩ１と負入力端子ＶＩ２ならびに正入力端子ＶＩ３と負入力端子ＶＩ４に供給されるアナログ入力の差電圧を増幅し差動型入力段出力端子１０１，１０２へ出力する差動型入力段回路２，３と、同様に高位側電源８および低位側電源９間に一方を接続され且つ他方を演算増幅器１ａの出力端子ＶＯ１，ＶＯ２にそれぞれ接続する出力段ＦＥＴ１１，１２およびＦＥＴ１３，１４と、同様に高位側電源８および低位側電源９間に接続され、出力端子１０１，１０２からの差動出力に基いてそれぞれ出力段ＦＥＴ１１，１２およびＦＥＴ１３，１４への駆動出力を出力端子１０５，１０６ならびに１０７，１０８を介して供給する駆動段回路４，５とを有しており、機能的には出力インピーダンスの変換回路として用いられる。
【０００４】
この液晶パネル駆動用演算増幅器１ａの差動型入力段回路２，３は、入力レンジが低位側電源レベル（ＶＳＳ）から高位側電源レベル（ＶＤＤ）まで確保することができる。また、出力段ＦＥＴ１１は、ゲート電極が駆動段回路４の出力端子ＶＯ１に接続され、ソース電極とドレイン電極とがそれぞれ高位側電源８と出力端子ＶＯ１に接続される。出力段ＦＥＴ１３も駆動段回路５と出力端子ＶＯ２に同様に接続される。さらに、出力段ＦＥＴ１２，１４は低位側電源９と出力端子ＶＯ２に接続される。
【０００５】
図８は従来の演算増幅器を使用した液晶パネル駆動用回路の一例を示す構成図である。図８に示すように、かかる液晶パネル駆動用回路４０ａは、正極側入力および負極側入力のディジタルデータをそれぞれＤ／Ａ変換する正側Ｄ／Ａコンバータ４１および負側Ｄ／Ａコンバータ４２と、これらのＤ／Ａコンバータ４１，４２の変換出力を外部からの制御入力によりスイッチングするスイッチ手段４３，４４と、これらスイッチ手段４３，４４で切替られた出力を演算増幅する上述（図７）の演算増幅器１ａと、この演算増幅器１ａの出力ＶＯ１，ＶＯ２を外部からの制御入力によりスイッチングして出力端子ＯＵＴ１，ＯＵＴ２に供給するスイッチ手段４７，４８とを有している。
【０００６】
これらＤ／Ａコンバータ４１，４２は、それぞれ入力されるデジタルデータに応じて、中間電位から高位側電源および中間電位から低位側電源のアナログデータに変換する。また、各スイッチ手段４３，４４，４７，４８は、相反する動作を行う一対のスイッチＳおよびＳｂから構成される。さらに、演算増幅器１ａは信号の負帰還を行っており、各出力ＶＯ１，ＶＯ２が正側入力ＶＩ１，ＶＩ３に対する負側入力ＶＩ２，ＶＩ４にフィードバックされる。
【０００７】
かかる液晶パネル駆動用回路４０ａの動作は、まずスイッチ手段４３，４４，４７，４８における各スイッチＳがＯＮ（このとき、スイッチＳｂはＯＦＦ）の時、正極側Ｄ／Ａコンバータ４１から出力されたアナログ信号及び負極側Ｄ／Ａコンバータ４２から出力されたアナログ信号がそれぞれ演算増幅器１ａに入力され、それぞれがインピーダンス変換され、出力信号として、スイッチ手段４７または４８を介し出力端子ＯＵＴ１またはＯＵＴ２に出力される。なお、液晶パネル駆動用回路４０ａの出力は、パネルの各素子を駆動するために多数個設けられるが、説明を簡略化するために、便宜的に２個で説明している。
【０００８】
また、スイッチ手段４３，４４，４７，４８における各スイッチＳｂがＯＮ（このとき、スイッチＳはＯＦＦ）の時も同様であり、正極側Ｄ／Ａコンバータ４１で選択されたアナログ信号はインピーダンス変換され、出力端子ＯＵＴ２に、また負極側Ｄ／Ａコンバータ４２で選択されたアナログ信号もインピーダンス変換され、出力端子ＯＵＴ１にそれぞれ出力される。
【０００９】
この液晶パネル駆動用回路４０ａは、数十回正極側または負極側のアナログ信号を出力、すなわちパネルに対して書き込みを行う。走査ラインが切り替われば、正極側を出力していた端子と負極側を出力していた端子とを入れ替えることにより、交流駆動を行う。
【００１０】
図９は従来の液晶パネル駆動用回路の出力波形のタイミング図である。図９に示すように、スイッチＳ，Ｓｂが相反する切替動作を行うと、出力端子ＯＵＴ１，ＯＵＴ２に出力される液晶パネル充放電のための信号波形は、高位側電源電圧ＶＤＤから低位側電源電圧ＶＳＳに、また低位側電源電圧ＶＳＳから高位側電源電圧ＶＤＤに変化する。
【００１１】
【発明が解決しようとする課題】
上述した液晶パネルは容量性の負荷である。このため、入力するアナログ信号の変化によって液晶パネルを駆動することは、液晶パネルの容量性負荷を充放電することである。
【００１２】
また、液晶パネル駆動用回路は、前述したように、正極側あるいは負極側電圧を数十回出力した後、出力極性を入れ替えて負極側あるいは正極側電圧を数十回出力し、その繰り返し動作を行う。
【００１３】
かかる容量性負荷の充放電は、高位側電源と低位側電源の間で行われるため、高位側電源と低位側電源との電位差をＶＤＤ、書き込み振幅をＶｐｐ、書き込み周波数をｆ（Ｈｚ）、液晶パネルの容量性負荷の容量値をＣとすると、１出力あたりの消費電力Ｐは、次の式で表わすことができる。
【００１４】
Ｐ＝Ｃ×ｆ×Ｖｐｐ×ＶＤＤ
しかるに、上述した従来の演算増幅器及びそれを用いた液晶パネル用駆動回路は、正極性側あるいは負極性側出力電圧だけを数十回書き込むにも拘わらず、高位側電源と低位側電源との電位差がＶＤＤ（ＶＳＳを０Ｖとしたとき）であるために、消費電力Ｐが大きくなってしますという問題がある。
【００１５】
また、液晶パネルの交流駆動を行う際には、液晶パネルの表示ムラを極力抑制する必要がある。
【００１６】
本発明の目的は、液晶パネルの交流駆動を行う際に消費されるパネル負荷充放電電力を削減するとともに、交流駆動を行う際に発生する液晶パネルの表示ムラを極力抑制することのできる演算増幅器及びそれを用いた液晶パネル駆動用回路を提供することにある。
【００１７】
【課題を解決するための手段】
本発明は、消費電力を小さくすると同時に、交流駆動を行う際に発生する液晶パネルの表示ムラを従来例と同様に極力抑制するものであり、その解決手段として、高位側電源，低位側電源の他に、中位側電源およびスイッチ手段を設けたことにある。特に、最終的に出力するトランジスタ段についてみると、正極側を駆動する出力トランジスタ段を高位側電源と中位側電源の間に接続し且つ負極側を駆動する出力トランジスタ段を中位側電源と低位側電源の間に接続する。
【００１８】
かかる手段を使用することにより、充放電は高位側電源から中位側電源の間または中位側電源から低位側電源の間で行われ、高位側電源と中位側電源との電位差または中位側電源と低位側電源との電位差をＶＤＤ／２、書き込み振幅をＶｐｐ、書き込み周波数をｆ（Ｈｚ）、液晶パネルの容量性負荷の容量値をＣとすると、１出力あたりの消費電力Ｐは、つぎの式で表わすことができる。
【００１９】
Ｐ＝Ｃ×ｆ×Ｖｐｐ×（ＶＤＤ／２）
また、本発明は、正極側書き込み時に使用する差動型入力段回路と負極側書き込み時に使用する差動型入力段回路とを同一とすることにより、交流駆動を行う際に発生する液晶パネルの表示ムラを極力抑制することができる。
【００２０】
【発明の実施の形態】
以下、図面を参照し、本発明の演算増幅器及びそれを用いた液晶パネル駆動用回路の実施形態について説明する。
【００２１】
図１は本発明の一実施形態を示すパネル駆動用演算増幅器の構成図である。図１に示すように、本実施の形態における液晶パネル駆動用演算増幅器１は、高位側電源（ＶＤＤ）８および低位側電源（ＶＳＳ）９間に接続され、それぞれ正入力端子ＶＩ１と負入力端子ＶＩ２ならびに正入力端子ＶＩ３と負入力端子ＶＩ４に供給されるアナログ入力の差電圧を増幅し差動型入力段出力端子１０１，１０２へ出力する差動型入力段回路２，３と、高位側（ＶＤＤ）電源８および中位側（ＶＤＤ／２）電源１０間に直列に接続され且つそれらの接続点に出力端子ＶＯ１を接続した出力段ＦＥＴ１１，１２と、中位側（ＶＤＤ／２）電源１０および低位側（ＶＳＳ）電源９間に直列に接続され且つそれらの接続点に出力端子ＶＯ２を接続した出力段ＦＥＴ１３，１４と、差動入力段出力１０１，１０２および駆動段入力１０３，１０４間に接続されるとともに、外部から供給される所定の制御信号によってオン・オフを制御され且つ互いに相反する動作をするスイッチＳ１，Ｓ１ｂおよびスイッチＳ２ｂ，Ｓ２からなるスイッチ手段６，７と、高位側電源８および低位側電源９間に接続され、入力端子１０３，１０４からの信号に基いてそれぞれ出力段ＦＥＴ１１，１２およびＦＥＴ１３，１４への駆動出力を出力端子１０５，１０６ならびに１０７，１０８を介して供給する駆動段回路４，５とを有しており、機能的には出力インピーダンスの変換回路として用いられる。なお、これら差動型入力段回路２，３は入力レンジが低位側電源レベル（ＶＳＳ）から高位側電源レベル（ＶＤＤ）まで確保できる。
【００２２】
このパネル駆動用演算増幅器１は、スイッチ手段６，７と中位側電源１０を追加したことにあり、スイッチ手段６，７はその構成スイッチＳ１，Ｓ２が同相でオン・オフし、またこれらのスイッチＳ１，Ｓ２とは逆相でオフ・オンするスイッチＳ１ｂ，Ｓ２ｂが同相でオン・オフする。さらに、中位側電源１０を設けることにより、出力端子ＶＯ１，ＶＯ２における出力電圧の立ち上げを高速化し、パネル負荷充放電電力を削減するとともに、交流駆動を行う際に発生する液晶パネルの表示ムラを抑制している。
【００２３】
図２は図１における演算増幅器の駆動段回路の第１の例を示す詳細図である。図２に示すように、演算増幅器における駆動段回路４は、ゲート電極が入力端子１０３に接続され、ソース電極が低位側電源９（ＶＳＳ）に接続されたＦＥＴ１５と、ゲート電極とドレイン電極とがＦＥＴ１５のドレイン電極に接続され、ソース電極が高位側電源８（ＶＤＤ）に接続されたＦＥＴ１６と、ゲート電極がＦＥＴ１５のドレイン電極とＦＥＴ１６のゲート，ドレイン電極に接続され、ソース電極が高位側電源８に接続されたＦＥＴ１７と、ゲート，ドレイン電極が出力端子１０５に接続され、ソース電極がＦＥＴ１７のドレイン電極に接続されたＦＥＴ１８と、ゲート電極がＦＥＴ１５のドレイン電極とＦＥＴ１６のゲート，ドレイン電極とＦＥＴ１７のゲート電極に接続され且つソース電極が高位側電源８に接続され、ドレイン電極が出力端子１０６に接続されたＦＥＴ１９と、一端をＦＥＴ１８のゲート，レイン電極及び出力端子１０５に接続され、他端を低位側電源９に接続された定電流源Ｉ１と、一端をＦＥＴ１９のドレイン電極及び出力端子１０６に接続され、他端を低位側電源９に接続された定電流源Ｉ２とで構成される。
【００２４】
同様に、駆動段回路５は、ゲート電極が入力端子１０４に接続され、ソース電極が低位側電源９に接続されたＦＥＴ２０と、ゲート電極とドレイン電極とがＦＥＴ２０のドレイン電極に接続され、ソース電極が高位側電源８に接続されたＦＥＴ２１と、ゲート電極がＦＥＴ２０のドレイン電極とＦＥＴ２１のゲート，ドレイン電極に接続され、ソース電極が高位側電源８に接続されたＦＥＴ２２と、ゲート，ドレイン電極が出力端子１０８及びＦＥＴ２２のドレイン電極に接続されたＦＥＴ２３と、ゲート電極がＦＥＴ２０のドレイン電極とＦＥＴ２１のゲート，ドレイン電極とＦＥＴ２２のゲート電極に接続され且つソース電極が高位側電源８に接続され、ドレイン電極が出力端子１０７に接続されたＦＥＴ２４と、一端をＦＥＴ２３のソース電極に接続され、他端を低位側電源９に接続された定電流源Ｉ３と、一端をＦＥＴ２４のドレイン電極及び出力端子１０７に接続され、他端を低位側電源９に接続された定電流源Ｉ４とで構成される。
【００２５】
これら駆動段回路４，５の動作は、前述した差動型入力段回路２，３からの出力信号１０１，１０２をスイッチ手段６，７によって切換えられた入力１０３，１０４が供給されると、その信号を駆動段回路４，５内で変換し、最終の出力ＦＥＴ１１，１２および出力ＦＥＴ１３，１４への出力信号１０５，１０６および１０７，１０８として伝達される。
【００２６】
例えば、差動型入力段回路２または３の正入力端子ＶＩ１，負入力端子ＶＩ２または正入力端子ＶＩ３，負入力端子ＶＩ４において、負入力端子ＶＩ２、ＶＩ４の電位レベルに比べ、正入力端子ＶＩ１，ＶＩ３の電位レベルが大きくなった場合、それぞれの差動型入力段回路２，３の出力信号１０１，１０２は、立ち下がりの信号になる。その信号は、駆動段回路４，５内で変換され、最終段の出力ＦＥＴ１１，１２および１３，１４への立ち下がり信号として出力される。すると、最終段の出力ＦＥＴ１１，１２および１３，１４は、それぞれＦＥＴ１１と１３が低抵抗、ＦＥＴ１２，１４が高抵抗となり、負荷に対しての充電信号として出力される。
【００２７】
同様に、差動型入力段回路２または３の正入力端子ＶＩ１，負入力端子ＶＩ２または正入力端子ＶＩ３，負入力端子ＶＩ４において、負入力端子ＶＩ２，ＶＩ４の電位レベルに比べ、正入力端子ＶＩ１，ＶＩ３の電位レベルが小さくなった場合、それぞれの差動型入力段回路２，３の出力信号１０１，１０２は、立ち上がりの信号になる。その信号は、駆動段回路４，５内で変換され、最終段の出力ＦＥＴ１１，１２および１３，１４への立ち上がり信号として出力される。すると、最終段の出力ＦＥＴ１１，１２および１３，１４は、それぞれＦＥＴ１１と１３が高抵抗、ＦＥＴ１２，１４が低抵抗となり、負荷に対しての放電信号として出力される。
【００２８】
従って、これらの駆動段回路４，５を使用すれば、負荷に対するプッシュープル動作が可能である。
【００２９】
また、かかる駆動段回路４，５を使用すると、最終段の出力ＦＥＴ１２および１３のソース電極電位がバックゲート電極電位に対して浮いていたとしても、動作的に支障がない。その理由は、最終段の出力ＦＥＴ１１，１２またはＦＥＴ１３，１４それぞれに流れる定常電流は、駆動段回路４，５内のＦＥＴ１８，２３とカレントミラーを構成されている出力段ＦＥＴ１１，１４で決定されるからである。その場合、出力段ＦＥＴ１２，１３のソース電極電位がバックゲート電極電位に対し浮いたとしても、問題は生じない。
【００３０】
図３は図１における演算増幅器の駆動段回路の第２の例を示す詳細図である。図３に示すように、演算増幅器における駆動段回路４は、ゲート電極が入力端子１０３に接続され、ソース電極が低位側電源９（ＶＳＳ）に接続されたＦＥＴ２５と、ゲート電極とドレイン電極とがＦＥＴ２５のドレイン電極に接続され、ソース電極が低位側電源９に接続されたＦＥＴ２６と、ゲート電極がＦＥＴ２５のドレイン電極とＦＥＴ２６のゲート，ドレイン電極に接続され、ソース電極が低位側電源９に接続されたＦＥＴ２７と、ゲート，ドレイン電極がＦＥＴ２７のドレイン電極及び出力端子１０５に接続されたＦＥＴ２８と、ゲート電極がＦＥＴ２５のドレイン電極とＦＥＴ２６のゲート，ドレイン電極とＦＥＴ２７のゲート電極に接続され且つソース電極が低位側電源９に接続され、ドレイン電極が出力端子１０６に接続されたＦＥＴ２９と、一端をＦＥＴ２５のドレイン電極とＦＥＴ２６のゲート，ドレイン電極とＦＥＴ２７及びＦＥＴ２９のゲート電極に接続され、他端を高位側電源８に接続された定電流源Ｉ５と、一端をＦＥＴ２８のソース電極に接続され、他端を高位側電源８に接続された定電流源Ｉ６と、一端をＦＥＴ２９のドレイン電極及び出力端子１０６に接続された定電流源Ｉ７とで構成される。
【００３１】
同様に、駆動段回路５は、ゲート電極が入力端子１０４に接続され、ソース電極が低位側電源９に接続されたＦＥＴ３０と、ゲート電極とドレイン電極とがＦＥＴ３０のドレイン電極に接続され、ソース電極が低位側電源９に接続されたＦＥＴ３１と、ゲート電極がＦＥＴ３０のドレイン電極とＦＥＴ３１のゲート，ドレイン電極に接続され、ソース電極が低位側電源９に接続されたＦＥＴ３２と、ゲート，ドレイン電極が出力端子１０８に接続され、ソース電極がＦＥＴ３２のドレイン電極に接続されたＦＥＴ３３と、ゲート電極がＦＥＴ３０のドレイン電極とＦＥＴ３１のゲート，ドレイン電極とＦＥＴ３２のゲート電極に接続され且つソース電極が低位側電源９に接続され、ドレイン電極が出力端子１０７に接続されたＦＥＴ３４と、一端をＦＥＴ３０のドレイン電極とＦＥＴ３１のゲート，ドレイン電極とＦＥＴ３２及びＦＥＴ３４のゲート電極に接続され、他端を高位側電源８に接続された定電流源Ｉ８と、一端をＦＥＴ３３のゲート，ドレイン電極及び出力端子１０８に接続され、他端を高位側電源８に接続された定電流源Ｉ９と、一端をＦＥＴ３４のドレイン電極及び出力端子１０７に接続された定電流源Ｉ１０とで構成される。
【００３２】
この場合の駆動段回路４，５の動作は、前述した図２の第１の例と同様であるので、説明は省略する。
【００３３】
図４は図１における演算増幅器の駆動段回路の第３の例を示す詳細図である。図４に示すように、この場合の演算増幅器における駆動段回路は、前述した図３の第２の例における駆動段回路４と、前述した図２の第１の例における駆動段回路５とを組合わせたものである。
【００３４】
すなわち、駆動段回路４は、ゲート電極を入力端子１０３に且つソース電極を低位側電源９に接続したＦＥＴ５５と、ゲート，ドレイン電極をＦＥＴ２５のドレイン電極に且つソース電極を低位側電源９に接続したＦＥＴ２６と、ゲート電極をＦＥＴ２６のゲート電極に接続し、ソース電極を低位側電源９に接続したＦＥＴ２７と、ゲート，ドレイン電極をＦＥＴ２７のドレイン電極及び出力端１０５に接続したＦＥＴ２８と、ゲート電極をＦＥＴ２７のゲーの電極に且つソース電極を低位側電源９に接続し、ドレイン電極を出力端１０６に接続したＦＥＴ２９と、ＦＥＴ２５のドレイン電極と高位側電源８間に接続した定電流源Ｉ５と、ＦＥＴ２８のソース電極と高位側電源８間に接続した定電流源Ｉ６と、出力端１０６と高位側電源８間に接続した定電流源Ｉ７とで構成する。
【００３５】
一方、駆動段回路５は、ゲート電極を入力端子１０４に接続し、ソース電極を低位側電源９に接続したＦＥＴ２０と、ゲート，ドレイン電極をＦＥＴ２０のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴ２１と、ゲート電極をＦＥＴ２１のゲート電極と接続し、ソース電極を高位側電源８に接続したＦＥＴ２２と、ゲート，ドレイン電極をＦＥＴ２２のドレイン電極及び出力端１０８に接続したＦＥＴ２３と、ゲート電極をＦＥＴ２２のゲート電極に且つソース電極を高位側電源に接続し、ドレイン電極を出力端１０７に接続したＦＥＴ２４と、ＦＥＴ２３のソース電極と低位側電源９間に接続した定電流源Ｉ３と、ＦＥＴ２４のドレイン電極と低位側電源９間に接続した定電流源Ｉ４とで構成する。
【００３６】
なお、これらの駆動段回路４，５の回路動作については、第１の例と同様であるので、その説明を省略する。
【００３７】
また、上述した２と図３の駆動段回路を図４とは逆に組合せて構成することもできる。例えば、第１の駆動段回路として図２の駆動段回路４を用い、第２の駆動段回路として図３の駆動段回路５を用いて実現することもできる。
【００３８】
図５は図１における演算増幅器の差動型入力段回路の一例を示す詳細図である。図５に示すように、上述した演算増幅器１の差動型入力段回路２，３はつぎのように形成される。
【００３９】
例えば、差動型入力段回路２は、ソース電極が共通接続され、ゲート電極がそれぞれ第１の正入力端子ＶＩ１と第１の負入力端子ＶＩ２とに接続されたＦＥＴＮ１およびＮ２（ＮＭＯＳトランジスタ：以下同様）と、ゲート，ドレイン電極をＦＥＴＮ１のドレイン電極に接続し、ソース電極を高位側電源（ＶＤＤ）８に接続したＦＥＴＰ２（ＰＭＯＳトランジスタ：以下同様）と、ゲート，ドレイン電極をＦＥＴＮ２のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴＰ３と、ゲート電極をＦＥＴＰ２のゲート，ドレイン電極及びＦＥＴＮ１のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴＰ１と、ゲート電極をＦＥＴＰ３のゲート，ドレイン電極及びＦＥＴＮ２のドレイン電極に接続し、ソース電極を高位側電源８に且つドレイン電極を第１の出力端子に接続したＦＥＴＰ４と、ソース電極を共通接続し、ゲート電極をそれぞれ第１の負入力端子ＶＩ２と第１の正入力端子ＶＩ１に接続したＦＥＴＰ５及びＦＥＴＰ６と、ゲート，ドレイン電極をＦＥＴＰ１及びＦＥＴＰ５のドレイン電極に接続し、ソース電極を低位側電源９に接続したＦＥＴＮ３と、ゲート電極をＦＥＴＰ１，ＦＥＴＰ５のドレイン電極及びＦＥＴＮ３ゲート，ドレイン電極に接続し、ソース電極を低位側電源９に接続するとともに、ドレイン電極を第１の出力端子１０１及びＦＥＴＰ６のドレイン電極に接続したＦＥＴＮ４と、一端をＦＥＴＮ１，Ｎ２のソース電極に接続し且つ他端を低位側電源９に接続した第１の定電流源Ｉ１１と、一端をＦＥＴＰ５，Ｐ６のソース電極に接続し且つ他端を高位側電源８に接続した第２の定電流源Ｉ１２とで構成される。
【００４０】
同様に、差動型入力段回路３は、ソース電極を共通接続し、ゲート電極をそれぞれ第２の正入力端子ＶＩ３と第２の負入力端子ＶＩ４とに接続したＦＥＴＮ５およびＮ６と、ゲート，ドレイン電極をＦＥＴＮ５のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴＰ８と、ゲート，ドレイン電極をＦＥＴＮ６のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴＰ９と、ゲート電極をＦＥＴＰ８のゲート，ドレイン電極及びＦＥＴＮ５のドレイン電極に接続し、ソース電極を高位側電源８に接続したＦＥＴＰ７と、ゲート電極をＦＥＴＰ９のゲート，ドレイン電極及びＦＥＴＮ６のドレイン電極に且つソース電極を高位側電源８に接続し、ドレイン電極を第２の出力端子１０２に接続したＦＥＴＰ１０と、ソース電極を共通接続し、ゲート電極がそれぞれ第２の負入力端子ＶＩ４と第２の正入力端子ＶＩ３とに接続されたＦＥＴＰ１１およびＦＥＴＰ１２と、ゲート，ドレイン電極をＦＥＴＰ７およびＦＥＴＰ１１のドレイン電極に接続し、ソース電極を低位側電源９に接続したＦＥＴＮ７と、ゲート電極をＦＥＴＰ７，ＦＥＴＰ１１のドレイン電極及びＦＥＴＮ７のゲート，ドレイン電極に且つソース電極を低位側電源９に接続し、ドレイン電極を第２の出力端子１０２及びＦＥＴＰ１２のドレイン電極に接続したＦＥＴＮ８と、一端をＦＥＴＮ５，Ｎ６のソース電極に接続し且つ他端を低位側電源９に接続した第３の定電流源Ｉ１３と、一端をＦＥＴＰ１１，Ｐ１２のソース電極に接続し且つ他端を高位側電源８に接続した第４の定電流源Ｉ１４とで構成される。
【００４１】
上述の例では、差動型入力段回路２，３を形成する半導体素子としてＭＯＳＦＥＴの例を取り上げたが、ベース電極，エミッタ電極およびコレクタ電極を備えるバイポーラトランジスタにより形成しても良いし、また高位側電源および低位側電源を入れ換えて構成しても良い。さらに、液晶パネル駆動用の演算増幅器の形成にあたっては、上述した差動型入力段回路２，３と、前述した図２から図５の駆動段回路４，５とを組合わせて形成することもできる。
【００４２】
図６は本発明の演算増幅器を使用した液晶パネル駆動用回路の１例を示す構成図である。図６に示すように、液晶パネル駆動用回路４０は、中位側電源電位から高位側電源電位までのデジタル・アナログ変換を行う正極側Ｄ／Ａコンバータ４１と、低位側電源電位から中位側電源電位までのデジタル・アナログ変換を行う負極側Ｄ／Ａコンバータ４２と、これらのＤ／Ａコンバータ４１，４２の変換出力を外部からの制御入力によりスイッチングするスイッチ手段４３，４４と、これらスイッチ手段４３，４４で切替られた出力を正入力端子ＶＯ１，ＶＯ３に入力し、演算増幅して出力のインピーダンス変換を行って出力端子ＶＯ１，ＶＯ２に出力する上述（図１）の演算増幅器１と、この演算増幅器１の出力ＶＯ１ＶＯ２を外部からの制御入力によりスイッチングして演算増幅器１の負入力端子ＶＯ２，ＶＯ４に供給するスイッチ手段４５，４６と、演算増幅器１の出力ＶＯ１，ＶＯ２を外部からの制御入力によりスイッチングして出力端子ＯＵＴ１，ＯＵＴ２に供給するスイッチ手段４７，４８とを有している。なお、これらのうち、Ｄ／Ａコンバータ４１，４２と、スイッチ手段４３，４４およびスイッチ手段４７，４８とは、前述した図８の従来例と同様であるので、ここではその説明を省略する。
【００４３】
本実施の形態では、新たな演算増幅器１と、スイッチ手段４５，４６とを設けたことにあり、特にスイッチ手段４５は演算増幅器１の負入力端子ＶＩ２と出力端子ＶＯ１，ＶＯ２に接続され且つ相補動作するスイッチＳ，Ｓｂで形成したことにあり、同様にスイッチ手段４６は演算増幅器１の負入力端子ＶＩ４と出力端子ＶＯ１，ＶＯ２に接続され且つ相補動作するスイッチＳ，Ｓｂで形成したことにある。
【００４４】
この液晶パネル駆動用回路４０の動作は、まずスイッチ手段４３〜４８におけるスイッチＳおよび演算増幅器１内のスイッチＳ１，Ｓ２（図１参照）がＯＮ（Ｓ１ｂ，Ｓ２ｂはＯＦＦ）の時、正極側Ｄ／Ａコンバータ４１から出力されたアナログ信号と、負極側Ｄ／Ａコンバータ４２から出力されたアナログ信号がそれぞれ演算増幅器１の正入力端子ＶＩ１，ＶＩ２に入力される。すなわち、正極側のアナログ信号は、図１中の演算増幅器１における差動入力段回路２，駆動段回路４に入力され、インピーダンス変換され、出力信号として出力端子ＯＵＴ１に出力される。一方、負極側のアナログ信号は、図１中の演算増幅器１における差動入力段回路３，駆動段回路５に入力されるので、インピーダンス変換され、出力信号として出力端子ＯＵＴ２に出力される。
【００４５】
次に、スイッチ手段４３〜４８におけるスイッチＳｂおよび演算増幅器１内のスイッチＳ１ｂ，Ｓ２ｂ（図１参照）がＯＮ（Ｓ１，Ｓ２はＯＦＦ）の時、正極側Ｄ／Ａコンバータ４１から出力されたアナログ信号と、負極側Ｄ／Ａコンバータ４２から出力されたアナログ信号がそれぞれ演算増幅器１の正入力端子ＶＩ１，ＶＩ２に入力される。すなわち、正極側のアナログ信号は、図１中の演算増幅器１における差動入力段回路２，駆動段回路５に入力され、インピーダンス変換され、出力信号として出力端子ＯＵＴ２に出力される。一方、負極側のアナログ信号は、図１中の演算増幅器１における差動入力段回路３，駆動段回路４に入力され、インピーダンス変換され、出力信号として出力端子ＯＵＴ１に出力される。
【００４６】
かかる液晶パネル駆動用回路４０は、数十回正極側または負極側のアナログ信号を出力端子ＯＵＴ１，ＯＵＴ２に出力（パネルに対して書き込みを行う）し、操作ラインが切り替われば、正極側のアナログ信号を出力していた端子と、負極側アナログ信号を出力していた端子とを入れ替え、交流駆動を行う。
【００４７】
以上説明した動作をタイミングチャートで示すと、前述した図９の従来駆動と同様となる。
【００４８】
要するに、上述した演算増幅器１およびスイッチ手段４３〜４８を使用することにより、出力端子ＯＵＴ１，ＯＵＴ２における充放電は高位側電源から中位側電源の間または中位側電源から低位側電源の間で行われ、仮に高位側電源と中位側電源との電位差または中位側電源と低位側電源との電位差をＶＤＤ／２（ボルト）、書き込み振幅をＶｐｐ、書き込み周波数をｆ（Ｈｚ）、液晶パネルの容量性負荷の値をＣとすれば、１出力あたりの消費電力Ｐは、つぎの式で表わすことができる。
【００４９】
Ｐ＝Ｃ×ｆ×Ｖｐｐ×（ＶＤＤ／２）
従って、本実施形態の液晶パネル駆動回路４０を用いると、従来の液晶パネル駆動回路を使用した場合と比べて、１／２の負荷消費電力にすることができる。しかも、正極側書き込み時に使用する差動型入力段回路と負極側書き込み時に使用する差動型入力段回路とが同一であるため、交流駆動を行う際に発生する液晶パネルの表示ムラを従来通り極力抑制することができる。
【００５０】
また、液晶パネル駆動回路は、上述した液晶パネル駆動回路４０を複数個用いて形成するとができる。
【００５１】
さらに、この液晶パネル駆動回路は、複数個の液晶パネル駆動用回路を設けて形成される。
【００５２】
【発明の効果】
以上説明のように、本発明の液晶パネル駆動用演算増幅器及びその演算増幅器を用いた液晶パネル駆動回路は、演算増幅器の差動段出力を駆動段回路に供給する経路をスイッチ手段により切換え、しかも出力段ＦＥＴを高位側電源，低位側電源の他に中位側電源を用いて駆動することにより、負荷を充放電する場合に発生する負荷電力を小さくでき、しかもパネル表示時の色ムラを極力抑制できるという効果がある。
【図面の簡単な説明】
【図１】本発明の一実施形態を示すパネル駆動用演算増幅器の構成図である。
【図２】図１における演算増幅器の駆動段回路の第１の例を示す詳細図である。
【図３】図１における演算増幅器の駆動段回路の第２の例を示す詳細図である。
【図４】図１における演算増幅器の駆動段回路の第３の例を示す詳細図である。
【図５】図１における演算増幅器の差動型入力段回路の一例を示す詳細図である。
【図６】本発明の他の実施形態を示す演算増幅器を使用した液晶パネル駆動用回路の構成図である。
【図７】従来の液晶パネル駆動用演算増幅器の一例を示す構成図である。
【図８】従来の演算増幅器を使用した液晶パネル駆動用回路の一例を示す構成図である。
【図９】従来の液晶パネル駆動用回路の出力波形のタイミング図である。
【符号の説明】
１演算増幅器
２，３差動型入力段回路
４，５駆動段回路
６，７，４３〜４８スイッチ手段
８高位側電源
９低位側電源
１０中位側電源
１１〜１４出力段ＦＥＴ
４０液晶パネル駆動用回路
４１正側Ｄ／Ａコンバータ
４２負側Ｄ／Ａコンバータ
ＶＩ１，ＶＩ３正入力端子
ＶＩ２，ＶＩ４負入力端子
１０１，１０２差動型入力段出力端子
１０３，１０４駆動段入力端子
１０５〜１０８駆動段出力端子
Ｉ１〜Ｉ１４定電流源
ＶＯ１，ＶＯ２演算増幅器出力端子
ＯＵＴ１，ＯＵＴ２液晶パネル駆動用回路出力端子
Ｓ１，Ｓ１ｂ，Ｓ２，Ｓ２ｂ，Ｓ，Ｓｂスイッチ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal panel driving device, and more particularly to an operational amplifier for calculating and amplifying an input signal and a liquid crystal panel driving circuit using the operational amplifier.
[0002]
[Prior art]
In general, a liquid crystal panel needs to write several tens of frames (several tens) per second. For this reason, the output signal from the liquid crystal panel driving circuit performs AC driving for each scanning line or for each frame with respect to the potential of the counter electrode of the liquid crystal panel. A liquid crystal panel driving operational amplifier and a liquid crystal panel driving circuit that perform AC driving with respect to the potential of the counter electrode of the liquid crystal panel will be described with reference to FIGS.
[0003]
FIG. 7 is a block diagram showing an example of a conventional operational amplifier for driving a liquid crystal panel. As shown in FIG. 7, a conventional operational amplifier 1a for driving a liquid crystal panel is connected between a high power supply (VDD) 8 and a low power supply (VSS) 9, and has a positive input terminal VI1, a negative input terminal VI2, and a positive input terminal VI2, respectively. The differential input stage circuits 2 and 3 that amplify the differential voltage between the analog inputs supplied to the input terminal VI3 and the negative input terminal VI4 and output the amplified voltage to the differential input stage output terminals 101 and 102, as well as the higher power supply 8 And the output stages FET11, 12 and FET13, 14 having one connected between the lower power supply 9 and the other connected to the output terminals VO1, VO2 of the operational amplifier 1a, respectively, and similarly between the higher power supply 8 and the lower power supply 9 And drive outputs to the output stages FET 11 and 12 and FETs 13 and 14 based on the differential outputs from the output terminals 101 and 102, respectively. Has a drive stage circuits 4 and 5 supplied via 107 to rabbi is functionally used as a conversion circuit of the output impedance.
[0004]
The differential input stage circuits 2 and 3 of the operational amplifier 1a for driving the liquid crystal panel can secure the input range from the lower power supply level (VSS) to the higher power supply level (VDD). The output stage FET 11 has a gate electrode connected to the output terminal VO1 of the drive stage circuit 4, and a source electrode and a drain electrode connected to the high-potential power supply 8 and the output terminal VO1, respectively. The output stage FET 13 is similarly connected to the drive stage circuit 5 and the output terminal VO2. Further, the output stage FETs 12 and 14 are connected to the lower power supply 9 and the output terminal VO2.
[0005]
FIG. 8 is a block diagram showing an example of a liquid crystal panel driving circuit using a conventional operational amplifier. As shown in FIG. 8, the liquid crystal panel driving circuit 40a includes a positive side D / A converter 41 and a negative side D / A converter 42 that D / A convert digital data of the positive side input and the negative side input, respectively. The switching means 43 and 44 for switching the conversion outputs of these D / A converters 41 and 42 by an external control input, and the calculation described above (FIG. 7) for calculating and amplifying the output switched by these switching means 43 and 44 The amplifier 1a has switching means 47 and 48 for switching the outputs VO1 and VO2 of the operational amplifier 1a by an external control input and supplying them to the output terminals OUT1 and OUT2.
[0006]
These D / A converters 41 and 42 convert the intermediate potential into analog data of the higher power supply and the intermediate potential to the lower power supply according to the input digital data. Each switch means 43, 44, 47, 48 includes a pair of switches S and Sb that perform opposite operations. Further, the operational amplifier 1a performs negative feedback of the signal, and the outputs VO1, VO2 are fed back to the negative inputs VI2, VI4 with respect to the positive inputs VI1, VI3.
[0007]
The operation of the liquid crystal panel driving circuit 40a is output from the positive-side D / A converter 41 when each switch S in the switch means 43, 44, 47, 48 is ON (the switch Sb is OFF at this time). The analog signal and the analog signal output from the negative-side D / A converter 42 are input to the operational amplifier 1a, respectively, impedance converted, and output as an output signal to the output terminal OUT1 or OUT2 via the switch means 47 or 48. The Note that a large number of outputs from the liquid crystal panel driving circuit 40a are provided to drive each element of the panel. However, in order to simplify the description, two outputs are described for convenience.
[0008]
The same applies when each switch Sb in the switch means 43, 44, 47, 48 is ON (the switch S is OFF at this time), and the analog signal selected by the positive-side D / A converter 41 is impedance-converted. The analog signal selected by the negative terminal D / A converter 42 is also impedance-converted to the output terminal OUT2 and output to the output terminal OUT1.
[0009]
The liquid crystal panel driving circuit 40a outputs the analog signal on the positive electrode side or the negative electrode side several tens of times, that is, performs writing on the panel. When the scanning line is switched, AC driving is performed by switching the terminal that outputs the positive side and the terminal that outputs the negative side.
[0010]
FIG. 9 is a timing diagram of output waveforms of a conventional liquid crystal panel driving circuit. As shown in FIG. 9, when the switches S and Sb perform opposite switching operations, the signal waveform for charging / discharging the liquid crystal panel output to the output terminals OUT1 and OUT2 changes from the higher power supply voltage VDD to the lower power supply voltage. It changes to VSS and from the lower power supply voltage VSS to the higher power supply voltage VDD.
[0011]
[Problems to be solved by the invention]
The liquid crystal panel described above is a capacitive load. For this reason, driving the liquid crystal panel by a change in the input analog signal means charging / discharging the capacitive load of the liquid crystal panel.
[0012]
Further, as described above, the liquid crystal panel driving circuit outputs the positive side or negative side voltage several tens of times, then switches the output polarity and outputs the negative side or positive side voltage several tens of times, and repeats the operation. Do.
[0013]
Since charging and discharging of the capacitive load is performed between the high-order power supply and the low-order power supply, the potential difference between the high-order power supply and the low-order power supply is VDD, the write amplitude is Vpp, the write frequency is f (Hz), and the liquid crystal When the capacitance value of the capacitive load of the panel is C, the power consumption P per output can be expressed by the following equation.
[0014]
P = C × f × Vpp × VDD
However, the above-described conventional operational amplifier and the liquid crystal panel drive circuit using the same have the potential difference between the high-side power supply and the low-side power supply, although only the positive side or negative side output voltage is written several tens of times. Is VDD (when VSS is set to 0 V), there is a problem that the power consumption P is increased.
[0015]
Further, when AC driving of the liquid crystal panel is performed, it is necessary to suppress display unevenness of the liquid crystal panel as much as possible.
[0016]
An object of the present invention is to reduce the panel load charge / discharge power consumed when AC driving of a liquid crystal panel is performed, and an operational amplifier capable of suppressing display unevenness of the liquid crystal panel generated when performing AC driving as much as possible. And a liquid crystal panel driving circuit using the same.
[0017]
[Means for Solving the Problems]
The present invention reduces the power consumption and suppresses the display unevenness of the liquid crystal panel that occurs when alternating current drive is performed as much as possible in the same manner as the conventional example. In addition, a middle power supply and switch means are provided. In particular, regarding the transistor stage that finally outputs, the output transistor stage that drives the positive side is connected between the high-side power source and the middle-side power source, and the output transistor stage that drives the negative side is the middle-side power source. Connect between the lower power supplies.
[0018]
By using such means, charging / discharging is performed between the high power supply and the middle power supply or between the middle power supply and the low power supply, and the potential difference between the high power supply and the middle power supply or the Assuming that the potential difference between the side power supply and the lower power supply is VDD / 2, the writing amplitude is Vpp, the writing frequency is f (Hz), and the capacitance value of the capacitive load of the liquid crystal panel is C, the power consumption P per output is It can be expressed by the following formula.
[0019]
P = C × f × Vpp × (VDD / 2)
The present invention also provides a liquid crystal panel that is generated when AC driving is performed by making the differential input stage circuit used at the time of positive side writing the same as the differential input stage circuit used at the time of negative side writing. Display unevenness can be suppressed as much as possible.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of an operational amplifier and a liquid crystal panel driving circuit using the operational amplifier according to the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a configuration diagram of a panel driving operational amplifier showing an embodiment of the present invention. As shown in FIG. 1, a liquid crystal panel driving operational amplifier 1 according to the present embodiment is connected between a high-potential power supply (VDD) 8 and a low-potential power supply (VSS) 9, and has a positive input terminal VI1 and a negative input terminal, respectively. Differential input stage circuits 2 and 3 for amplifying the differential voltage of the analog input supplied to VI2 and positive input terminal VI3 and negative input terminal VI4 and outputting them to differential input stage output terminals 101 and 102; VDD) power supply 8 and intermediate side (VDD / 2) power supply 10 are connected in series and output stage FETs 11 and 12 having an output terminal VO1 connected to the connection point thereof, and intermediate side (VDD / 2) power supply 10 And the output stage FETs 13 and 14 connected in series between the lower power supply (VSS) power supply 9 and connected to the output terminal VO2 at their connection points, the differential input stage outputs 101 and 102, and the drive stage input 103 Switch means 6, 7 comprising switches S 1, S 1 b and switches S 2 b, S 2, which are connected between 104 and controlled to be turned on / off by a predetermined control signal supplied from the outside and operate in opposition to each other; Is connected between the low-side power supply 8 and the low-side power supply 9, and drive outputs to the output stages FET 11, 12 and FETs 13, 14 based on signals from the input terminals 103, 104 via the output terminals 105, 106 and 107, 108, respectively. Drive stage circuits 4 and 5 that are supplied in a functional manner, and are functionally used as an output impedance conversion circuit. The differential input stage circuits 2 and 3 can ensure the input range from the lower power supply level (VSS) to the higher power supply level (VDD).
[0022]
The operational amplifier 1 for driving the panel is that the switch means 6 and 7 and the middle power supply 10 are added. The switch means 6 and 7 have their constituent switches S1 and S2 turned on and off in the same phase. The switches S1b and S2b that are turned off and on in the opposite phase to the switches S1 and S2 are turned on and off in the same phase. Further, by providing the middle power supply 10, the rise of the output voltage at the output terminals VO 1 and VO 2 is speeded up, the panel load charge / discharge power is reduced, and the display unevenness of the liquid crystal panel that occurs when AC driving is performed. Is suppressed.
[0023]
FIG. 2 is a detailed diagram showing a first example of the driving stage circuit of the operational amplifier in FIG. As shown in FIG. 2, the driving stage circuit 4 in the operational amplifier includes an FET 15 having a gate electrode connected to the input terminal 103 and a source electrode connected to the lower power supply 9 (VSS), and a gate electrode and a drain electrode. The FET 16 is connected to the drain electrode of the FET 15, the source electrode is connected to the high-order power supply 8 (VDD), the gate electrode is connected to the drain electrode of the FET 15 and the gate and drain electrodes of the FET 16, and the source electrode is the high-order power supply 8. FET 17 connected to, and the gate and drain electrodes are connected to the output terminal 105, the source electrode is connected to the drain electrode of FET 17, and the gate electrode is the drain electrode of FET 15 and the gate and drain electrode of FET 16. The gate electrode and the source electrode are connected to the higher power supply 8 and the drain The FET 19 whose electrode is connected to the output terminal 106, one end connected to the gate of the FET 18, the rain electrode and the output terminal 105, the other end connected to the lower power supply 9, and one end to the drain of the FET 19 The constant current source I2 is connected to the electrode and the output terminal 106, and the other end is connected to the lower power supply 9.
[0024]
Similarly, the drive stage circuit 5 includes an FET 20 having a gate electrode connected to the input terminal 104 and a source electrode connected to the lower power supply 9, and a gate electrode and a drain electrode connected to the drain electrode of the FET 20. FET 21 connected to the higher power supply 8, the gate electrode connected to the drain electrode of FET 20 and the gate and drain electrodes of FET 21, and the FET 22 connected to the higher power supply 8 and the gate and drain electrodes output The FET 23 connected to the terminal 108 and the drain electrode of the FET 22, the gate electrode is connected to the drain electrode of the FET 20, the gate of the FET 21, the drain electrode and the gate electrode of the FET 22, and the source electrode is connected to the high-order power supply 8. Is connected to the output terminal 107, and one end of the FET is connected to the FET 23. A constant current source I3 connected to the low-side power source 9 at the other end, a constant current source connected to the drain electrode and the output terminal 107 of the FET 24 at one end, and a constant current source connected to the low-side power source 9 at the other end. Source I4.
[0025]
The operation of the drive stage circuits 4 and 5 is as follows. When the inputs 103 and 104 in which the output signals 101 and 102 from the differential input stage circuits 2 and 3 are switched by the switch means 6 and 7 are supplied. The signals are converted in the drive stage circuits 4 and 5 and transmitted as the output signals 105 and 106 and 107 and 108 to the final output FETs 11 and 12 and the output FETs 13 and 14.
[0026]
For example, in the positive input terminal VI1, the negative input terminal VI2 or the positive input terminal VI3, and the negative input terminal VI4 of the differential input stage circuit 2 or 3, the positive input terminals VI1 and VI4 are compared with the potential levels of the negative input terminals VI2 and VI4. When the potential level of VI3 increases, the output signals 101 and 102 of the differential input stage circuits 2 and 3 become falling signals. The signal is converted in the drive stage circuits 4 and 5 and output as a fall signal to the output FETs 11, 12 and 13, 14 in the final stage. Then, the output FETs 11, 12, 13, and 14 at the final stage have FETs 11 and 13 having low resistance and the FETs 12 and 14 have high resistance, respectively, and are output as charging signals for the load.
[0027]
Similarly, in the positive input terminal VI1, the negative input terminal VI2 or the positive input terminal VI3, and the negative input terminal VI4 of the differential input stage circuit 2 or 3, the positive input terminal VI1 is compared with the potential level of the negative input terminals VI2 and VI4. , VI3 become low, the output signals 101, 102 of the differential input stage circuits 2, 3 become rising signals. The signal is converted in the drive stage circuits 4 and 5 and is output as a rising signal to the output FETs 11, 12 and 13, 14 in the final stage. Then, the output FETs 11, 12, 13, and 14 at the final stage have FETs 11 and 13 having high resistance and the FETs 12 and 14 have low resistance, respectively, and are output as discharge signals to the load.
[0028]
Therefore, if these drive stage circuits 4 and 5 are used, a push-pull operation with respect to the load is possible.
[0029]
Further, when such driving stage circuits 4 and 5 are used, even if the source electrode potentials of the output FETs 12 and 13 in the final stage are floating with respect to the back gate electrode potential, there is no operational problem. The reason is that the steady-state currents flowing in the final stage output FETs 11 and 12 or FETs 13 and 14 are determined by the FETs 18 and 23 in the drive stage circuits 4 and 5 and the output stage FETs 11 and 14 constituting a current mirror. Because. In that case, even if the source electrode potentials of the output stage FETs 12 and 13 float with respect to the back gate electrode potential, no problem occurs.
[0030]
FIG. 3 is a detailed diagram showing a second example of the driving stage circuit of the operational amplifier in FIG. As shown in FIG. 3, the driving stage circuit 4 in the operational amplifier includes an FET 25 having a gate electrode connected to the input terminal 103 and a source electrode connected to the lower power supply 9 (VSS), and a gate electrode and a drain electrode. The FET 26 is connected to the drain electrode of the FET 25, the source electrode is connected to the lower power supply 9, the gate electrode is connected to the drain electrode of the FET 25, the gate and drain electrodes of the FET 26, and the source electrode is connected to the lower power supply 9. FET 27, the gate and drain electrodes of which are connected to the drain electrode of FET 27 and output terminal 105, the gate electrode of which is connected to the drain electrode of FET 25, the gate of FET 26, the drain electrode and the gate electrode of FET 27, and the source electrode of which is Connected to the lower power supply 9 and connected to the output terminal 106 at the drain electrode. FET 29, one end connected to the drain electrode of FET 25, the gate of FET 26, the drain electrode and the gate electrode of FET 27 and FET 29, the other end connected to the high-order power supply 8, and one end connected to the source of FET 28. The constant current source I6 is connected to the electrode, the other end is connected to the high-order power supply 8, and the constant current source I7 is connected to the drain electrode of the FET 29 and the output terminal 106 at one end.
[0031]
Similarly, the drive stage circuit 5 includes an FET 30 having a gate electrode connected to the input terminal 104 and a source electrode connected to the lower power supply 9, and a gate electrode and a drain electrode connected to the drain electrode of the FET 30. FET 31 connected to the lower power supply 9, the gate electrode connected to the drain electrode of FET 30 and the gate and drain electrodes of FET 31, and the FET 32 connected to the lower power supply 9 and the gate and drain electrodes output The FET 33 is connected to the terminal 108, the source electrode is connected to the drain electrode of the FET 32, the gate electrode is connected to the drain electrode of the FET 30, the gate of the FET 31, the drain electrode and the gate electrode of the FET 32, and the source electrode is the low-side power supply 9 FET 34 having a drain electrode connected to output terminal 107, and One end is connected to the drain electrode of the FET 30 and the gate of the FET 31, the drain electrode is connected to the gate electrode of the FET 32 and the FET 34, the other end is connected to the high-order power source 8, and one end is connected to the gate and drain electrode of the FET 33. The constant current source I9 is connected to the output terminal 108, and the other end is connected to the high-order power supply 8. The constant current source I10 is connected to the drain electrode of the FET 34 and the output terminal 107 at one end.
[0032]
The operation of the driving stage circuits 4 and 5 in this case is the same as that of the first example of FIG.
[0033]
FIG. 4 is a detailed diagram showing a third example of the driving stage circuit of the operational amplifier in FIG. As shown in FIG. 4, the driving stage circuit in the operational amplifier in this case includes the driving stage circuit 4 in the second example of FIG. 3 and the driving stage circuit 5 in the first example of FIG. It is a combination.
[0034]
That is, the driving stage circuit 4 has the FET 55 in which the gate electrode is connected to the input terminal 103 and the source electrode is connected to the lower power supply 9, and the gate and drain electrodes are connected to the drain electrode of the FET 25 and the source electrode is connected to the lower power supply 9. The FET 26, the gate electrode connected to the gate electrode of the FET 26, the FET 27 connected to the lower power supply 9, the FET 28 connected the gate and drain electrodes to the drain electrode of the FET 27 and the output terminal 105, and the gate electrode FET 27 FET 29 having a source electrode connected to the lower power supply 9 and a drain electrode connected to the output terminal 106, a constant current source I5 connected between the drain electrode of FET25 and the higher power supply 8, and an FET 28 A constant current source I6 connected between the source electrode and the higher power supply 8 and between the output terminal 106 and the higher power supply 8 Composed of a constant current source I7 connected.
[0035]
On the other hand, the drive stage circuit 5 has the FET 20 having the gate electrode connected to the input terminal 104, the source electrode connected to the low-side power supply 9, the gate and drain electrodes connected to the drain electrode of the FET 20, and the source electrode connected to the high-side power supply. FET 21 connected to 8, FET 22 having a gate electrode connected to the gate electrode of FET 21, FET 22 having a source electrode connected to the higher power supply 8, FET 23 having the gate and drain electrodes connected to the drain electrode of FET 22 and the output terminal 108, An FET 24 having a gate electrode connected to the gate electrode of the FET 22 and a source electrode connected to the high-side power source, and a drain electrode connected to the output terminal 107; a constant current source I3 connected between the source electrode of the FET 23 and the low-side power source 9; It comprises a constant current source I4 connected between the drain electrode of the FET 24 and the lower power supply 9.
[0036]
Note that the circuit operations of these drive stage circuits 4 and 5 are the same as those in the first example, and thus the description thereof is omitted.
[0037]
Further, the above-described drive stage circuit 2 and FIG. 3 can be combined in the reverse manner of FIG. For example, the drive stage circuit 4 of FIG. 2 can be used as the first drive stage circuit, and the drive stage circuit 5 of FIG. 3 can be used as the second drive stage circuit.
[0038]
FIG. 5 is a detailed diagram showing an example of the differential input stage circuit of the operational amplifier in FIG. As shown in FIG. 5, the differential input stage circuits 2 and 3 of the operational amplifier 1 described above are formed as follows.
[0039]
For example, the differential input stage circuit 2 includes FETs whose source electrodes are commonly connected and whose gate electrodes are respectively connected to the first positive input terminal VI1 and the first negative input terminal VI2. N 1 and N 2 ( N MOS transistor (same below) and gate and drain electrodes are FET N 1 FET connected to the drain electrode, and the source electrode connected to the higher power supply (VDD) 8 P 2 ( P MOS transistor (same below) and gate and drain electrodes are FET N FET connected to the drain electrode of 2 and the source electrode connected to the higher power supply 8 P 3 and the gate electrode is FET P 2 gate, drain electrode and FET N FET connected to the drain electrode of 1 and the source electrode connected to the higher power supply 8 P 1 and the gate electrode is FET P 3 gate, drain electrode and FET N FET having a source electrode connected to the higher power supply 8 and a drain electrode connected to the first output terminal P 4 and the source electrode are connected in common, and the gate electrode is connected to the first negative input terminal VI2 and the first positive input terminal VI1, respectively. P 5 and FET P 6 and FET for gate and drain electrodes P 1 and FET P 5 FET connected to the drain electrode, and the source electrode connected to the lower power supply 9 N 3 and the gate electrode is FET P 1, FET P 5 drain electrode and FET N 3 The gate and drain electrodes are connected, the source electrode is connected to the lower power supply 9, and the drain electrode is connected to the first output terminal 101 and the FET. P FET connected to drain electrode of 6 N 4 and one end FET N 1, N A first constant current source I11 connected to the two source electrodes and the other end connected to the lower power supply 9; P 5, P 6 and a second constant current source I12 connected to the higher power source 8 at the other end.
[0040]
Similarly, the differential input stage circuit 3 includes FETs having source electrodes connected in common and gate electrodes connected to a second positive input terminal VI3 and a second negative input terminal VI4, respectively. N 5 and N 6 and FET for gate and drain electrodes N 5 FET connected to the drain electrode, and the source electrode connected to the higher power supply 8 P 8 and the gate and drain electrodes are FET N 6 FET connected to the drain electrode, and the source electrode connected to the higher power supply 8 P 9 and the gate electrode is FET P 8 gate, drain electrode and FET N 5 FET connected to the drain electrode, and the source electrode connected to the higher power supply 8 P 7 and the gate electrode is FET P 9 gate, drain electrode and FET N FET having the drain electrode connected to the high-order power supply 8 and the drain electrode connected to the second output terminal 102 P 10 and a source electrode connected in common, and a gate electrode connected to a second negative input terminal VI4 and a second positive input terminal VI3, respectively. P 11 and FET P 12 and FET gate and drain electrodes P 7 and FET P 11 FET connected to the drain electrode, and the source electrode connected to the lower power supply 9 N 7 and the gate electrode is FET P 7, FET P 11 drain electrodes and FETs N 7 and the source electrode are connected to the lower power supply 9 and the drain electrode is connected to the second output terminal 102 and the FET. P FET connected to 12 drain electrodes N 8 and one end FET N 5, N A third constant current source I13 connected to the source electrode 6 and the other end connected to the lower power supply 9; P 11, P The fourth constant current source I14 is connected to the 12 source electrodes and the other end is connected to the high-order power source 8.
[0041]
In the above example, the MOSFET is taken as an example of the semiconductor element forming the differential input stage circuits 2 and 3, but it may be formed by a bipolar transistor having a base electrode, an emitter electrode, and a collector electrode. The side power supply and the lower power supply may be interchanged. Further, when forming the operational amplifier for driving the liquid crystal panel, the differential input stage circuits 2 and 3 described above and the drive stage circuits 4 and 5 shown in FIGS. 2 to 5 described above may be combined. it can.
[0042]
FIG. 6 is a block diagram showing an example of a liquid crystal panel driving circuit using the operational amplifier of the present invention. As shown in FIG. 6, the liquid crystal panel driving circuit 40 includes a positive-side D / A converter 41 that performs digital / analog conversion from the middle power supply potential to the high power supply potential, and a middle power supply from the low power supply potential. Negative side D / A converter 42 for performing digital / analog conversion up to the power supply potential, switch means 43 and 44 for switching the conversion output of these D / A converters 41 and 42 by an external control input, and these switch means The above-described operational amplifier 1 (FIG. 1) that inputs the output switched at 43 and 44 to the positive input terminals VO1 and VO3, performs operational amplification, converts the output impedance, and outputs it to the output terminals VO1 and VO2; A switch for switching the output VO1VO2 of the operational amplifier 1 by a control input from the outside and supplying it to the negative input terminals VO2 and VO4 of the operational amplifier 1. And it means 45 and 46, and an output VO1, VO2 of operational amplifier 1 and switching the control input from the outside and a switching means 47, 48 to the output terminal OUT1, OUT2. Of these, the D / A converters 41 and 42, the switch means 43 and 44, and the switch means 47 and 48 are the same as the conventional example of FIG.
[0043]
In the present embodiment, a new operational amplifier 1 and switch means 45 and 46 are provided. In particular, the switch means 45 is connected to the negative input terminal VI2 and the output terminals VO1 and VO2 of the operational amplifier 1 and is complementary. Similarly, the switch means 46 is formed by switches S and Sb which are connected to the negative input terminal VI4 and the output terminals VO1 and VO2 of the operational amplifier 1 and operate in a complementary manner. .
[0044]
The operation of the liquid crystal panel driving circuit 40 is as follows. First, when the switch S in the switch means 43 to 48 and the switches S1 and S2 (see FIG. 1) in the operational amplifier 1 are ON (S1b and S2b are OFF), The analog signal output from the / A converter 41 and the analog signal output from the negative D / A converter 42 are input to the positive input terminals VI1 and VI2 of the operational amplifier 1, respectively. That is, the positive-side analog signal is input to the differential input stage circuit 2 and the drive stage circuit 4 in the operational amplifier 1 in FIG. 1, impedance-converted, and output as an output signal to the output terminal OUT1. On the other hand, the negative-side analog signal is input to the differential input stage circuit 3 and the drive stage circuit 5 in the operational amplifier 1 in FIG. 1, so that the impedance is converted and output as an output signal to the output terminal OUT2.
[0045]
Next, when the switch Sb in the switch means 43 to 48 and the switches S1b and S2b (see FIG. 1) in the operational amplifier 1 are ON (S1 and S2 are OFF), the analog output from the positive-side D / A converter 41 The signal and the analog signal output from the negative-side D / A converter 42 are input to the positive input terminals VI1 and VI2 of the operational amplifier 1, respectively. That is, the positive-side analog signal is input to the differential input stage circuit 2 and the driving stage circuit 5 in the operational amplifier 1 in FIG. 1, impedance-converted, and output as an output signal to the output terminal OUT2. On the other hand, the negative-side analog signal is input to the differential input stage circuit 3 and the drive stage circuit 4 in the operational amplifier 1 in FIG. 1, impedance-converted, and output as an output signal to the output terminal OUT1.
[0046]
The liquid crystal panel driving circuit 40 outputs a positive or negative analog signal to the output terminals OUT1 and OUT2 several tens of times (writes data to the panel), and switches the positive analog signal when the operation line is switched. The terminal that has output the signal and the terminal that has output the negative-side analog signal are switched to perform AC driving.
[0047]
When the operation described above is shown in a timing chart, it is the same as the conventional driving of FIG. 9 described above.
[0048]
In short, by using the operational amplifier 1 and the switch means 43 to 48 described above, charging / discharging at the output terminals OUT1 and OUT2 is performed between the high power supply and the middle power supply or between the middle power supply and the low power supply. Temporarily, the potential difference between the higher power supply and the middle power supply or the potential difference between the middle power supply and the lower power supply is VDD / 2 (volts), the write amplitude is Vpp, the write frequency is f (Hz), and the liquid crystal panel If the value of the capacitive load is C, the power consumption P per output can be expressed by the following equation.
[0049]
P = C × f × Vpp × (VDD / 2)
Therefore, when the liquid crystal panel drive circuit 40 of the present embodiment is used, the load power consumption can be reduced to ½ compared to the case where the conventional liquid crystal panel drive circuit is used. In addition, since the differential input stage circuit used at the time of writing on the positive electrode side is the same as the differential input stage circuit used at the time of writing on the negative electrode side, the display unevenness of the liquid crystal panel that occurs when AC driving is performed as usual. It can be suppressed as much as possible.
[0050]
Further, the liquid crystal panel drive circuit can be formed using a plurality of the liquid crystal panel drive circuits 40 described above.
[0051]
Further, the liquid crystal panel driving circuit is formed by providing a plurality of liquid crystal panel driving circuits.
[0052]
【The invention's effect】
As described above, the liquid crystal panel driving operational amplifier of the present invention and the liquid crystal panel driving circuit using the operational amplifier switch the path for supplying the differential stage output of the operational amplifier to the driving stage circuit by the switch means. By driving the output stage FET using the middle power supply in addition to the high power supply and low power supply, the load power generated when charging and discharging the load can be reduced, and color unevenness during panel display is minimized. There is an effect that it can be suppressed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an operational amplifier for driving a panel showing an embodiment of the present invention.
2 is a detailed diagram showing a first example of a driving stage circuit of the operational amplifier in FIG. 1; FIG.
FIG. 3 is a detailed diagram illustrating a second example of the driving stage circuit of the operational amplifier in FIG. 1;
4 is a detailed diagram showing a third example of the driving stage circuit of the operational amplifier in FIG. 1; FIG.
5 is a detailed diagram showing an example of a differential input stage circuit of the operational amplifier in FIG. 1. FIG.
FIG. 6 is a configuration diagram of a liquid crystal panel driving circuit using an operational amplifier according to another embodiment of the present invention.
FIG. 7 is a block diagram showing an example of a conventional operational amplifier for driving a liquid crystal panel.
FIG. 8 is a block diagram showing an example of a liquid crystal panel driving circuit using a conventional operational amplifier.
FIG. 9 is a timing chart of output waveforms of a conventional liquid crystal panel driving circuit.
[Explanation of symbols]
1 operational amplifier
2,3 Differential type input stage circuit
4,5 Drive stage circuit
6, 7, 43 to 48 Switch means
8 High power supply
9 Low power supply
10 Middle power supply
11-14 Output stage FET
40 LCD panel drive circuit
41 Positive D / A Converter
42 Negative D / A Converter
VI1, VI3 positive input terminal
VI2, VI4 Negative input terminal
101,102 Differential input stage output terminal
103,104 Drive stage input terminal
105 to 108 Drive stage output terminals
I1 to I14 constant current source
VO1, VO2 operational amplifier output terminals
OUT1, OUT2 LCD panel drive circuit output terminals
S1, S1b, S2, S2b, S, Sb switch

Claims

A differential input terminal composed of a first positive input terminal and a first negative input terminal and a first output terminal are connected between the low-order power supply and the high-order power supply, and the input range is changed from the low-order power supply level. A first differential input stage circuit that secures up to a higher power supply level;
A differential input terminal composed of a second positive input terminal and a second negative input terminal and a second output terminal are provided, and are connected between the low-order power supply and the high-order power supply, so that the input range is changed from the low-order power supply level. A second differential input stage circuit that secures up to a higher power supply level;
A first drive stage circuit connected between the lower power supply and the higher power supply and having a first input terminal and third and fourth output terminals;
A second drive stage circuit connected between the lower power supply and the higher power supply and having a second input terminal and fifth and sixth output terminals;
A first semiconductor element having a first electrode connected to the third output terminal of the first drive stage circuit and a second and a third electrode connected to the high-order power source and a first output terminal, respectively;
A second semiconductor element having a first electrode connected to a fourth output terminal of the first drive stage circuit and a second and a third electrode connected to a middle power source and the first output terminal, respectively; ,
A third semiconductor element in which a first electrode is connected to a fifth output terminal of the second drive stage circuit and a second and a third electrode are connected to the intermediate power supply and a second output terminal, respectively;
A fourth semiconductor element having a first electrode connected to a sixth output terminal of the second drive stage circuit and a second electrode and a third electrode connected to the lower power supply and the second output terminal, respectively;
The first output terminal of the first differential input stage circuit, the first input terminal of the first drive stage circuit, and the second input terminal of the second drive stage circuit, respectively. a first switch means having a connected and reciprocal operation to Luz switch,
The second output terminal of the second differential input stage circuit, the first input terminal of the first drive stage circuit, and the second input terminal of the second drive stage circuit, respectively. operational amplifier and having a second switch means having a connected and reciprocal operation to Luz switch.

The first drive stage circuit includes:
A fifth semiconductor element having a first electrode connected to the first input end and a second electrode connected to the lower power supply;
A sixth semiconductor element in which first and third electrodes are connected to a third electrode of the fifth semiconductor element, and a second electrode is connected to the higher power supply;
A seventh semiconductor element having a first electrode connected to the first electrode of the sixth semiconductor element and a second electrode connected to the higher power supply;
An eighth semiconductor element in which first and third electrodes are connected to the third output terminal, and a second electrode is connected to a third electrode of the seventh semiconductor element;
A ninth semiconductor element in which a first electrode is connected to the first electrode of the seventh semiconductor element, a second electrode is connected to the high-order power supply, and a third electrode is connected to the fourth output terminal When,
The first and second constant current sources connected between the third electrode of the eighth semiconductor element and the lower power supply and between the fourth output terminal and the lower power supply, respectively.
The second drive stage circuit includes:
A tenth semiconductor element having a first electrode connected to the second input terminal and a second electrode connected to the lower power supply;
An eleventh semiconductor element in which first and third electrodes are connected to a third electrode of the tenth semiconductor element, and a second electrode is connected to the high-order power supply;
A twelfth semiconductor element having a first electrode connected to the first electrode of the eleventh semiconductor element and a second electrode connected to the high-order power supply;
A thirteenth semiconductor element having first and third electrodes connected to the third electrode of the twelfth semiconductor element and the sixth output end;
A fourteenth semiconductor element having a first electrode connected to the first electrode of the twelfth semiconductor element, a second electrode connected to the high-order power supply, and a third electrode connected to the fifth output terminal When,
Third and fourth constant current sources connected between the second electrode of the thirteenth semiconductor element and the lower power supply and between the third electrode of the fourteenth semiconductor element and the lower power supply, respectively. The operational amplifier according to claim 1 configured.

The first drive stage circuit includes:
A fifth semiconductor element in which a first electrode is connected to the first input terminal, a second electrode is connected to the lower power supply, and first and third electrodes are connected to the fifth semiconductor element. A sixth semiconductor element connected to the third electrode and the second electrode connected to the lower power supply;
A first electrode connected to the first electrode of the sixth semiconductor device, a seventh semiconductor element connected to the second electrode to the low-potential power supply,
An eighth semiconductor element having first and third electrodes connected to the third electrode of the seventh semiconductor element and the third output end;
A ninth semiconductor element having a first electrode connected to the first electrode of the seventh semiconductor element, a second electrode connected to the lower power supply, and a third electrode connected to the fourth output terminal When,
Between the higher power supply and the third electrode of the fifth semiconductor element, between the higher power supply and the second electrode of the eighth semiconductor element, and between the higher power supply and the fourth output terminal. The first to third constant current sources connected to each other,
The second drive stage circuit includes:
A tenth semiconductor element having a first electrode connected to the second input terminal and a second electrode connected to the lower power supply;
An eleventh semiconductor element having first and third electrodes connected to the third electrode of the tenth semiconductor element, and a second electrode connected to the lower power supply;
A twelfth semiconductor element having a first electrode connected to the first electrode of the eleventh semiconductor element and a second electrode connected to the lower power supply;
A thirteenth semiconductor element having first and third electrodes connected to the sixth output end, and a second electrode connected to the third electrode of the twelfth semiconductor element;
A fourteenth semiconductor element having a first electrode connected to the first electrode of the twelfth semiconductor element, a second electrode connected to the lower power supply, and a third electrode connected to the fifth output terminal; When,
Between the higher power supply and the third electrode of the tenth semiconductor element, between the higher power supply and the third electrode of the thirteenth semiconductor element, and between the higher power supply and the fifth output terminal. fourth to sixth constant current source and the configuration claims 1, wherein the arithmetic amplifier connected respectively.

The first drive stage circuit includes:
A fifth semiconductor element in which the first electrode is connected to the first input terminal, the second electrode is connected to the lower power supply, and the first and third electrodes are the third of the fifth semiconductor element. A sixth semiconductor element connected to the first electrode and a second electrode connected to the lower power supply;
A seventh semiconductor element having a first electrode connected to the first electrode of the sixth semiconductor element and a second electrode connected to the lower power supply;
An eighth semiconductor element having first and third electrodes connected to the third electrode of the seventh semiconductor element and the third output end;
A ninth semiconductor element having a first electrode connected to the first electrode of the seventh semiconductor element, a second electrode connected to the lower power supply, and a third electrode connected to the fourth output terminal When,
Between the higher power supply and the third electrode of the fifth semiconductor element, between the higher power supply and the second electrode of the eighth semiconductor element, and between the higher power supply and the fourth output terminal. The first to third constant current sources connected to each other,
The second drive stage circuit includes:
A tenth semiconductor element having a first electrode connected to the second input terminal and a second electrode connected to the lower power supply;
An eleventh semiconductor element in which first and third electrodes are connected to a third electrode of the tenth semiconductor element, and a second electrode is connected to the high-order power supply;
A twelfth semiconductor element having a first electrode connected to the first electrode of the eleventh semiconductor element and a second electrode connected to the high-order power supply;
A thirteenth semiconductor element having first and third electrodes connected to the third electrode of the twelfth semiconductor element and the sixth output end;
A fourteenth semiconductor element having a first electrode connected to the first electrode of the twelfth semiconductor element, a second electrode connected to the high-order power supply, and a third electrode connected to the fifth output terminal When,
2. The fourth and fifth constant current sources connected between the second electrode of the thirteenth semiconductor element and the lower power source and between the fifth output terminal and the lower power source, respectively. The operational amplifier described.

The first drive stage circuit includes:
A fifth semiconductor element having a first electrode connected to the first input end and a second electrode connected to the lower power supply;
A sixth semiconductor element in which first and third electrodes are connected to a third electrode of the fifth semiconductor element, and a second electrode is connected to the higher power supply;
A seventh semiconductor element having a first electrode connected to the first electrode of the sixth semiconductor element and a second electrode connected to the higher power supply;
An eighth semiconductor element in which first and third electrodes are connected to the third output terminal, and a second electrode is connected to a third electrode of the seventh semiconductor element;
A ninth semiconductor element in which a first electrode is connected to the first electrode of the seventh semiconductor element, a second electrode is connected to the high-order power supply, and a third electrode is connected to the fourth output terminal When,
The first and second constant current sources connected between the third electrode of the eighth semiconductor element and the lower power supply and between the fourth output terminal and the lower power supply, respectively.
The second drive stage circuit includes:
A tenth semiconductor element having a first electrode connected to the second input terminal and a second electrode connected to the lower power supply;
An eleventh semiconductor element having first and third electrodes connected to the third electrode of the tenth semiconductor element, and a second electrode connected to the lower power supply;
A twelfth semiconductor element having a first electrode connected to the first electrode of the eleventh semiconductor element and a second electrode connected to the lower power supply;
A thirteenth semiconductor element having first and third electrodes connected to the sixth output end, and a second electrode connected to the third electrode of the twelfth semiconductor element;
A fourteenth semiconductor element having a first electrode connected to the first electrode of the twelfth semiconductor element, a second electrode connected to the lower power supply, and a third electrode connected to the fifth output terminal; When,
Between the higher power supply and the third electrode of the tenth semiconductor element, between the higher power supply and the third electrode of the thirteenth semiconductor element, and between the higher power supply and the fifth output terminal. 2. The operational amplifier according to claim 1, wherein the operational amplifier is composed of third to fifth constant current sources connected to each other.

The first differential input stage circuit is:
Fifteenth and sixteenth semiconductor elements, each having a first electrode connected to the first positive input terminal and the first negative input terminal, and a second electrode commonly connected;
A seventeenth semiconductor element in which first and third electrodes are connected to a third electrode of the fifteenth semiconductor element, and a second electrode is connected to the high-order power supply;
An eighteenth semiconductor element in which first and third electrodes are connected to a third electrode of the sixteenth semiconductor element, and a second electrode is connected to the high-order power supply;
A nineteenth semiconductor element having a first electrode connected to the first electrode of the seventeenth semiconductor element and a second electrode connected to the high-order power supply;
A twentieth semiconductor element in which a first electrode is connected to the first electrode of the eighteenth semiconductor element, a second electrode is connected to the high-order power supply, and a third electrode is connected to the first output terminal. When,
A seventh constant current source connected between the second electrodes of the fifteenth and sixteenth semiconductor elements and the lower power supply;
21st and 22nd semiconductor elements, each having a first electrode connected to the first negative input terminal and the first positive input terminal, and a second electrode connected in common,
A 23rd semiconductor element having a first electrode connected to a third electrode of the nineteenth and twenty-first semiconductor elements and a second electrode connected to the lower power supply;
The first electrode is connected to the first electrode of the twenty- third semiconductor element, the second electrode is connected to the lower power supply, and the third electrode is connected to the first output terminal and the twenty-second semiconductor element. A twenty-fourth semiconductor element connected to the third electrode;
The high-potential power supply and the second 1, constituted by the eighth constant current source connected between the second electrode of the semiconductor element 22,
The second differential input stage circuit is:
25th and 26th semiconductor elements, each having a first electrode connected to the second positive input terminal and a second negative input terminal, and a second electrode connected in common,
A first, a third electrode connected to the third electrode of the second 25 semiconductor devices, the 27 semiconductor element connected to the second electrode to the high-potential power supply,
A first, a third electrode connected to the third electrode of the semiconductor element of the first 26, second 28 semiconductor element connecting a second electrode to said high-potential power supply,
A first electrode connected to the first electrode of the semiconductor element of the first 27 and second 29 semiconductor element connecting a second electrode to said high-potential power supply,
A thirty- third semiconductor element in which a first electrode is connected to the first electrode of the twenty-eighth semiconductor element, a second electrode is connected to the high-order power supply, and a third electrode is connected to the second output terminal. When,
A ninth constant current source connected between the second electrodes of the 25th and 26th semiconductor elements and the lower power supply;
31st and 32nd semiconductor elements, each having a first electrode connected to the second negative input terminal and a second positive input terminal, and a second electrode connected in common;
A first, a third electrode connected to the third electrode of the first 29 and second 31 semiconductor devices, the 33 semiconductor element connected to the second electrode to the low-potential power supply,
The first electrode is connected to the first electrode of the 33rd semiconductor element, the second electrode is connected to the lower power supply, and the third electrode is connected to the second output terminal and the 32nd semiconductor element. A thirty- fourth semiconductor element connected to the third electrode;
6. The operational amplifier according to claim 1, wherein the operational amplifier includes the high-order power source and a tenth constant current source connected between second electrodes of the 31st and 32nd semiconductor elements.

The operational amplifier according to any one of claims 1 to 6, respectively, the first electrode the gate electrode of the semiconductor element, the second electrode is a source electrode, a third electrode is a drain electrode An operational amplifier formed by an FET comprising:

The operational amplifier according to any one of claims 1 to 6, each of the semiconductor element, a base electrode as a first electrode, an emitter electrode as a second electrode, a collector electrode as a third electrode An operational amplifier formed by a bipolar transistor provided.