JPH10177367A - Liquid crystal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving circuit capable of miniaturizing its size. SOLUTION: Power supply voltage components +2Va, -2Va are impressed to an operational amplifier 10, which outputs voltage +2Va or +Va. Power supply voltage components of +Va and ground potential are impressed to an operational amplifier 11, which outputs the voltage of +Va or ground potential. These output voltage components are impressed to one terminal of a liquid crystal cell 523 and voltage +Va from a counter electrode 513 is impressed to the other terminal. When the voltage +2Va is outputted from the amplifier 10, the cell 523 is driven by voltage +Va, and when the voltage of ground potential is outputted from the amplifier 11, the cell 523 is driven by voltage -Va. Since voltage to be impressed to the amplifiers 10, 11 can be reduced to a half of conventional voltage, a low voltage resistance transistor can be used and the circuit can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal driving circuit, and more particularly to a liquid crystal driving circuit using an operational amplifier.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram of a main part of a conventional liquid crystal drive circuit and a liquid crystal display. The conventional liquid crystal driving circuit 500 includes a plurality of operational amplifiers 501 to 50n (n is a positive integer), and a liquid crystal display 510 includes a plurality of liquid crystal cells 511 and transistors 512 arranged in a matrix.

Then, the drain of the transistor 512 and one terminal of the liquid crystal cell 511 are connected, and the liquid crystal cell 51 is connected.
1 is connected to the counter electrode 513, the source of the transistor 512 is connected to the output terminals of the operational amplifiers 501 to 50n, and the gate of the transistor 512 is connected to the gate electrode 514.

In this circuit, for example, the gate electrode 5
14 and a counter electrode 513, a predetermined voltage is output from the operational amplifier 501, and the liquid crystal cell 5
11 is driven.

By the way, it is known that the liquid crystal cell 511 is deteriorated when a DC voltage is continuously applied to the liquid crystal cell 511. Therefore, a voltage of the opposite polarity must always be alternately applied to the liquid crystal cell 511 for each frame.

[0006] Taking one liquid crystal pixel as an example, m
(M is a positive integer) The voltage at the time of the frame is + Va (v) (Va is a positive real number) with respect to the counter electrode 513 of the liquid crystal cell 511.
Then, the voltage to be applied to the liquid crystal cell 511 in the next (m + 1) frame is -Va with respect to the counter electrode.
(V). This will be described with reference to FIGS.

FIG. 8 is a first characteristic diagram of the operational amplifier output versus the counter electrode voltage. In the figure, the voltage of the counter electrode 513 on the liquid crystal cell 511 side is kept constant, and the liquid crystal driving circuit 500
The operational amplifiers 501 to 50n have bipolar (0 (v) to +
2 shows a case where a wide range capable of outputting 2 Va (v) is provided and the liquid crystal cell 511 is driven.

This is because the voltage Vb of the counter electrode 513 is + V
The case where a is constant and the positive electrode potential + Va or the negative electrode potential -Va is alternately applied to the liquid crystal cell 511 is shown.

FIG. 9 is a second characteristic diagram of the operational amplifier output versus the counter electrode voltage. This figure shows that the voltage Vb of the counter electrode 513 is alternately changed to 0 (v) and + Va (v), and the voltage Vb is synchronized with the operational amplifiers 501 to 50.
The output voltage of n also changes to + Va (v) and 0 (v).

In this case, the output range of the operational amplifiers 501 to 50n is 0 (v) to + Va (v), which is half that in the case where the voltage Vb of the counter electrode 513 is fixed at + Va.

Next, the details of the liquid crystal driving circuit and the liquid crystal display corresponding to the first characteristic diagram shown in FIG. 8 will be described. FIG. 10 is a detailed circuit diagram of the liquid crystal drive circuit and the liquid crystal display. This is extracted from the circuits related to the operational amplifiers 501 and 502 in FIG. 7 as an example. Therefore, the connection is the same for the other operational amplifiers 503 and the like.

The outputs of the operational amplifiers 501 and 502 are output to the sources of the transistors 521 and 522 via the changeover switch 520. The liquid crystal cell 523 is connected between the counter electrode 513 and the drain of the transistor 521, and the liquid crystal cell 524 is connected between the counter electrode 513 and the drain of the transistor 522.

The operational amplifier 501 always outputs a high level (+2 Va (v)) signal when an external input signal is input, and the operational amplifier 502 always outputs a low level (0 (v) when an external input signal is input). )) It is configured to output a signal.

That is, the operational amplifier 501 is used exclusively for start-up, and the operational amplifier 502 is used exclusively for start-up. Then, the changeover switch 520 switches and outputs the high level signal and the low level signal alternately at predetermined time intervals. Also,
The potential of the counter electrode 513 is + Va (v).

According to this configuration, for example, when a voltage of +2 Va (v) output from the operational amplifier 501 is applied to the source of the transistor 521 via the changeover switch 520, a predetermined gate voltage is applied to the gate of the transistor 521. At this point, a voltage of + Va (v) is applied to the liquid crystal cell 523.

On the other hand, 0 output from the operational amplifier 502
When the voltage (v) is applied to the source of the transistor 521 via the changeover switch 520, the liquid crystal cell 523 has a voltage of -V when a predetermined gate voltage is applied to its gate.
The voltage of a (v) is applied.

Next, the circuits of the operational amplifiers 501 to 50n will be described. FIG. 11 is a circuit diagram of an example of a conventional operational amplifier.

This operational amplifier is the same as that shown in FIG. 9 of the conventional example of Japanese Patent Application Laid-Open No. 8-56128.

The conventional operational amplifier comprises a pair of an operational amplifier 501 dedicated for starting and an operational amplifier 502 dedicated for falling.

The operational amplifier 501 dedicated to start-up is + 2V
an N-channel FET having a power supply terminal 51 to which a (v) is applied and a power supply terminal 52 to which 0 (v) is applied, having a source connected in common and gates connected to signal input terminals 61 and 62, respectively; (Field Effect Transi
(stor) 71, 72, a constant current source 91 having one end connected to the power supply terminal 52, the other end connected to the sources of the N-channel FETs 71, 72, and a gate and a drain connected to the drain of the N-channel FET 71. Are connected to the power supply terminal 51, a source is connected to the power supply terminal 51, and the gate is a P-channel FET 7.
P-channel F connected to the gate and drain of N-channel FET 72 and the drain is connected to the drain of N-channel FET 72
An ET 74; a P-channel FET 601 having a gate connected to the drains of the N-channel FET 72 and the P-channel FET 74 and a source connected to the power supply terminal 51; and a constant current source 602 connected between the drain of the P-channel FET 601 and the power supply terminal 52. Consists of

On the other hand, the operational amplifier 502 dedicated to falling is
P-channel FET 78 having a power supply terminal 53 to which + 2Va (v) is applied and a power supply terminal 52 to which 0 (v) is applied, having a source connected in common, and gates connected to signal input terminals 63 and 64, respectively. , 79, one end is connected to the power supply terminal 52, the other end is connected to the sources of the P-channel FETs 78, 79, the gate and the drain are connected to the drain of the P-channel FET 78, and the source is the power supply terminal. An N-channel FET 80 connected to the N-channel FET 53; a source connected to the power supply terminal 53;
An N-channel FET 81 connected to the gate and the drain of the ET 80 and a drain connected to the drain of the P-channel FET 79, and an N-channel FET connected to the drains of the N-channel FET 81 and the P-channel FET 79 and the source connected to the power supply terminal 53 Channel FET 603
And the drain of the N-channel FET 603 and the power supply terminal 52
And a constant current source 604 connected therebetween.

The operational amplifier 501 dedicated to startup is such that when a voltage difference between the voltages applied to the signal input terminals 61 and 62 is input, the voltage output from the output terminal 95 rises.

On the other hand, when the difference voltage between the voltages applied to the signal input terminals 63 and 64 is input to the operational amplifier 502,
That is, the voltage output from the output terminal 96 falls.

FIG. 12 is a schematic explanatory view showing the dot inversion operation. As shown in the figure, voltages having different polarities are alternately applied to adjacent liquid crystal cells.

According to the dot inversion driving, it is easy to obtain high image quality.

[0026]

However, when the opposing electrode is kept constant and the operational amplifier outputs 0 (v) to +2 Va (v), the voltage of the operational amplifier is twice the voltage Va applied to the liquid crystal cell. However, it is difficult to miniaturize the high-voltage transistor, and the area of the liquid crystal driving circuit becomes large, and it is difficult to reduce the area.

The counter electrode is set to 0 (v) and + Va
When the voltage is alternately changed to (v), the voltage of the counter electrode is set to 1
There is a problem that the image quality of the liquid crystal is deteriorated (screen flickers) because the image is shaken up and down for each frame.

Further, when the outputs of the operational amplifiers exclusively for start-up and fall are switched by a changeover switch and the output is applied to the liquid crystal cell, each operational amplifier has only the capability of starting or lowering. Therefore, dot inversion driving is possible when driving the liquid crystal cell, but there is a problem that source line inversion (inversion for each adjacent line) for low power consumption is impossible.

That is, in the case of the dot inversion drive, a large current flows during the inversion.

Further, Japanese Patent Application Laid-Open No. 4-236514 discloses that
A target signal is obtained by synthesizing outputs obtained from a circuit driven at the ground level and half the power supply voltage level and a circuit driven at a half power supply voltage level and the power supply voltage level. A circuit is disclosed.

In this circuit, each circuit is connected to 1 / power supply voltage.
It can be driven at two levels.

On the other hand, Japanese Patent Application Laid-Open No. 62-257196 discloses a matrix display panel having a circuit for separately outputting a voltage lower than a target output voltage and a circuit for adding a required remaining voltage to the output voltage. A driving method is disclosed.

According to these prior arts, since the power supply voltage can be reduced, the circuit can be downsized. However, these circuits cannot be used directly in the above-described liquid crystal drive circuit, and However, this does not mean that the size of the liquid crystal drive circuit can be reduced, the image quality of the liquid crystal can be prevented from being deteriorated, and the source line can be inverted.

Further, another prior art of this kind is disclosed in
No. 24919 and JP-A-62-237432.

It is therefore an object of the present invention to provide a liquid crystal driving circuit capable of miniaturizing a circuit, preventing deterioration of liquid crystal image quality and inverting a source line.

[0036]

According to the present invention, a first power supply voltage and a second power supply voltage lower than the first power supply voltage are supplied, and a first output voltage is supplied to an input signal. And a second output for receiving the second power supply voltage and a third power supply voltage having a lower potential than the second power supply voltage and generating a second output voltage in response to an input signal. Voltage generating means, switching means for alternately switching the first output voltage and the second output voltage at predetermined time intervals and outputting the same, and alternately switching voltages output from the switching means being one of them. It comprises two liquid crystal display elements applied to a voltage input terminal, and a voltage having the same potential as the second power supply voltage is applied to the other voltage input terminal of each of the two liquid crystal display elements. And

According to another aspect of the present invention, the first and second output voltage generating means include an amplifying means for amplifying the input signal, and a rise time and a rise time of a signal output from the first amplifying means. Output control means for shortening the fall time.

According to the present invention, the power supply voltage applied to each of the first and second output voltage generating means is halved from the conventional one. Further, since the second power supply voltage corresponding to the counter electrode does not change with respect to the first and second power supply voltages, it is possible to prevent the image quality of the liquid crystal from deteriorating.

According to another aspect of the present invention, the rise time and the fall time of the output signal can be shortened. For example, after outputting a predetermined positive voltage signal, a positive voltage signal lower than that voltage is output. It is possible to output continuously. This allows source line inversion.

[0040]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The same components as those in the related art are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is a block diagram of a preferred embodiment of a liquid crystal drive circuit according to the present invention. The liquid crystal drive circuit includes a first operational amplifier 10 and a second operational amplifier 11 as a pair.

Then, a voltage of +2 Va (v) is applied to the power supply terminal 1 of the first operational amplifier 10, and a voltage of + Va (v) is applied to the power supply terminal 2. Similarly, a voltage of + Va (v) is applied to the power supply terminal 2 of the second operational amplifier 11, and a voltage of 0 (v) is applied to the power supply terminal 3.

Therefore, +2 Va (v) is output as a high (H) level voltage and + Va (v) is output as a low (L) level voltage from the first operational amplifier 10 in response to an external input signal. Similarly, the second operational amplifier 11 outputs + Va (v) as a high (H) level voltage and 0 (v) as a low (L) level voltage in response to an external input signal.

Next, a circuit in a state where the liquid crystal driving circuit and the liquid crystal cell are connected will be described. FIG. 2 is a circuit diagram showing a state where the liquid crystal drive circuit and the liquid crystal cell are connected.

The liquid crystal driving circuit comprises first and second operational amplifiers 10 and 11 and a changeover switch 520. One of the output sides of the changeover switch 520 is connected to a transistor 521 and a liquid crystal cell 523. Switch 5
The transistor 522 and the liquid crystal cell 524 are connected to the other output side of the transistor 20.

Further, +2 Va (v) is applied to the power supply terminal 1,
A voltage of + Va (v) is applied to the power terminal 2, and a voltage of 0 (v) is applied to the power terminal 3.

Further, the source of the transistor 521 is connected to one output side of the changeover switch 520, the drain of the transistor 521 is connected to one terminal of the liquid crystal cell 523, and the other terminal of the liquid crystal cell 523 is connected to the counter electrode 5
13 is connected. Similarly, the source of the transistor 522 is connected to the other output side of the changeover switch 520,
The drain of the transistor 522 is connected to one terminal of the liquid crystal cell 524, and the other terminal of the liquid crystal cell 524 is connected to the counter electrode 513.

Further, + Va (v) is applied to the counter electrode 513.

Next, the operation of this circuit will be described.
It is assumed that the changeover switch 520 is switched so that the outputs of the operational amplifiers 10 and 11 are output as they are.

Now, the H level voltage +
When 2Va (v) is output, + 2Va (v) is applied to the drain of the transistor 521. Therefore,
When a gate voltage is applied to the gate of the transistor 521, + Va (v) is applied to the liquid crystal cell 523. Thus, the liquid crystal cell 523 is driven.

On the other hand, the L level voltage +
When Va (v) is output, + Va (v) is applied to the drain of the transistor 521. Therefore, when a gate voltage is applied to the gate of the transistor 521, 0 (v) is applied to the liquid crystal cell 523. As a result, the liquid crystal cell 523 is not driven.

The H level voltage +
When Va (v) is output, + Va (v) is applied to the drain of the transistor 522. Therefore, when a gate voltage is applied to the gate of the transistor 522, 0 (v) is applied to the liquid crystal cell 524. As a result, the liquid crystal cell 523 is not driven.

On the other hand, the L level voltage 0
When (v) is output, −Va (v) is applied to the drain of the transistor 522. Therefore, when a gate voltage is applied to the gate of the transistor 522, -Va (v) is applied to the liquid crystal cell 524. Thus, the liquid crystal cell 523 is driven.

The changeover switch 520 is connected to the liquid crystal cell 523.
Is driven at + Va (v), the liquid crystal cell 524 becomes −V
Switching is performed so as to be driven by a (v), and this is alternately switched at regular intervals.

As described above, the voltage applied to the operational amplifiers 11 and 12 can be reduced to half of the conventional voltage, that is, + Va (v). Therefore, the circuit area can be reduced and the circuit can be downsized.

Further, since the voltage of the counter electrode 513 can be kept constant, it is possible to prevent the image quality of the liquid crystal from deteriorating.

Next, the circuit configuration of the operational amplifiers 10 and 11 will be described. FIG. 3 is a circuit diagram of a first embodiment of the operational amplifier.

This circuit is a circuit described in Japanese Patent Application Laid-Open No. 8-56128 (FIGS. 1 and 2 of the same).
Is the same as

The operational amplifier 10 has a power supply terminal 51 to which + 2Va (v) is applied and a power supply terminal 52 to which + Va (v) is applied. The sources are connected in common, and the gates are connected to the signal input terminal 61, respectively. N-channel FET connected to 62
71 and 72; a constant current source 91 having one end connected to the power supply terminal 52 and the other end connected to the sources of the N-channel FETs 71 and 72;
A P-channel FET 73 connected to the drain of the power supply terminal 71 and a source connected to the power supply terminal 51;
1, the gate is connected to the gate and drain of the P-channel FET 73, and the drain is N-channel FE
P-channel FET 74 connected to the drain of T72
The source is connected to the power supply terminal 51, the gate is the drain of the N-channel FET 72 and the P-channel FET 74
A P-channel FET 75 connected to the drain of the P-channel FET, one end connected to the power supply terminal 52, and the other end connected to the P-channel FET 7
5, a constant current source 92 connected to the drain, a source connected to the power supply terminal 51, and a gate connected to the N-channel FET 72.
And a drain of the P-channel FET 74, a drain of which is connected to the signal output terminal 95, a source of which is connected to the drain of the P-channel FET 76, a gate of which is connected to a drain of the P-channel FET 75, And a P-channel FET 77 connected to the power supply terminal 52.

On the other hand, the operational amplifier 11 has a power supply terminal 52 to which + Va (v) is applied and a power supply terminal 53 to which 0 (v) is applied. The sources are commonly connected, and the gates are signal input terminals. P-channel FET connected to 63, 64
A constant current source 93 having one end connected to the power supply terminal 52 and the other end connected to the sources of the P-channel FETs 78 and 79;
An N-channel FET 80 connected to the drain of the power supply terminal 78 and a source connected to the power supply terminal 53;
3, the gate is connected to the gate and the drain of the N-channel FET 80, and the drain is the P-channel FE.
N-channel FET 81 connected to the drain of T79
The source is connected to the power supply terminal 53, the gate is the drain of the P-channel FET 79 and the N-channel FET 81
An N-channel FET 82 connected to the drain of the N-channel FET 82, one end connected to the power supply terminal 52, and the other end connected to the N-channel FET 8
2, a source connected to the power supply terminal 53, and a gate connected to the P-channel FET 79.
And an N-channel FET 83 whose drain is connected to the signal output terminal 96, whose source is connected to the drain of the N-channel FET 83, whose gate is connected to the drain of the N-channel FET 82, And a P-channel FET 84 connected to the power supply terminal 52.

Next, the operation of this circuit will be described.
The operational amplifier 10 includes a differential amplifier composed of FETs 71 to 74 and an output control circuit composed of FETs 75 to 77. In accordance with the signal voltage input to the signal input terminals 61 and 62, the output voltage level to the gates of the P-channel FETs 75 and 76 changes, and the gate voltage of the P-channel FET 77 also changes.

In this state, if the signal voltage input to the signal input terminal 62 is higher in level than the signal voltage input to the signal input terminal 61, the N-channel F
The connection point between the drain of the ET 72 and the drain of the P-channel FET 74, that is, the gate voltages of the P-channel FETs 75 and 76, becomes low, and the P-channel FET 77 connected to the drain of the P-channel FET 75 and the other end of the constant current source 92. Gate voltage becomes higher.

Here, the operating states of the P-channel FETs 76 and 77 are such that the P-channel FET 76 can pass a large current and the P-channel FE
T77 is in a state where a small amount of current can flow. Therefore, when a current flows from the high-order power supply terminal 51 to the signal output terminal 95 of the operational amplifier, the potential of the signal output terminal 95 rapidly increases.

When the signal voltage input to the signal input terminal 62 is lower in level than the signal voltage input to the signal input terminal 61, the P-channel FETs 75 and 7
6, the gate voltage of the P-channel F
The gate voltage of ET77 decreases.

Here, the operating states of the P-channel FETs 76 and 77 are such that the P-channel FET 76 cannot flow much current and the P-channel FET 77 can flow large current. The supply of current from the power supply terminal 51 is interrupted,
Conversely, the lower power supply terminal 52
, The potential of the signal output terminal 95 rapidly drops.

As described above, in the present embodiment, when the output potential rises, a current flows from the higher power supply terminal 51 to the signal output terminal 95 via the P-channel FET 76 in a state where a large current flows. The output voltage of the signal output terminal 95 rapidly rises, and when the output voltage falls, a large current flows through the P-channel F
From the signal output terminal 95 to the lower terminal 5 via ET77.
2, the output voltage of the signal output terminal 95 immediately drops.

As a result, both the rise time when the output voltage of the signal output terminal 95 rises and the fall time when the output voltage falls are greatly reduced, and the response speed of the operational amplifier is further improved.

That is, according to the operational amplifier 10,
For example, after outputting the voltage of +7 (v),
(V) can be output. This allows source line inversion.

This was impossible with the conventional operational amplifier shown in FIG. +7 (v) voltage followed by +5
This is because the output signal of (v) needs to fall by +2 (v).

Therefore, conventionally, after the voltage of +7 (v), +
When 5 (v) is output, −7 (v) voltage is followed by −
3 (v) was output. The liquid crystal display does not change when +3 (v) is applied or -3 (v) is applied.

FIG. 4 is a schematic diagram showing source line inversion. As shown in the figure, the vertically arranged liquid crystal cells have the same polarity, and the adjacent liquid crystal cells have the opposite polarity. These poles are alternately switched by the changeover switch 520 described above.

By adopting this source line inversion, the number of times a large current flows at the time of inversion can be reduced, so that power consumption can be reduced.

The operation of the operational amplifier 11 is the same as that of the operational amplifier 10 except that the P-type FET is replaced with the N-type FET and the N-type is replaced with the P-type FET.

FIG. 5 is a circuit diagram of a second embodiment of the operational amplifier. This operational amplifier differs from the first embodiment in that each FET is constituted by an FET with a back gate (substrate terminal). Each back gate is connected to each source.

In the figure, the number of each FET is indicated by three digits by adding 1 to the beginning of the number assigned to each FET of the first embodiment. For example, the FET 71 of the first embodiment corresponds to the FET 171 of the second embodiment.

As described above, by providing each FET with a back gate, the range of the output voltage, that is, the dynamic range can be expanded as compared with the first embodiment.

FIG. 6 is a circuit diagram of a third embodiment of the operational amplifier. The third embodiment is a modification of the second embodiment. In this embodiment, as in the second embodiment, each FE
The number of T is 2 prefixed to the number given to each FET of the first embodiment.
Is displayed in three digits. For example, the FET 71 of the first embodiment corresponds to the FET 271 of the third embodiment.

This operational amplifier differs from the second embodiment in that the back gates of the FETs 271, 272, 278, 279 are connected to the power supply terminal 252.

The third embodiment can also expand the dynamic range as compared with the first embodiment.

The FET according to the first to third embodiments
The dynamic range of the operational amplifier can be further expanded by changing the ion implantation amount so as to decrease the absolute value of the gate voltage threshold value of the operational amplifier.

On the other hand, output stage FETs 76, 77, 83, 8
4,176,177,183,184,276,27
The dynamic range of the operational amplifier can also be expanded by changing the ion implantation amount so as to lower the absolute value of the gate voltage threshold value of only 7,283,284.

[0082]

According to the present invention, a first power supply voltage and a second power supply voltage having a lower potential than the first power supply voltage are supplied to generate a first output voltage in response to an input signal. Means, the second power supply voltage and a third voltage lower than this voltage.
A second output voltage generating means for generating a second output voltage in response to an input signal supplied from the power supply voltage, and alternately switching the first output voltage and the second output voltage at predetermined time intervals Switching means for outputting the two liquid crystal display elements which are alternately switched and output from the switching means and are applied to one of the voltage input terminals, respectively. Since the liquid crystal drive circuit is configured so that a voltage having the same potential as the second power supply voltage is applied to the voltage input terminal of the first embodiment, the circuit can be downsized and the image quality of the liquid crystal can be prevented from deteriorating.

According to another aspect of the present invention, the first
And the second output voltage generating means includes an amplifying means for amplifying the input signal and an output control means for shortening the rise time and the fall time of the signal output from the first amplifying means. , The source line can be inverted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a preferred embodiment of a liquid crystal drive circuit according to the present invention.

FIG. 2 is a circuit diagram showing a state where the liquid crystal drive circuit and a liquid crystal cell are connected.

FIG. 3 is a circuit diagram of a first embodiment of an operational amplifier of the liquid crystal drive circuit.

FIG. 4 is a schematic explanatory diagram showing source line inversion of the liquid crystal drive circuit.

FIG. 5 is a circuit diagram of a second embodiment of the operational amplifier of the liquid crystal drive circuit.

FIG. 6 is a circuit diagram of a third embodiment of the operational amplifier of the liquid crystal drive circuit.

FIG. 7 is a main part circuit diagram of a conventional liquid crystal drive circuit and a liquid crystal display.

FIG. 8 is a first characteristic diagram of a conventional operational amplifier output versus a counter electrode voltage.

FIG. 9 is a second characteristic diagram of a conventional operational amplifier output versus a counter electrode voltage.

FIG. 10 is a detailed circuit diagram of a conventional liquid crystal drive circuit and a liquid crystal display.

FIG. 11 is a circuit diagram of an example of a conventional operational amplifier.

FIG. 12 is a schematic explanatory view showing a dot inversion operation.

[Explanation of symbols]

 1-3 Power supply terminal 10, 11 Operational amplifier 513 Counter electrode 520 Changeover switch 523, 524 Liquid crystal cell

Claims (8)

[Claims] A first output voltage generating means for receiving a first power supply voltage and a second power supply voltage having a lower potential than the first power supply voltage and generating a first output voltage in response to an input signal; Power supply voltage and a third power supply voltage having a lower potential than the power supply voltage, a second output voltage generating means for generating a second output voltage in response to an input signal, and the first output voltage and the second output voltage Switching means for alternately switching the output voltage at predetermined time intervals and outputting the same, and two liquid crystal display elements each of which alternately switching voltages output from the switching means are applied to one of the voltage input terminals. And a voltage having the same potential as the second power supply voltage is applied to the other voltage input terminal of each of the two liquid crystal display elements. 2. The first and second output voltage generating means include an amplifying means for amplifying the input signal, and an output for reducing a rise time and a fall time of a signal output from the first amplifying means. 2. The liquid crystal drive circuit according to claim 1, further comprising control means. 3. The amplifying means has first and second transistors whose sources are commonly connected and whose gates receive first and second external input signals, respectively, and one end of which has the second power supply voltage. Is applied, the other end of which is connected to the sources of the first and second transistors, a first low current source, the gate and the drain of which are connected to the drain of the first transistor, and the source is the first or second source. A third transistor to which a third power supply voltage is applied, a source to which the first or third power supply voltage is applied, a gate connected to the gate of the third transistor, and a drain connected to the second transistor 3. The liquid crystal drive circuit according to claim 2, further comprising a fourth transistor connected to the drain of the second transistor and outputting an amplified signal from the drain. 4. The liquid crystal driving circuit according to claim 3, wherein each of the first to fourth transistors has a back gate connected to each source. 5. The output control means includes: a fifth transistor to which a signal amplified by the amplification means is input to a gate, and the first or third power supply voltage is applied to a source;
The second power supply voltage is applied to one end thereof, the second constant current source having the other end connected to the drain of the fifth transistor, and the source is applied with the first or third power supply voltage, A sixth transistor having a gate to which a signal amplified by the amplifying means is input and a first or second output voltage being output from a drain, a source connected to a drain of the sixth transistor, and a gate connected to a sixth transistor. 5. The liquid crystal drive circuit according to claim 2, further comprising: a seventh transistor connected to a drain of said fifth transistor, said drain being applied with said second power supply voltage. 6. The liquid crystal driving circuit according to claim 3, wherein each of the fifth to seventh transistors has a back gate connected to each source. 7. The liquid crystal driving circuit according to claim 4, wherein the transistor is formed by changing an ion implantation amount so as to reduce an absolute value of a gate voltage threshold. 8. The liquid crystal drive circuit according to claim 6, wherein the sixth and seventh transistors are formed by changing the amount of ion implantation so as to reduce the absolute value of the gate voltage threshold.