JPH04182805A - Programmable controller - Google Patents

Abstract

PURPOSE:To load, save, and edit a user program with simple constitution and to reduce the cost by providing a shared memory in a high-function unit and transferring a sequence program between a CPU unit and the high-function unit. CONSTITUTION:The sequence program is loaded, saved, and edited by a programming device 10. In this case, when input operation is performed from the side of the device 10, each high-function unit 40 sends a command requesting a read of the program to the side of the CPU unit 20 by using the identification code of the CPU unit 20 as a transmission destination identification code 41a stored in the shared memory 41 and its identification code as a transmission origin identification code 41b. On the side of the unit 20, the user program stored in a memory unit 25 or internal program memory 24 is read out and transferred to the requesting unit 40. Consequently, not only the sequence program of the unit 20, but also programs of respective units 40 can be loaded, saved, and edited from the device 10 and the cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a programmable controller, and particularly to a programmable controller equipped with a programmable high-performance unit.

<Prior Art> As a conventional device of this type, the one shown in FIG. 4 is known.

Now, the overall configuration will be explained with reference to the same figure.
The programming device 10 is a program development device that can load, save, and edit programs to the CPU unit 20 and multiple high-performance units 40, and connects the connection terminal 12 of the connection cable 11 to the programming device provided in the CPU unit 20. The CPU unit 20 can be connected by inserting it into the connector 27 or the programming device connection connector 47 provided on the high-performance unit 40.
It is configured so that programs for the high-performance unit 40 can be developed.

In this case, the CPU unit 20 is provided with a built-in memory (not shown) and a memory unit installation window 26 into which an external memory unit 25 can be inserted, and the sequence program executed by the CPU unit 20 is It can be stored in the built-in memory or the memory unit 25.

Further, the high-performance unit 40 is configured such that a sequence program executed by the high-performance unit 40 can be stored in a built-in memory (not shown).

In addition, in FIG. 4, 30 is a base unit, and a unit connection connector 3 to which a high-performance unit 40 is connected.
A plurality of 2 are provided. Further, 48 is a switch for setting a high-performance unit number, and 60 is a power supply unit.

<Problem to be solved by the invention> However, in the conventional device as described above, the CPU
Both the unit 20 and the high-performance unit 40 have their own built-in memory, and each high-performance unit 40 and the CPU
Since the unit 20 must be provided with a connector 47 or 27 for connection to the programming device 10, the program cannot be loaded.

When saving and editing, it is necessary to connect the connection terminal 12 of the connection cable 11 to the connectors 27 and 47 of the CPU unit 20 and each high-performance unit 40, and load, save, and edit each program while changing the connection terminal 12 of the connection cable 11.
Therefore, troublesome work is required, and the CPU unit 20 and each high-performance unit 40 must be equipped with a built-in memory and connection connectors 27, 47, resulting in high costs.

In addition, if each built-in program memory is configured with volatile memory such as static RAM, it is necessary to provide a backup circuit consisting of a battery or the like so that the program can be retained even when the power is turned off, which is also a cause of high costs. It became.

This invention was made in view of the conventional problems as described in ``2'', and its purpose is to provide a CPU with a simple configuration.
To provide a programmable controller that can load, save, and edit user programs executed in units and high-performance units, and can be manufactured at low cost.

<Means for Solving the Problems> In order to achieve the above object, the present invention has a CPU unit and a high-performance unit connected to the CPU unit, and the CPU unit is programmed by an external programming device connected to the CPU unit. and a programmable φ controller that can load, save, and edit sequence programs executed in the high-function unit, which is connected to the CPU unit and receives input from the programming device for the CPU unit and the high-function unit. A storage means in which a sequence program is stored; and a shared memory provided in the high-performance unit and capable of transmitting and receiving the sequence program stored in the storage means between the CPU unit and the high-performance unit. Features.

<Operation> In this invention, sequence programs executed in the CPU unit and each high-function unit can be loaded, saved, and edited from a programming device connected to the CPU unit, and these developed or modified sequence programs can be stored on the CPU unit side. is stored in the storage means. Each high-performance unit can import its own sequence program stored in the storage means via the shared memory.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. The overall configuration of this embodiment is exactly the same as that used in the explanation of the conventional example, so the same parts are given the same reference numerals and detailed explanation thereof will be omitted.

FIG. 1 is a block diagram showing the electrical hardware configuration of this embodiment.

First, to explain the configuration, the programming device 10 has a CR
A program development device that has a communication means with a display such as T, a CPU unit 20, and each high-performance unit 40, and is capable of loading, saving, and editing sequence programs executed by the CPU unit 20 and each high-performance unit 40. It is.

The CPU unit 20 connected to the programming device 10 via the connection cable 11 has a calculation execution unit 2.
1 and an I10 data memory 23 connected to the arithmetic execution unit 2 via an internal bus 22 and a built-in program memory 22.
, and is configured to be connectable to an external memory unit 25.

Here, the arithmetic execution unit 21 is composed of a microprocessor or the like, is a part that performs arithmetic operations according to a sequence program stored in the built-in program memory 22 or the memory unit 25, and also has a communication function with the programming device 10.

The I10 data memory 23 is a memory that stores input data and calculation results in the calculation execution unit 21.

The built-in program memory 24, like the memory unit 25, is a memory that stores a sequence program input from the programming device 10. In addition, the memory 24
If it is configured with volatile memory such as static RAM, it must be backed up with a battery or the like so that the sequence program can be retained even when the power is turned off.

On the other hand, the memory unit 25 is a non-volatile memory, and the CP
It is not built into the U unit 20 and can be replaced.

Next, 30 is the base unit I, and the CPU unit 20
C which sends and receives data between the high-performance unit 40 and
Supply voltage from the PU bus 31 and the power supply unit 60 (see Figure 4) to the CPU unit 20 and each high-performance unit 4.
A backboard with a connector (not shown) that connects to 0.

A plurality of high-performance units 40 are connected to the CPU bus 31 in this base unit 30 via a connection bus 48.
are connected, and each high-performance unit 40 has a shared memory 41 .
Arithmetic execution unit 42. Contains built-in program memory 43.

Here, the shared memory 41 is a memory for exchanging data between the CPU unit 20 and the high-performance unit 40,
It is accessible from any of the arithmetic execution unit 21 of the CPU unit 20, the arithmetic execution unit 42 of another high-performance unit 40, and the arithmetic execution unit 42 included in its own high-performance unit, and can read and write to the shared memory 41. can be performed by each calculation execution unit.

That is, although FIG. 2 is a detailed diagram of the shared memory 41,
The shared memory 41 includes a sending light identification code field 41a, a sending light identification code field 4]b, a command area 41C, and a data area 4.
1d is provided.

The sending light identification code specifies the destination of the command and data, and the sending light identification code indicates the sending source of the command and data. Note that the types of identification codes include CPU unit 20. Each high-performance unit 40. There is a programming device 10, etc., and each high-function unit is identified using the high-function unit t-No setting switch 4.
The unit number 1-No.8 (see FIG. 4) is used.

Further, the command area 41c is used for writing programs, requests for reading, and writing data.

A designation of a read request or a response command to the request command is stored.

Furthermore, data and programs designated by commands are stored in the data area 41d.

On the other hand, the built-in program memory 4 in the high-performance unit 40
3 stores a sequence program to be executed by the high-performance unit 40, and if it is configured with a volatile memory such as a static RAM, a backup circuit such as a battery is provided so that the program can be saved even when the power is turned off. It is provided.

This is the configuration of this embodiment, and its operation will be explained next.

First, when attempting to load, save, and edit a sequence program executed by the CPU unit 20 or the high-performance unit 40 using the programming device 10, the connection cable 11. Connection terminal 1 provided at the tip of
2 into the connector 27 of the CPU unit 20, and the memory unit 25 into the memory unit mounting window 26, and perform input operations from the programming device 10 side.

This allows the memory unit 25 to load, save, and edit programs used by the CPU unit 20 and each high-performance unit 40, and these programs are stored in the memory unit 25.

In this case, similar content can also be stored in the built-in program memory 24.

By the way, in this embodiment, the shared memory 41 of the high-performance unit 40 is configured as shown in FIG. The source of the command and data can be specified by the source identification code stored in the identification code field 41b.
1c can store requests for program writing and reading, designation of data writing and reading requests, and response commands to request commands, and data area 41d can store data and programs specified by commands. can.

Therefore, when each high-performance unit sends a program read request command to the CPU unit 20 using the identification code of the CPU unit 20 as the destination identification code and its own identification code as the source identification code,
In response, the CPU unit 20 side reads the user program used in the corresponding high-function unit 40 stored in the memory unit 25 or built-in program memory 24, and executes the requested high-performance uni-soto 4.
Transfer to the 0 side. In this case, the identification code of the high-performance unit at the transfer destination is the destination identification code, and the CPU unit 20
The program will be transferred using the identification code as the source identification code.

Note that FIG. 3 shows a shared memory 51 in a conventional example. In this case, the shared memory 51 has an input data area for exchanging data between the CPU unit 20 and the high-performance unit 40. 51a and output data area 51
It is composed of b.

The data in the input data area 51a is read into the input part of the I10 data memory 23 of the CPU unit 20, and the data in the I10 data memory 23 of the CPU unit 20 is read into the output data area 51b.
Although the CPU unit 20 and the high-performance unit 40 are configured to write the calculation results in the data memory 23, only data can be transferred between the CPU unit 20 and the high-performance unit 40.

However, in this embodiment, as described above, the shared memory 41 is configured as shown in FIG. 2, and can transfer not only data but also programs.

Therefore, when a program is written from the programming device 10 to the memory unit 25 or the built-in program memory 24 connected to the CPU unit 20, when there is a request from each high-function unit 40, the CPU unit 20 writes a program to each high-function Since programs can be transferred to the units 40, each high-performance unit 40 can execute programs even if it does not have a built-in program memory 43.

As explained above, in this embodiment, the programming device 10 connected to the CPU unit 20 can load, save, and edit not only the sequence program of the CPU unit 20 (but also the programs of each high-function unit 40). There is no need to connect the connection terminal 12 of the connection cable 11 to the connection connector 47 of each high-performance unit 40 every time a program is loaded, saved, or edited for each high-performance unit as in the conventional case.

Program creation efficiency can be greatly improved compared to the conventional method.

In addition, each program can be stored centrally in the external memory unit 25 of the CPU unit 20.
Program changes associated with system changes can be efficiently performed.

In this embodiment, a multi-function programmable controller is realized (each high-function unit 40 is provided with a built-in program memory 43, and a connection connector 47 is also provided at the same time. The programs used in the functional units 40 are stored in the memory unit 25 and the built-in program memory 24, and can be transferred to each high-function unit 40 when necessary. In this case, the connector 47 for connecting the programming device is also not necessary. Therefore, with such a configuration,
In addition to the above-mentioned effects, there is no need to provide a backup circuit such as a battery to hold the program when the power is turned off in the built-in program memory 43, and a highly functional unit can be obtained at low cost.

Further, in this case, since there is no need to provide the connection connector 47 on the high-performance unit 40 side, the high-performance unit 40 can be obtained at low cost in this respect as well.

<Effects of the Invention> As explained above, the present invention provides a storage means that is connected to the CPU unit and can store sequence programs for the CPU unit and the high-performance units that are input from the programming device; The above-mentioned tJi' is provided in the high-performance unit and between the CPU unit and the high-performance unit.

Since a shared memory is provided that enables exchange of sequence programs stored in the device, sequence programs to be executed by each CPU unit and each high-performance unit can be loaded and saved from a programming device connected to the CPU unit. Easy to configure and edit CP
It has the advantage that it is possible to develop and change user programs to be executed by the U unit and the high-performance unit, and it is also possible to obtain this type of device at low cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the electrical hardware configuration of an embodiment to which the present invention is applied, Fig. 2 is an explanatory diagram of a shared memory used in this embodiment, and Fig. 3 is a shared memory of a conventional example. FIG. 4 is a perspective view showing the overall configuration of the programmable controller. 10...Programming device 11...Connection cable 12...Connection terminal 20...CPU unit 21...Calculation execution unit 23...I10 data memory 24...Built-in program memory 25...Memory Unit 27...Programming device connection connector 30...
-Base unit 31...CPU bus 40...High-performance unit 41...Shared memory 42...Arithmetic execution section 43...Built-in program memory

Claims (1)

[Claims] 1. Loading of a sequence program that has a CPU unit and a high-performance unit connected to the CPU unit, and is executed by the CPU unit and the high-performance unit by an external programming device connected to the CPU unit; A programmable controller capable of saving and editing, a storage means connected to the CPU unit and storing sequence programs for the CPU unit and the high-performance unit inputted from the programming device; A programmable controller comprising: a shared memory provided within the unit and capable of transmitting and receiving sequence programs stored in the storage means between the CPU unit and the high-performance unit.