JPH04180633A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
MOS (Metal Oxide Sem1cond) with D (Lightly Doped Drain) structure
) A so-called gate overlap LD, which is a transistor in which the gate electrode and the diffusion layer overlap.
D) A method of manufacturing a transistor, and a method of forming a T-shaped metal layer suitable for the method of manufacturing a gate-overlap LDD transistor.

[Conventional technology]

A conventional method for manufacturing gate-overlap LDD (LDD) transistors is described, for example, on page 12 of ``34th Semiconductor Technical Seminar Proceedings J,'' published in July 1990.

This is a method for manufacturing gate-overlap LDD (LDD) transistors using oblique rotational ion implantation, in which ions are implanted obliquely when forming a low-concentration diffusion layer, thereby implanting ions into the lower side of an already formed gate electrode. In this method, a diffusion layer is also inserted to overlap the gate electrode and the diffusion layer.

In addition, an inverted T-shaped gate electrode is formed on the semiconductor substrate,
There is also a method of manufacturing a gate overlap LDD transistor by performing ion implantation using this as a mask.

[Invention or problem to be solved]

However, with the conventional manufacturing method using oblique rotational ion implantation, it is not possible to arbitrarily control the impurity concentration of the diffusion layer and the dimensions in the depth and width directions.
The drawback is that there are significant restrictions depending on the film thickness and material of the gate electrode, and there is little freedom in designing the transistor. especially,
If the gate electrode is thin, ions may be implanted into the part that will become the channel, which can cause problems, so the gate electrode must be thicker than a certain value, which hinders the miniaturization of transistors. Ta.

In addition, in the manufacturing method using an inverted T-shaped gate electrode,
In particular, it is difficult to accurately control the cell length, and there are limits to miniaturization.

This invention was made by paying attention to the unresolved problems of the conventional technology, and has developed a gate-overlap LDD that does not cause a significant increase in cost and can easily be miniaturized. It is an object of the present invention to provide a method for manufacturing a transistor and a method for forming a T-shaped metal layer suitable for manufacturing a gate-overlap LDD transistor.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor device according to claim (1) is provided, in which the lower layer is made of polysilicon and the upper layer is made of a high melting point metal or its silicide on a semiconductor substrate on which a thin insulating film is laminated. a step of etching the semiconductor substrate on which the gate electrode is formed with an alkaline organic solution; and a step of performing low concentration diffusion by implanting ions into the etched semiconductor substrate from an oblique direction. a step of stacking polysilicon on the upper surface of the semiconductor substrate on which the low concentration diffusion layer has been formed and etching it back; and implanting ions into the semiconductor substrate after the etching back. and forming a high concentration diffusion layer.

Moreover, the invention described in claim (2) is the method for manufacturing a semiconductor device according to claim (1), in which etchback is performed with a bromine-based gas.

Furthermore, the invention according to claim (3) provides a step of forming a metal layer on the semiconductor substrate on which the thin insulating film is laminated, the lower layer side being made of polysilicon and the upper layer side being made of a high melting point metal or its silicide; The method further comprises a step of etching the semiconductor substrate on which the metal layer is formed using an alkaline organic solution.

[Effect]

A gate electrode consisting of a stack of polysilicon and a high-melting point metal or its silicide, or a gate electrode made of polysilicon alone when etched with an alkaline organic solution such as that used in a developer (for example, TMAH: tetramethylammonium hydroxydiene) The etching speed of polysilicon is much higher than that of etching the polysilicon layer, and the high melting point metal or its silicide or the oxide film on the semiconductor substrate are not damaged. This will be etched to form a gate electrode with a T-shaped cross section.

Then, when ions are implanted into the semiconductor substrate in this state while rotating from an oblique direction to form a low concentration diffusion layer, the ions are also implanted under the gate electrode without being blocked by the gate electrode.

Furthermore, when polysilicon is laminated on the semiconductor substrate and etched back, new polysilicon adheres to the sides of the polysilicon layer below the etched gate electrode, and the gate electrode returns to its original shape. It turns out.

Note that this etchback is performed using a bromine-based gas (bromine gas Br2 or hydrogen bromide HBr), as described in claim (2).
etc.), the selectivity ratio between the high melting point metal or its silicide and polysilicon will be 1.10 or more, so the reduction in the upper layer of the gate electrode will be minimal.

When ions are implanted into the semiconductor substrate in this state to form a highly concentrated diffusion layer, the ions are blocked by the gate electrode and do not enter the lower part of the semiconductor substrate. It is formed in a region outside the low concentration diffusion layer.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing the manufacturing process of a gate-overlapping DD transistor in an embodiment of the present invention.

First, on a semiconductor substrate 1 on which an oxide film 2 as a thin insulating film is laminated, the lower layer is made of polysilicon 4 with impurities (n+ or p+) added, and the upper layer is made of silicide of a refractory metal (for example, tungsten). Silicide W S
12, molybdenum silicide MoS L, etc.) 5 is formed through a known photo process or the like (
(See Figure 1 fat).

Next, the semiconductor substrate l on which the gate electrode 3 has been formed is processed using a developer solution such as TMAH (TMAH) as an alkaline organic solution.
Etching with tetramethylammonium hydroxydiene).

Then, when polysilicon alone is etched with TMAH, almost no polysilicon is etched, or when a so-called polycide structure in which polysilicon 4 and silicide 5 are stacked is etched with an alkaline organic solution. Since the etching rate of polysilicon 4 is much higher than that of oxide film 2 and silicide 5, it is possible to selectively etch polysilicon 4, and as a result of this etching, a T-shaped cross section is formed. A gate electrode 3 of the mold type is formed (FIG. 1(b)).
reference).

Next, phosphorus ions are implanted obliquely into the semiconductor substrate l to form a low concentration diffusion layer 6 (FIG. 1(C)).
reference).

In case 2, since the gate electrode 3 is T-shaped, the low concentration diffusion layer 6 can be inserted under the gate electrode 3 without passing through the inside of the gate electrode 3.

Therefore, it is easy to arbitrarily control the concentration and depth dimension of the low concentration diffusion layer 6, and the amount of overlap between the gate electrode 3 and the low concentration diffusion layer 6 can also be adjusted using polysilicon 4 and silicide. By appropriately selecting the film thickness of polysilicon 5 and the etching time of polysilicon 4, it can be controlled as desired.

After the desired low concentration diffusion layer 6 is formed, polysilicon 7 having the same shape as the polysilicon 4 and the impurities attached thereto is laminated on the semiconductor substrate I (see FIG. 1(d)). 7 is etched back to make the cross-sectional shape of the gate electrode 3 square (the original shape shown in FIG. 1(a)), and then arsenic ions are implanted using the gate electrode 3 as a mask to form a highly concentrated diffusion layer 8. (see FIG. 1(e)).

Note that the above etchback is desirably performed using a bromine gas, for example, bromine gas Br2, hydrogen bromide HBr, or the like.

This is because when a bromine-based gas is used, the selectivity between silicide 5 and polysilicon 7 becomes 110 or more, and the loss of the silicide 5 film can be minimized.

Since the high concentration diffusion layer 8 hardly penetrates under the gate electrode 3, as shown in FIG. 1 (el),
A low concentration diffusion layer 6 is formed inside the high concentration diffusion layer 8, and the gate electrode 3 and the diffusion layer overlap to form a gate overlap LDDH transistor.

Moreover, in this embodiment, it is possible to arbitrarily control the concentration and dimensions of the diffusion layer in the portion overlapping with the gate electrode 3, so the degree of freedom in design is increased.

Furthermore, when forming the T-shaped gate electrode 3 (see FIG. 1 (bl)) and when etching back the polysilicon 7, the silicide 5 is hardly reduced, so that the silicide 5 is Since the gate electrode 3 (see FIG. 1 (el)) has the same dimensions as the original mask, the gate length can be precisely controlled and miniaturization is easy.

Furthermore, compared to the conventional method of manufacturing a transistor with an LDD structure using sidewalls, the process is not particularly complicated, so there is no need for a significant increase in cost.

〔Effect of the invention〕

As explained above, according to the invention described in claim (1), it is possible to manufacture a DD transistor with gate overlap without causing a significant increase in cost compared to the conventional manufacturing method of an LDD transistor. Moreover, there are advantages in that the degree of freedom in design is high and miniaturization is easy.

In particular, if a bromine-based gas is used for etch-back as in the invention described in claim (2), the gate length can be controlled with high precision because the refractory metal or its silicide is not reduced.

Furthermore, the invention as set forth in claim (3) has the effect that a metal layer having a T-shaped cross section can be formed without causing reduction of the high melting point metal or its silicide on the upper layer side.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are T cross-sectional views showing the manufacturing process of a gate-overlapping DD transistor in an embodiment of the present invention.

Claims (3)

[Claims] (1) A step of forming a gate electrode on a semiconductor substrate on which a thin insulating film is laminated, the lower layer of which is made of polysilicon and the upper layer of which is made of a high melting point metal or its silicide; a step of etching with an alkaline organic solution; a step of performing ion implantation from an oblique direction into the etched semiconductor substrate to form a low concentration diffusion layer; and a step of forming a low concentration diffusion layer on the semiconductor substrate on which the low concentration diffusion layer is formed. The method is characterized by comprising the steps of stacking polysilicon on the upper surface and etching it back, and implanting ions into the etched back semiconductor substrate to form a high concentration diffusion layer. A method for manufacturing a semiconductor device. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the etch-back is performed using a bromine gas. (3) forming a metal layer on a semiconductor substrate on which a thin insulating film is laminated, the lower layer side of which is made of polysilicon and the upper layer side of which is made of a high melting point metal or its silicide; A method for manufacturing a semiconductor device, comprising the step of etching with an alkaline organic solution.