JPH04180257A - Method of mounting integrated circuit - Google Patents
Method of mounting integrated circuitInfo
- Publication number
- JPH04180257A JPH04180257A JP2310356A JP31035690A JPH04180257A JP H04180257 A JPH04180257 A JP H04180257A JP 2310356 A JP2310356 A JP 2310356A JP 31035690 A JP31035690 A JP 31035690A JP H04180257 A JPH04180257 A JP H04180257A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chips
- circuit board
- pad
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は集積回路（以後ＩＣと略す）チップの実装方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting an integrated circuit (hereinafter abbreviated as IC) chip.
［従来の技術］
第５図は、従来のテープキャリヤ方式によりプリント基
板上に実装したＩＣチップを示す断面図である。図にお
いて、（１）はプリント基板、（２）はＩＣチップ、（
３）はＩＣチップの信号接続端子部（以下パッドという
）、（４）はＩＣチップ（２）のパッド（３）とプリン
ト基板（１）とを接続するリード、（５）はプリント基
板（１）におけるＩＣチップ（２）間を接続する配線で
ある。[Prior Art] FIG. 5 is a sectional view showing an IC chip mounted on a printed circuit board using a conventional tape carrier method. In the figure, (1) is a printed circuit board, (2) is an IC chip, (
3) is the signal connection terminal part of the IC chip (hereinafter referred to as pad), (4) is the lead that connects the pad (3) of the IC chip (2) and the printed circuit board (1), and (5) is the printed circuit board (1). ) is the wiring that connects the IC chips (2).
次に動作について説明する。プリント基板上（１１に実
装されたＩＣチップ（２）において、プリント基板（１
１上の配線（５）を伝達してきた信号は、リード（４）
を経てパッド（３）から入力され、 ＩＣチップ（２）
内部の回路を伝搬しパッド（３）から出力され、プリン
ト基板（１）上の配線（５）に伝わる。Next, the operation will be explained. In the IC chip (2) mounted on the printed circuit board (11), the printed circuit board (1
The signal transmitted through the wiring (5) above 1 is connected to the lead (4)
input from the pad (3) through the IC chip (2)
It propagates through the internal circuit, is output from the pad (3), and is transmitted to the wiring (5) on the printed circuit board (1).
［発明が解決しようとする課題］
従来の半導体集積回路実装方法は、以上のように行われ
ているので、ＩＣ用パッケージ内あるいはプリント基板
上に複数個のＩＣチップ全てを平面的に実装しており実
装面積は個々のＩＣチップ面積の総和とＩＣチップ間を
接続するための配線に要する面積の和によって決定され
ていた。さらにＩＣ用パッケージ内、およびプリント基
板上の配線ルールの制約からも実装面積の縮小が困難に
なりつつあるという澗題点があった。[Problems to be Solved by the Invention] Conventional semiconductor integrated circuit mounting methods are performed as described above, so it is difficult to mount all of a plurality of IC chips in a two-dimensional manner within an IC package or on a printed circuit board. The mounting area of the IC chip is determined by the sum of the areas of the individual IC chips and the area required for wiring to connect the IC chips. Furthermore, there is a problem in that it is becoming difficult to reduce the mounting area due to restrictions on wiring rules within the IC package and on the printed circuit board.
この発明は上記のような問題点を解決するためになされ
たもので、ＩＣ用パッケージ内、あるいはプリント基板
上のＩＣを従来の方法よりさらに高密度に実装する半導
体集積回路実装方法を得ることを目的としている。This invention was made in order to solve the above-mentioned problems, and aims to provide a semiconductor integrated circuit mounting method that allows ICs to be mounted in an IC package or on a printed circuit board at a higher density than conventional methods. The purpose is
［課題を解決するための手段］
この発明にかかわる実装方法は、ＩＣチップの上に他の
ＩＣチップを搭載し、パッド同士を接続したものである
。[Means for Solving the Problems] In the mounting method according to the present invention, another IC chip is mounted on an IC chip, and the pads are connected to each other.
［作用］
この発明にあけるＩＣチップの実装方法は、ＩＣチップ
に他のＩＣチップを対向して搭載し、同一間隔で配置さ
れたパッド同士が接続され、ＩＣチップ間の配線を不要
とする。[Function] The IC chip mounting method according to the present invention mounts another IC chip on an IC chip facing each other, and pads arranged at the same interval are connected to each other, thereby eliminating the need for wiring between the IC chips.
［実施例］
以下この発明に係る半導体集積回路実装方法の一実施例
を図について説明する。[Embodiment] An embodiment of the semiconductor integrated circuit mounting method according to the present invention will be described below with reference to the drawings.
第１図はプリント基板上に実装したＩＣチップの断面図
、第２図は第１図に示す接合されたＩＣチップＡ−Ｂの
上面図、第３図は第２図に示すＩＣチップＢの裏面図で
ある。図において（１）、 （３）、 （４１゜（５）
は第５図の従来例におけるものと同等であるので説明を
省略する。（１１）はＩＣチップＡ、（１３）はＩＣチ
ップＢ、（１２）はＩＣチップＢ ＋１３）の接続パッ
ド、 ＋１４）はＩ’ＣチップＡ （ＩＩ）とＩＣチッ
プＢ （１３）を互いに接合させるためのバンブ、（１
５）はＩＣチップＡ Ｎｔｌのパッドである。第１図及
び第２図に示すごと（ＩＣチップＡ （ｉｌｌ、ｒｃチ
ップＢ （１３＋を縦方向に接合する構造により、プリ
ント基板（１）上での実装面積の削減がはかれる。ここ
でＩＣチップＡ （１１）は従来例におけるＩＣチップ
（２）にパ・ソド（１５）をもたせたものである。ＩＣ
チップＡ（Ｉｌｌのパッド（１５）は、ＩＣチップＢ
（１３１の接続バ・ソド（１２）と接合させるため同間
隔で同数配置されている。また、接続パッド（１２）に
はあらかじめバンブ（１４）を設けている。Fig. 1 is a cross-sectional view of an IC chip mounted on a printed circuit board, Fig. 2 is a top view of the joined IC chip A-B shown in Fig. 1, and Fig. 3 is a cross-sectional view of the IC chip B shown in Fig. 2. It is a back view. In the figure (1), (3), (41° (5)
Since this is the same as that in the conventional example shown in FIG. 5, the explanation will be omitted. (11) is the connection pad of IC chip A, (13) is IC chip B, (12) is the connection pad of IC chip B +13), and +14) is the connection pad of IC chip A (II) and IC chip B (13). Banbu to make (1
5) is a pad of the IC chip A Ntl. As shown in Figures 1 and 2, the mounting area on the printed circuit board (1) can be reduced by the structure in which IC chip A (ill, rc chip B (13+) is vertically bonded. A (11) is a conventional IC chip (2) with a Pa Sodo (15).
Chip A (Ill pad (15) is IC chip B
(The same number of connection pads (131) are arranged at the same intervals in order to connect them to the connection pads (12). Furthermore, bumps (14) are provided in advance on the connection pads (12).
次に実装方法について説明する。第１図において、プリ
ント基板（１）上の配線（５）を伝搬してきた信号は、
リード（４）を経てパッド（３）から入力され、ＩＣ
チヴブＡ （１１１内部の回路を伝搬し、パッド（１５
）と接続パッド（１２）を介してＩＣチップＢ （１３
）へと伝搬する。ＩＣチップＢ （１３）内部の回路を
信号が伝搬したのち、接続パッド（１２）、パッド（１
５）を通りＩＣチップＡ（１１）の内部回路に再び信号
が伝搬する。この信号はＩＣチップＡ （１１１の内部
回路を伝搬し、 ＩＣチップＡ （１１）のパッド（３
）から出力され、リード（４）を経てプリント基板（１
）上の配線（５）に伝わる。Next, the implementation method will be explained. In Figure 1, the signal propagating through the wiring (5) on the printed circuit board (1) is
Input from pad (3) via lead (4), IC
Chivub A (111 internal circuit is propagated and the pad (15
) and the IC chip B (13) via the connection pad (12).
). After the signal propagates through the internal circuit of IC chip B (13), connection pad (12) and pad (1
5), the signal propagates again to the internal circuit of IC chip A (11). This signal propagates through the internal circuit of IC chip A (111) and reaches the pad (3) of IC chip A (11).
) is output from the printed circuit board (1) via the lead (4).
) is transmitted to the upper wiring (5).
なお、上・記実施例はＩＣチップＡ （１１１、ＩＣチ
ップＢ （１３）を積み重ねる場合について説明したが
、第４図のように複数個のＩＣチップを、単に重ねるだ
けではなく１つのチップを今して他のチップ同士を接続
することも可能である。第４図はこの発明の他の実施例
による複数のＩＣチップの結合を示す上面図である。図
において（１７）はＩＣチップＣ１（五８）はＩＣチッ
プＤ、（１９）はＩＣチップＥである。ＩＣチップＣ（
１７＋とＩＣチップＥ、 （１９）との信号Φ伝搬をＩ
ＣチップＤ （１８）がその内部の回路を介しておこな
っている。 −［発明の効果］ ・
以上のようにこの発明によれば、複数個のＩＣチップを
実装する場合、信号の供受関係が強い工Ｃチップ同士を
搭載して接合することにより、 ＩＣチップ、およびＩ
Ｃチップ間配線の占める実装面積が従来の実装方法より
縮小できるという効果がある。さらにＩＣチップ間の配
線数を削減できることにより配線によるノイズが軽減さ
れ、電子機器の小型化、高性能化がはかれる効果がある
。Note that the above embodiments have been described with respect to the case where IC chips A (111) and IC chips B (13) are stacked, but as shown in FIG. It is also possible to connect other chips now. Fig. 4 is a top view showing the connection of a plurality of IC chips according to another embodiment of the present invention. In the figure, (17) is the IC chip C1. (58) is IC chip D, (19) is IC chip E. IC chip C (
17+ and IC chip E, (19) signal Φ propagation is I
The C chip D (18) performs this through its internal circuit. - [Effects of the Invention] As described above, according to the present invention, when mounting a plurality of IC chips, by mounting and bonding C chips that have a strong signal reception relationship, the IC chips, and I
This has the effect that the mounting area occupied by the C-chip wiring can be reduced compared to the conventional mounting method. Furthermore, since the number of wires between IC chips can be reduced, noise caused by the wires can be reduced, resulting in smaller size and higher performance of electronic devices.
【図面の簡単な説明】
第１図はこの発明に係る半導体集積回路実装方法の一実
施例によるプリント基板上に実装したＩＣチップを示す
断面図、第２図は第１図に示す接合されたＩＣチップＡ
−Ｂの上面図、第３−図は第２図に示すＩＣチップＢの
裏面図、第４図はこの発明の他の実施例によるＩＣチッ
プの結合を示す上面図、第５図は従来のテープキャリヤ
方式により、ブリ、ント基板上に実装したＩＣチップを
示す断面図である。
図にお−ｂ）て、 ｊｌ）はプリント基板、 （３）は
パッド、（４）は、す、−ド、 （５）は配線、 （Ｌ
ｊ）はＩＣチップＡ、（１２）は接続パッド、（！３）
、はＩＣチップＢ、（１４）はバンブ、 （１５）はパ
ッド、 ＋１７）はＩＣチップＣ，（１８１はＩＣチッ
プＤ、 ＋１９＋はＩＣチップＥである。
なお、各図中、同一符号は同一、または相当部分を示す
。
代理人 大 岩 増 雄
第１ＩＩ
第２図
第８Ｉｌ
第４ＷＩＡ
１９：工Ｃテ・ツデＥ[Brief Description of the Drawings] FIG. 1 is a cross-sectional view showing an IC chip mounted on a printed circuit board according to an embodiment of the semiconductor integrated circuit mounting method according to the present invention, and FIG. IC chip A
-A is a top view of the IC chip B shown in FIG. FIG. 2 is a cross-sectional view showing an IC chip mounted on a print board using a tape carrier method. In the figure -b), jl) is a printed circuit board, (3) is a pad, (4) is a board, (5) is a wiring, (L
j) is IC chip A, (12) is connection pad, (!3)
, (14) is an IC chip B, (14) is a bump, (15) is a pad, +17) is an IC chip C, (181 is an IC chip D, and +19+ is an IC chip E. In each figure, the same reference numerals are the same. , or a corresponding portion. Agent Masuo Oiwa No. 1II Figure 2 No. 8Il No. 4 WIA 19: Engineering C Te Tsude E
Claims (1)
回路チップを、集積回路用パッケージあるいはプリント
基板上等で互いに信号接続端子部同士を接続することを
特徴とする半導体集積回路実装方法。A method for mounting a semiconductor integrated circuit, which comprises connecting a plurality of semiconductor integrated circuit chips each having a signal connection terminal section to the outside to each other on an integrated circuit package, a printed circuit board, or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310356A JPH04180257A (en) | 1990-11-14 | 1990-11-14 | Method of mounting integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310356A JPH04180257A (en) | 1990-11-14 | 1990-11-14 | Method of mounting integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04180257A true JPH04180257A (en) | 1992-06-26 |
Family
ID=18004249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2310356A Pending JPH04180257A (en) | 1990-11-14 | 1990-11-14 | Method of mounting integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04180257A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
-
1990
- 1990-11-14 JP JP2310356A patent/JPH04180257A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
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