JPH04176229A - Atm switch, multiplexer and its control method - Google Patents

Abstract

PURPOSE:To realize a low abort rate by forming the switch with a single kind of switch modules only and sending a read inhibit signal to a switch module of one preceding stage when a cell abort due to buffer overflow is going to take place in any of the switch modules. CONSTITUTION:Switch modules are arranged to each stage so that number of the switch modules of each stage of a line concentration switch is selected twice the number of switch modules belong to one succeeding stage with respect to the stage to which the switch module belongs and an output of the switch module of each stage is connected to the input of the switch module of a stage succeeding to the stage to which the switch module belongs. When cell abort is going to take place in a buffer memory of any switch module, a read inhibit signal is sent to the switch module of the pre-stage to stop the output of the cell to the switch module of the post stage. When there is no possibility of occurrence of cell abort, the transmission of the read inhibit signal is stopped and the cell transmission is restarted.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an ATM transmission device, an ATM switch, and an ATM multiplexing device. [Prior Art] In the conventional technology, as shown in FIG. 11, buffers are provided for each winter mountain highway in the number of input highways. ATM cells (hereinafter referred to as cells) coming from each input highway shall be
13, and a Verticel Path Indicator (hereinafter referred to as VPI) is displayed in the header section. At the input port, an input highway number is assigned to the cell. At the entrance of each switch, an address filter (hereinafter referred to as AF) determines whether to output to the output highway to which the AF belongs, based on the VPI and input highway number assigned to the cell. Cells that have passed through AF enter a buffer and wait for their turn to be output. Then, the selector selects one of the outputs of the buffer and outputs it to the outgoing line. Alternatively, an output highway number to which the cell should be output is assigned at the input port. At the entrance of each switch, an address filter (hereinafter referred to as AF) determines whether or not to output to the output highway to which the AF belongs, based on the output high unique number assigned to the cell. Cells that have passed through AF enter a buffer and wait for their turn to be output. Then, the selector selects one of the outputs of the buffer and outputs it to the outgoing line. Switching is performed by such an operation.

[Problem to be solved by the invention]

In the conventional switching system in which buffers are provided individually for each outgoing line, a large-capacity buffer is required in order to reduce the cell discard rate. Therefore, it is difficult to incorporate the plurality of buffer memories shown in FIG. 11 and the buffer memory control circuit that controls them into one LSI. Therefore, in reality, it is necessary to provide a plurality of buffer LSIs and independently provide a control LSI that controls the plurality of buffer LSIs.
Therefore, the number of types of LSIs to be developed increases. Further, in order to configure a switch with a low discard rate, a buffer with as large a capacity as possible is required, but since the buffer size is also limited by the capacity of the LSI, it has been difficult to configure a switch with a low discard rate. The purpose of the present invention is to achieve a low discard rate by using fewer types of switch modules and by simple control.
An object of the present invention is to provide an M switch and a control method thereof.

[Means for solving the problem] K input highways (K is an integer of 1 or more) and L input highways (L
In an individually buffered ATM switch, an acquisition switch having one input and one output is provided for each output highway in order to switch asynchronously multiplexed cells between output highways (where is an integer greater than or equal to 1). The line concentration switch is configured by connecting eight switch modules (S is an integer of 1 or more) having buffer means for multiplexing M inputs (M is an integer of 1 or more) into one output, and each The number of switch modules in each stage is equal to or less than M times the number of switch modules belonging to one stage after the stage to which the switch module belongs, and the number of switch modules belonging to the last stage is one. The outputs of the M switch modules in each stage are connected to the inputs of the switch module one stage after the stage to which the switch module belongs. If cells are about to be discarded due to buffer overflow in any of the switch modules, then
A read inhibit signal is sent to the switch module at the previous stage, and when the switch module one stage before the switch module receives the read inhibit signal, it stops sending cells to the switch module. Alternatively, if cells are discarded due to buffer overflow in any of the switch modules, a retransmission request signal is sent to the switch module immediately preceding the switch module, and When the switch module receives the retransmission request signal, the switch module retransmits the discarded cells. [Operation] =11- This will be explained using FIG. As shown in Figure 6, K
It accommodates input highways (K is an integer greater than or equal to 1) and L output highways (L is an integer greater than or equal to 1), and has K inputs and one output provided for each output highway. In the line concentration switch, each line concentration switch has a structure shown in FIG. In FIG. 7, M inputs (M is an integer of 1 or more) and switch modules that multiplex the M inputs into one are connected in 8 stages (S is an integer of 1 or more),
One switch module is placed in the S-th stage. Then, M switch modules are arranged in the (S-1)th stage. The (S-2)th stage has a switch module M2.
Arrange them. In this way, the switch modules are arranged in each stage so that the number of switch modules in each stage is less than or equal to M times the number of switch modules belonging to the next stage after the stage to which the switch module belongs, and the number of switch modules in each stage is The output is connected to the input of a switch module at a stage subsequent to the stage to which the switch module belongs. Then, the input of the switch module belonging to the first stage = 12
- Make sure that the total number of blades is K or more. By arranging and connecting the switch modules in this manner, cells can be automatically guided to the output highway, and only one type of switch module is required. moreover,
If cells are about to be discarded in the buffer of any switch module, a read prohibition signal is sent to the previous switch module to stop sending out cells. The detailed operation in this case will be explained using FIG. As shown in FIG.
When buffer overflow is about to occur in the buffer memory 52, a read prohibition signal is sent to the buffer memory control circuit 53 of the switch module 56 at the jth previous stage. When the buffer memory control circuit 53 in the switch module 56 receives the read prohibition signal,
The sending of cells from the switch module 56 to the switch module 57 is stopped. This is equivalent to connecting the buffer memories of the arranged switch modules in cascade, and can be treated as one large-capacity buffer memory, making it possible to reduce the cell discard rate. Alternatively, as shown in FIG.
When a buffer overflow occurs in the buffer memory 52 of No. 7, a retransmission request signal is sent to the buffer memory control circuit 53 of the switch module 56 of the previous stage. Buffer memory control circuit 5 in switch module 56
3 instructs the switch module 57 to retransmit the discarded cells when receiving the retransmission request signal. As a result, the switch module 56 retransmits the cells discarded by the switch module 57. Therefore, this is equivalent to connecting the buffer memories of the arranged switch modules in cascade, and can be treated as one large-capacity buffer, making it possible to reduce the cell discard rate. Here, the switch module includes a cell arrival detection circuit that detects the arrival of cells on M inputs as shown in FIG. 9, and a multiplexing circuit that multiplexes the arrived cells into one line by cell interleaving. A buffer memory for storing cells output from the multiplexing circuit, and a cell arrival signal from the cell arrival circuit to control writing when arriving cells are written into the buffer memory and control reading of cells from the buffer memory. It consists of a buffer memory control circuit and a buffer memory control circuit. Alternatively, the switch module may include a buffer memory having M inputs and one output as shown in FIG. The buffer memory control circuit may also include a buffer memory control circuit that controls writing and reading of cells from the buffer memory. It is also possible to use the concentrator switch shown in FIG. 7 as a multiplexer. Further, the cell storage capacity of the buffer memory in each switch module may be different.

【Example】

The first embodiment of the present invention will be explained using FIG. As shown in Figure 2, in an individual buffer type ATM switch that switches cells between eight input highways and eight output highways, the two inputs shown in Figure 4 are combined into one. A multiplexing circuit 21 for multiplexing, a cell arrival detection circuit 20-1, 20-2 for detecting the arrival of cells on the input highway, and N cells (N is an integer of 1 or more).
A switch module consisting of a buffer memory 22 having a capacity of 8 shown in FIG. 2 corresponding to each output highway.
Concentrating switches 5-1 to 5-8 with one output of human power are configured. Cells transferred on the input highway are assigned a VPI and an input highway number, and the AF uses this VPI.
The PI and input highway number determine whether the cell should be output to the output highway. Cells that are determined to be allowed to be output to the output highway are output to the output highway via the concentrator switch shown in FIG. Alternatively, if a cell transferred on an input highway is given an output highway number and entered, the AP determines whether or not to output the cell to the output highway based on the output highway number. Cells that are determined to be allowed to be output to the output highway are output to the output highway via the concentrator switch shown in FIG. Here, as shown in FIG. 1, the number of switch modules in each stage of the concentrator switch is twice the number of switch modules belonging to one stage after the stage to which the switch module belongs. The output of the switch module at each stage is connected to the input of the switch module at the stage subsequent to the stage to which the switch module belongs. That is, as shown in FIG. 1, four switch modules are arranged in the first stage, two in the second stage, and one in the third stage, and the switch modules in each stage are connected in series. Thus, by arranging the switch module, cells can be automatically directed to the output highway. Also,
Only one type of switch module is required. Next, if cells are about to be discarded in the buffer memory of any switch module,
As shown in FIG. 1, a read inhibit signal is sent to the preceding switch module, and the switch module that detects the read signal stops outputting cells to the subsequent switch module. When there is no longer a possibility that cells will be discarded, the switch module stops sending out the read inhibit signal, and cell sending is then resumed. The details of this process will be explained using FIG. 3. As shown in FIG. 3, when a buffer overflow is about to occur in the buffer memory 12-3 of the switch module 17-3, the buffer memory control circuit 13-3 detects this and the buffer memory 12-3 of the switch module 17-3 A read inhibit signal 16 is sent to the buffer memory control circuits 13-1 and 13-2 of the switch modules 17-1 and 17-2 in the previous stage. Buffer memory control circuit 13-
1 and 13-2 do not issue a cell sending instruction to the buffer memory 12-1 and 12-2 when they receive the read prohibition signal 16. As a result, switch modules 17-1 and ]7-2
Stop sending cells to 7-3. Therefore, switch module] 7-1. This is equivalent to connecting the buffer memories 1'7-2 and 17-3 in cascade, and can be treated as one large-capacity buffer, making it possible to reduce the cell discard rate. Further, a process to be performed when a cell is discarded in the buffer memory of one of the switch modules will be described with reference to FIG. As shown in FIG.
3 detects this and sends a retransmission request signal 16 to the buffer memory control circuit of the switch module 1.7-1.17-2, one stage before the switch module 17-3. When the buffer memory control circuit 13-1.13-2 receives the retransmission request signal 16, it issues an instruction to retransmit the cells discarded by the switch module 17-3. As a result, switch modules 17-]-217-2 and 1
This is equivalent to connecting 7-3 buffers in cascade,
Since it can be treated as one large-capacity buffer, it is possible to reduce the cell discard rate. Here, the switch module includes a cell arrival detection circuit that detects the arrival of cells on two inputs as shown in FIG. 4, and a multiplexing circuit that multiplexes the arrived cells into one line by cell interleaving. A buffer memory for storing cells output from the multiplexing circuit, and a cell arrival signal from the cell arrival circuit to control writing when arriving cells are written into the buffer memory and control reading of cells from the buffer memory. It consists of a buffer memory control circuit and a buffer memory control circuit. Alternatively, the switch module may include a buffer memory having 32 inputs and one output as shown in FIG. 5, and a cell arrival signal from the cell arrival circuit to write the arrived cell to the buffer memory. The buffer memory control circuit may also include a buffer memory control circuit that controls writing and reading of cells from the buffer memory. Here, the address filter can be removed by providing the cell arrival detection circuit with the function of the address filter. It is also possible to use the concentrator switch shown in FIG. 1 as a multiplexer. [Effects of the Invention] A switch can be configured with only a single type of switch module, and a low waste rate can be achieved with simple control.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a concentrator switch according to the first embodiment of the present invention, FIG. 2 is a diagram of an ATM switch according to the first embodiment of the present invention, FIG. 3 is an enlarged view of FIG. 1, and FIG. 5 is a diagram of an example of a switch module, FIG. 5 is a diagram of another side of the switch module, FIG. 6 is a diagram of an A, TM switch used for the operation of the present invention, FIG. 7 is a diagram of a line concentrator switch, and FIG. 8 is a diagram of a switch module. 9 is an enlarged view of a concentrator switch, FIG. 9 is a diagram of another example of a switch module, FIG. 10 is a diagram of another example of a switch module, and FIG. 11 is a diagram of a conventional example. Description of symbols 1-1 to 1-8・Input highway, 2-1 to 2-8 Address filter, 3-1 to 3-7 Switch module, 4-1 to 4-8・Output highway, 5-1 to 5-8
Concentrator switch. and 16

Claims (1)

[Claims] 1. In order to switch asynchronously multiplexed cells between K input highways (K is an integer of 1 or more) and L output highways (L is an integer of 1 or more), each In an individual buffer type ATM switch in which a line concentration switch having K inputs and one output is provided for each output highway, the line concentration switch multiplexes M inputs (M is an integer of 1 or more) into one output. The switch module is configured by connecting S stages (S is an integer of 1 or more) of switch modules each having a buffer means for converting the data into S stages, and the number of switch modules in each stage is equal to the number of switch modules belonging to one stage after the stage to which the switch module belongs. Switch modules are arranged in each stage so that the number of switch modules is M times or less, and the number of switch modules belonging to the last stage is one, and the output of the switch module of each stage and one of the stages to which the switch module belongs An ATM switch characterized by connecting the input of a subsequent switch module. 2. The switch module according to claim 1 includes: a multiplexing circuit that multiplexes cells input from the M inputs by cell interleaving; a buffer memory that stores cells output from the multiplexing circuit; An ATM switch comprising a buffer memory control circuit that instructs the buffer memory to write and read cells. 3. The switch module according to claim 1 includes a buffer memory with M inputs and 1 output that stores cells input from the M inputs, and instructs the buffer memory to write and read cells. An ATM switch comprising a buffer memory control circuit. 4. An ATM switch according to any one of claims 1 to 3, characterized in that M=2. 5. In claim 4, if K=L=2^S, the first stage has 2^S^-^1 switch module, and the second stage has 2^S^ -^2 switch modules... An ATM switch characterized by arranging 1 (S^0) switch modules in the S-th stage. 6. AT according to any one of claims 1 to 5
In the method for controlling the M switch, if the number of cells in the buffer memory exceeds a predetermined threshold in any of the switch modules, reading is prohibited for the switch module immediately preceding the switch module. A control method for an ATM switch that transmits a signal and stops transmitting cells to the switch module when a switch module immediately preceding the switch module receives the read prohibition signal. 7. AT according to any one of claims 1 to 5
In the method for controlling the M switch, when cells are discarded due to buffer overflow in any of the switch modules, a retransmission request signal is sent to the switch module immediately preceding the switch module, and the switch When the switch module one stage before the module receives the retransmission request signal, the AT retransmits the discarded cells in the switch module.
How to control M switch. 8. Claims 1 to 5, characterized in that the cell storage capacity of the buffer memory in the subsequent switch module is less than or equal to the cell storage capacity of the buffer memory in the previous switch module. AT to be
M switch. 9. Claims 1 to 5, characterized in that the cell storage capacity of the buffer memory in the subsequent switch module is greater than or equal to the cell storage capacity of the buffer memory in the previous switch module. AT to be
M switch. 10. K input highways (K is an integer greater than or equal to 1) and 1
In an ATM multiplexing device accommodating one output highway, a switch module having M inputs (M is an integer of 1 or more) and a buffer means for multiplexing the M inputs into one is arranged in S stages (S is an integer greater than or equal to 1), the number of switch modules in each stage is less than or equal to M times the number of switch modules belonging to one stage after the stage to which the switch module belongs, and the number of switch modules belonging to the last stage is 1. An ATM multiplexing device in which switch modules are arranged in each stage so that the switch modules are connected to each other, and the output of the M switch modules in each stage is connected to the input of the switch module one stage after the stage to which the switch module belongs. 11. The switch module according to claim 10 includes a multiplexing circuit that multiplexes cells input from the M inputs by cell interleaving, and a buffer memory that stores cells on the output of the multiplexing circuit. , and a buffer memory control circuit for instructing the buffer memory to write and read cells. 12. The switch module according to claim 10 includes a buffer memory with M inputs and 1 output that stores cells input from the M inputs, and instructs the buffer memory to write and read cells. An ATM characterized by comprising a buffer memory control circuit.
Multiplexer. 13. An ATM multiplexing device according to any one of claims 10 to 12, characterized in that M=2. 14. In claim 13, K=L=2^
S, the first stage has 2^S^-^1 switch module, the second stage has 2^S^-^2 switch modules, ..., the S stage has is an ATM characterized by arranging 1 (S^0) switch modules.
Multiplexer. 15. In the method for controlling an ATM multiplexing device according to any one of claims 10 to 14, in any one of the switch modules, the number of cells in the buffer memory exceeds a predetermined threshold. If the switch module immediately preceding the switch module receives the read prohibition signal, a read prohibition signal is sent to the switch module immediately preceding the switch module. A method of controlling an ATM multiplexer to stop transmitting cells. 16. In the method for controlling an ATM multiplexing device according to any one of claims 10 to 14, when discarding cells due to buffer overflow occurs in any of the switch modules, the switch module A retransmission request signal is sent to the switch module immediately preceding the switch module, and if the switch module immediately preceding the switch module receives the retransmission request signal, the switch module transmits the discarded cell again. A method of controlling an ATM multiplexing device. 17. Claims 10 to 14, characterized in that the cell storage capacity of the buffer memory in the subsequent switch module is less than or equal to the cell storage capacity of the buffer memory in the previous switch module. ATM multiplexing equipment. 18. Claims 10 to 14, characterized in that the cell storage capacity of the buffer memory in the subsequent switch module is greater than or equal to the cell storage capacity of the buffer memory in the previous switch module. ATM multiplexing equipment.