JPH0494240A - Cell exchange - Google Patents

Abstract

PURPOSE:To allow the cell exchange to cope with a change in a call capacity without being noticed of an external part even when the change in a call capacity takes place by storing once an outgoing line of destination information to a buffer memory based on destination information of an inputted cell and allowing an arbitration circuit to arbitrate the cell transmission sequence between buffer memories of a unit switch belonging to the outgoing line. CONSTITUTION:A destination information recognition circuit 9 of a unit switch 6 connecting to each incoming line group 4 reads destination information of a header part of a cell incoming to an incoming line and is stored in a buffer memory 7 of the unit switch 6 accommodating a relevant outgoing line corresponding to the destination information. An arbitration circuit 818 of a unit switch 618 checks a buffer memory 1718, sends a cell to be sent to an outgoing line 264 unconditionally when the cell to be sent is in existence in the memory and sends a signal representing the absence of a cell to be sent to an arbitration circuit 828 of a unit switch 728 when the cell to be sent is not in existence in the memory to transfer the right of cell transmission to the succeeding unit switch 628. Thus, even when a call is set, the exchange copes with a change in a call capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cell switching device that switches cells containing blocks of various multimedia information such as voice, data, and images at high speed.

[Prior Art] To realize a cell switching device, there is a method of arranging unit switches to form a multi-stage configuration, but it is desirable that the switching device itself be non-blocking (referred to as non-blocking). Non-blocking here means that when there is free capacity on both the outgoing and incoming lines, there is at least one path with enough free capacity to connect them. .

Figure 9 is shown, for example, in Sakurai et al., "Study of non-blocking conditions for multi-stage connected ATM channels J" (Proceedings of the 1988 Institute of Electronics, Information and Communication Engineers Spring National Conference (B-2), March 1988). This is a configuration diagram of a three-stage connected ATM communication path. )
~(2,,) is the km outgoing line, (38,) ~(3,,)
is the first stage unit switch with m input and r output, (32,)~
(3□,) is the second stage unit switch of input to output, (
33,) to (3,,,) are the third stage unit switches with input m and output. These unit switches (3) temporarily hold the cell in a buffer memory, select an output terminal based on the destination information of the cell, and send the cell to the selected output terminal. The output of each unit switch in the first stage is 2
It is connected to each input of the r unit switches in the stage. Further, the output of each unit switch in the second stage is connected to the input of each unit switch in the third stage.

Next, the operation will be explained. For one incoming line, usually
A cell string containing cells with different outgoing lines comes in. This cell consists of a header section containing destination information and a data section containing images, data, etc., and is a unit of fixed-length transmission information. Before the cell destination information enters the incoming line of the unit switch, a vertical cell channel identifier converter (not shown) performs routing (which path should be taken between the first unit switch and the third unit switch) in advance. determined and written to the header section. There are r routes through which cells can be transferred, but some links are occupied by calls that have already been set up.

The explanation will now focus on the cell row above the incoming line (1z) of the unit switch (3, .). In this cell column, there are outgoing lines (2,
There are cells destined for Information is written to the header section of the cell.

The cell that reaches the incoming line (1,,) is connected to the unit switch (3z)
reads the destination information in the header part, and based on the destination information, it is temporarily stored in the buffer memory in the unit switch (3,,), and then the unit switch (3,,) is sent to the determined unit switch (3□ 1) to the output end. Similarly, the second stage unit switch (32,) also outputs to the third stage unit switch (33,) according to the information in the header part of the cell input from the first stage unit switch (3,,). Select the edges and print. The third stage unit switch (33□) selects the outgoing line (2,,) based on the cell destination information,
Send the cell from the buffer memory to the outgoing line (2°).

The links between unit switches (3z) and (32,) and between unit switches (3□1) and (33,) are also used for cell transfer from other incoming lines, so the incoming line (1++) and outgoing line There may be cases where cells cannot be transferred even if there is free capacity in (2,,). For example, from the incoming line (111) to the outgoing line (2,...
), there are r ways of routing to the incoming line (11υ color and outgoing line (2, may be occupied.

FIG. 10 is a channel graph showing this state,
If the input/output line speed is V, the ratio of the link speed to the input/output line speed is n, and the minute amount is δ, then the input line (1,,) and the output line (
2, □) has enough free capacity to pass a call with speed U,
Assume that all other links are used. At this time, in order to set up a call at speed U between the incoming line (111) and the outgoing line (2, -), unit switches (3,,) to (32,
) to (3,,) must have free capacity to allow calls at speed U to pass. Therefore, the speed U
A new call cannot be set up. In the figure, the unit switch (3
7,) has free capacity to pass a call at speed U, and the other links show a capacity ff1u-δ that is slightly insufficient to pass a call at speed U.

If there is no available capacity on any link for passing a call at speed U, it is necessary to temporarily disconnect the call and re-establish the call.

For this reason, various cell switching device systems that do not cause blocking are being studied.

[Problem to be solved by the invention] Since the conventional cell switching device is configured as described above, there is no blockage when a call is set up or released, but the capacity of one call increases midway through. Occasionally, the capacity may be exceeded on the interstage link, and to prevent this, when the call capacity changes, the call should be released once the call is notified of the changed call content from the outside, and a path with capacity should be used. There were problems such as the need to reconfigure the settings.

This invention was made to solve the above-mentioned problems.Even if a change in call capacity occurs, it can be handled without receiving notification of the change from outside, and it can also be used to release calls whose capacity has changed. The purpose of the present invention is to obtain a cell switching device that does not require setting and resetting.

[Means for Solving the Problem] The first invention corresponds to a plurality of incoming line groups each including a plurality of incoming lines into which a cell including a data part and a header part having destination information is input, and the incoming line group. multiple outgoing line groups that combine multiple outgoing lines together, and one specific incoming line group and one specific outgoing line group that collaborate to connect all incoming line groups and all outgoing line groups. A unit switch that temporarily holds the transfer cell in the buffer memory and selects a link according to the destination information in the header section, and a unit switch that temporarily holds the transfer cell in the buffer memory between the unit switches that belong to each of the outgoing line groups. This cell switching device includes an arbitration circuit that arbitrates the order in which cells are transmitted to outgoing lines.

The second invention includes a plurality of concentrating circuits that multiplex cells from an incoming line and output them to the input side of a unit switch, and separate the multiplexed cells on the output side of the unit switch into an outgoing line that becomes the destination of the cell. This is a cell switching device equipped with a separation circuit that sends data to the outgoing line.

[Operation] The cell switching device of the first invention temporarily stores the destination information in the buffer memory when accommodating the outgoing line based on the destination information of the cell inputted by the unit switch connected to the incoming line group, An arbitration circuit arbitrates the cell sending order between the buffer memories of the unit switches belonging to the outgoing line.

In the cell switching device of the second invention, the concentrating circuit multiplexes the incoming cells and outputs them to the high-speed incoming line, and the unit switch accommodates the outgoing line with the destination information based on the destination information of the cell on the high-speed incoming line. When doing so, the cells are temporarily held in a buffer memory, and an arbitration circuit arbitrates the cell sending order between the buffer memories of the unit switches belonging to that outgoing line, and sends them out to the high-distance outgoing line. The separation circuit separates the cells on the high outgoing lines for each outgoing line and sends them out.

[Embodiment of the Invention] A cell switching device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a cell switching device in a first embodiment of the present invention. In Figure 1, (1,,) to (
1,,4), etc. (1) is the incoming line, (2,,,) ~ (2,,4
) etc. (2) is the outgoing line, (6,,) ~ (61,), (62,
) ~ (628), ... (6,,) ~ (6,,) etc. (6
) is a unit switch, (41) to (48) etc. (4) is 64
The entry line group of books (1o,) to (164) is 8 lines each, (5,) to (58), etc. (5) is 64
This is a group of eight book lines (2o,) to (264). FIG. 2 is a diagram showing the state of connection between the unit switch (6), the incoming line (1), and the outgoing line (2) in FIG. 1, and each incoming line of the incoming line group (4,) is connected to the unit switch ( 6, J) input.

Further, the outputs of the unit switches (6, , ) are respectively connected to respective outgoing lines of the outgoing line group (5J). (7,
j) is the buffer memory, (8, J) is the buffer memory (
7, J) is an arbitration circuit that coordinates with other unit switches (6) when sending cells to the outgoing line, and (9, J) is a destination information that checks and takes in the destination information of the cell from the incoming line (1). It is a recognition circuit.

Next, the operation will be explained. Incoming line (1,,) to (1,4
), the destination information in the header is read by the destination information recognition circuit (9) of the unit switch (6) connected to each incoming line group, and the unit switch that accommodates the outgoing line corresponding to the destination information (7) takes the cell and temporarily holds it in the buffer. If the outgoing line corresponding to the destination information is not accommodated, the cell is discarded.

Here, based on FIG. 3, the operation of transmitting cells addressed to the outgoing line (264) held in the buffer memory (7) will be explained in detail (in the figure, the incoming line (1) and the destination information recognition circuit (
9) is omitted).

Cells destined for the outgoing line (264) are sent to unit switches (6+8), (
6□8), (63,), (6,8), (6,8), (6
68) and (6, 8) and held in the buffer memory (7) of each unit switch.

In unit switches other than those mentioned above, cells destined for the outgoing line (264) are discarded.

Figure 3 shows the output line (26) of the cells stored in the buffer.
This is a case where the sending order to 4) is fixed.

Now, assuming that the transmission time of one cell on the outgoing line (264) is one time slot, only one unit switch can transmit a cell in one time slot. The unit switch cell sending priority is (618), (6□8)
, (6,,), (64,), (658), (668),
(6□8), (6ss). Unit switch (6, 8
)'s arbitration circuit (8,,) checks the buffer memory (7, 8) and if there is a cell to be sent, it sends it out unconditionally to the outgoing line (264), and if there is no cell to be sent to the buffer memory (718), then it sends it out unconditionally to the outgoing line (264). For example, the arbitration circuit (8,,) sends a signal indicating that there is no cell to be sent to the arbitration circuit (9□) of the unit switch (7□8).
8) via the signal line (106,), and the right to send the cell is transferred to the next unit switch (6□8). The arbitration circuit (928) that received this signal is connected to the buffer memory (7□8).
If there is a cell to be sent out, it is sent to the outgoing line (2, 4), and if there is no cell, a signal indicating that there is no cell to be sent out is sent to the arbitration circuit (9, 8) of the unit switch (73,). via the signal line ('10., 4). Similarly, if there is a cell to be sent to the buffer memory (7, 8) of the unit switch (638), it is sent to the outgoing line (6□4), and if there is no cell, the cell is sent to the unit switch (7,...). Transfer rights.

In this way, the right to send cells is transferred sequentially. Although the signal indicating that there are no cells to be transmitted is sent via the signal line (10), a specific pattern may be sent to the outgoing line (264).

FIG. 4 is a diagram showing another embodiment of the first invention, and shows an example in which cell transmission priority is determined by a polling method. Here, the arbitration circuits (8114), (8□8), (83
, ), (84,), (8,8), (86,), (8,,
), (88, ) and determines the priority order and rank of cell transmission in the buffer memory (7) of each unit switch will be explained. Each arbitration circuit is connected in a loop through a signal line (1064) for circulating tokens.

The unit switch (6,,) of the master station is the signal line (10,,4)
circulate tokens and monitor lost and duplicated tokens. If a unit switch, for example, a unit switch (6, 8), holds cells to be transmitted in a certain time slot in a buffer memory, its arbitration circuit (8
−, 8) captures the token and buffer memory (7is
) is sent to the outgoing line (2, 4), and then the captured token is released. If the unit switch (66,) holds the cells to be sent in its buffer memory (668), if the token released by the unit switch (6V,) arrives without being captured on the way, the token will be captured. and sends the held cell to the outgoing line (2(,4)), then releases the captured token.

FIG. 5 is a diagram showing a cell switching device according to an embodiment of the second invention. In the figure, (121) to (1216) etc.
2) multiplexes the cells input to the incoming line groups (41) to (46) for each incoming line group to form high-speed incoming lines (13,) to (
13,, ), (LL+), (11,
2), (11□υ, (11,2) is the unit switch, (1
5,)~(156) is the high speed outgoing group (1□4+)~
This is a separation circuit that separates the multiplexed cells on (14, , , , ) for each outgoing line accommodated in each high-speed outgoing line group, and outputs the cells at a reduced speed.

In this embodiment, as shown in FIG.
shows a case where four incoming lines are concentrated to perform cell multiplexing, and the separation circuit (15) accommodates four outgoing lines.

Next, the operation will be explained.

For the sake of simplicity, a cell entering the incoming line group (1,) will be explained as an example. The incoming cells of the four incoming lines (io,), (1o2), (1o3), c 1.4) of the incoming line group (1,) are condensed by the concentrator circuit (12,) and run faster than the incoming lines. (In this example, the number is 4 times.) and sent to the high-speed input line (13). Cells on this high-speed incoming line are stored in their buffer memory by unit switches (1, 1, , ) and (11, 2), which accommodate cells destined for the outgoing line, similarly to the operation of the embodiment of the first invention. hold it for a while.

Next, cells addressed to outgoing lines (26,) to (26,) are held in unit switches (1112) and (112□), and their transmission will be explained based on FIG. In the figure, the high-speed input line and destination information identification circuit are omitted. Buffer memory (7) of unit switches (1112) and (1122)
Outgoing lines (2,,,)~( held in 1□) and (72,)
Cells addressed to 26,) are sent to the high outbound line (14,,,) by determining the cell sending order by the arbitration circuits (8,2) and (8□2) in the same way as in the embodiment of the first invention. Send. FIG. 7 uses a polling method, in which a unit switch that has captured a token sends out a cell held in a buffer memory.

The cells sent out on the Takato outgoing line (14+3.) are sent to the outgoing line (14+3.) in a separation circuit (15, 6) based on the destination information in the header.
26,), (26□), (263), and (264) are separated separately, and the speed is reduced to the output line speed and sent out.

By quadrupling the operation speed of the line concentration, the number of unit switches can be reduced to 4, which is 1/16 of that in the first invention, and the number of unit switches can be significantly reduced.

In the embodiments of the first and second inventions, the connection between the unit switch and the incoming line and outgoing line or the unit switch and the high-speed incoming line and the high-speed outgoing line has been explained as a bus type, but as shown in FIG. 16).

In the embodiments of the first and second inventions, an example of a unit switch with 64 input wires, 64.8 output wires, and 8 human outputs is shown, but the present invention is not limited to this value.

Furthermore, in the embodiment of the second invention, four incoming lines are concentrated for the high-speed incoming line, and four outgoing lines are separated from the high-speed outgoing line, but the present invention is not limited to this.

Furthermore, in the embodiments of the first and second inventions described above, one cell is output to one outgoing line.
If there is free capacity on the outgoing line, it may be possible to output to multiple outgoing lines, and a broadcast function can also be added.

Alternatively, the header section and the data section may be structurally separated and transmitted using circuits with different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Furthermore, in both the embodiments of the first and second inventions, the incoming link speed is the same, but if the reading speed from the buffer memory is made faster than the incoming link speed, traffic can be concentrated; It is also possible to make the incoming link speed faster than the outgoing link speed.

Further, in both the embodiments of the first and second inventions, one priority is provided for each outgoing line of the cell switching device, but a plurality of priorities are assigned to each outgoing line, and the cell header It is also possible to read cells with a high priority from the buffer memory first based on a code indicating priority added to the cell in addition to the destination outgoing line information.

Furthermore, if restrictions on operating speed are required, a serial/parallel conversion circuit or a parallel/serial conversion circuit may be provided at the front and rear stages of this cell switching device to process signals as parallel signals.

[Effects of the Invention] As explained above, according to the cell switching device of the first claim, a call can be set without fail if there is free capacity on the incoming and outgoing lines, and even after the call is set up, the call capacity is Able to respond to change. Furthermore, there is no need to keep track of changes in call capacity, which simplifies control.

Further, according to the cell switching device of the second claim, since a concentrating circuit for multiplexing incoming cells and a separating circuit for separating the multiplexed cells and reducing the speed to the outgoing line are provided, in addition to the above-mentioned effects, , the number of unit switches can be significantly reduced,
This has the advantage of being compatible with large-scale cell switching equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first invention, FIG. 2 is a diagram showing detailed connections of unit switches, and FIG. 3 is a diagram explaining the operation of determining priorities for cell transmission according to the first invention. FIG. 4 is a diagram showing another embodiment, FIG. 5 is a diagram showing the configuration of the second invention, FIG. 6 is a diagram showing a concentrator circuit and a separation circuit, and FIG. 7 is a diagram showing the cell transmission of the second invention. FIG. 8 is a diagram showing another embodiment, FIG. 9 is a diagram showing a conventional cell switching device, and FIG. 10 is a channel graph. (101) to (164)... Incoming line, (201) to (2
64)... Outgoing line, (41) to (416)... Incoming line group, (51) to (516)... Outgoing line group, (
6), (11)...Unit switch, (7)...Buffer memory, (8)...Arbitration circuit, (9)...Destination information identification circuit, (10)...Signal line, (12)...
Concentrator circuit, (13)...high-speed input group, (14)
...high-speed outgoing group, (15)...separation circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (2)

[Claims] (1) Multiple incoming line groups each containing a plurality of incoming lines into which a cell consisting of a data part and a header part containing destination information is input, and multiple outgoing lines each grouping together multiple outgoing lines corresponding to the incoming line group. It is provided between a specific incoming line group and a specific outgoing line group so as to connect all incoming line groups and all outgoing line groups in cooperation with the outgoing line group, and is stored in the buffer memory of the transfer cell. arbitration of the sending order of the cells temporarily held in the buffer memory to the outgoing line between a unit switch that temporarily holds the cells and selects a link according to the destination information in the header section, and a unit switch that belongs to each of the outgoing line groups; A cell switching device characterized by comprising an arbitration circuit that performs. (2) Multiplexed cells are supplied to the input side of the unit switch via multiple concentrator circuits that multiplex and output cells from the input line, and the multiplexed cells on the output side of the unit switch become the cell destination. 2. The cell switching device according to claim 1, wherein the cell switching device sends the cell to the outgoing line through a separation circuit that separates each outgoing line.