JPH04170648A - Data rapid transfer processor - Google Patents

Abstract

PURPOSE:To shorten a data transfer time by preparing a data register for storing data read out from a main storage device and writing the data in the main storage device without transferring them to a central processing unit (CPU). CONSTITUTION:Address buses are constituted so that data are sent from the CPU 1 to a read address latch (RAL) 7 through an ABO120 or a write address latch (WAL) 9, sent to a selector circuit (SEL) 11 through an AB10121 at the time of reading or through an AB11 at the time of writing and then sent from the SEL 11 to a main memory device (MEM) 3 though an AB2. The volume of data transfer is set up in a data transfer counting address latch (MAL) 4, the data of the MEM 3 are read out to a data latch 12 and then immediately written in the MEM 3 and the MAL 4 is counted down in each transfer end. The contents of the RAL 7 and the WAL 9 are counted up and data transfer is continued until the value of the MAL 4 becomes zero. Consequently, data transfer is rapidly executed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a high-speed data transfer processing device.

[Conventional technology]

Conventionally, this type of data transfer processing device reads data DO from address RAO in the main memory, writes it to a work register in the central processing unit, and then reads data DO from the work register in the central processing unit to the address in the main memory. Data Do was written to WAO.

Next, the read address RAO and write address WAO are counted up in the central processing unit and the same process as above is performed. For example, if the transfer data is 4 bytes, the data bus is 4B, so processing is performed 1024 times.

[Problem to be solved by the invention]

In the conventional data transfer device described above, data read from the main memory is stored in a work register in the central processing unit, and then written as write data from the work register to the main memory, so data transfer takes time. There was a drawback.

[Means to solve the problem]

The high-speed transfer processing device of the present invention includes means for requesting a main memory control device from a central processing unit a read request and a data transfer request when reading main memory, means for simultaneously setting a main memory read address in a read address register, and A means for setting the transfer amount in a data transfer count register, a means for reporting completion of reading before reading data from the main memory, a means for requesting a write to the main memory controller, and a means for simultaneously writing the main memory write address. means for setting in an address register; means for reporting completion of writing before writing data to the main memory;
A means for controlling AS, CAS, and WE; a data register for holding data read from the main memory; a means for writing data to the main memory without transferring it to the central processing unit; means for counting up a read address register and a write address register at the end of a transfer, means for counting down a data transfer count register, means for continuing data transfer until the value of the data transfer count register becomes O, and a data transfer count register. and means for terminating data transfer when the value of becomes O.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a central processing unit (abbreviated as CPU),
2 is a main memory control unit (abbreviated as MCU), 3 is a main memory unit (
4 is a data transfer count address latch (abbreviated as MAL), 5 is a MAL countdown circuit (abbreviated as DWO), 6 is a MAL 0 detection circuit (abbreviated as DET), ? is the read address latch (abbreviated as RAL)
, 8 is the RAL count up circuit (abbreviated as RUP),
9 is a write address latch (WAL for short), 10 is W
AL count up circuit (WUP for short), 11 is R
A selection circuit for AL and WAL (abbreviated as 5EL), and 12 a data latch (abbreviated as DL).

The control interface between CPU 1 and MCU 2 receives a signal indicating that data in the main memory space is being transferred.
R as a read request signal for MEM3
REQlol is a ride request signal for MEM3, so it is RREQl 0 L. It is TERM103, which is a signal indicating the end of reading or writing for MEM3.

The control interface of MCUI=MEM3 is RAS 110 as a row address strobe signal, CASll as a column address strobe signal, and WE 112 as a write enable signal.

The address bus is RAL7 from ABo12o than CPUI.
Or, when WAL9 bobble tallies +tAB10121, when writing, it is sent from AB11122 to 5EL11, and from 5EL11 to MEM3 via AB2123.

Through the data path, CPUI) DBO200,
*To DL12 DL12. J-11) Sent to MEM3 through DB1201.

Next, a detailed explanation will be given with reference to FIG. 2, which is a time chart of FIG. 1.

Read start address RAO to write start address WA
When data is transferred to O (data transfer amount 4 bytes)
EC is turned on.

At timing T1, RAO is set to RAL7, data transfer amount n is set to MAL4, and RAS is activated for a memory read request.

At timing T2, the MCU2 turns on the TERM signal to pseudo-indicate to the CPU that the memory read request has ended.
Report to. And start CAS.

WAO is A due to memory write request at timing T3.
It is output to BO and WREQ is turned on.

WAO is set to WAL9 at timing T4.

At the same time, the first read data Do of MEM3 is D.
Set to L12.

At timing T5, the MCU2 turns on the TERM signal to pseudo-indicate that the memory write request has ended.
Report to.

R for writing to MEM3 at timing T7.
Turn on the AS signal and at the same time turn on RAL7 and RUP8.
Then the read address RAO+ is counted up by
Set to 1.

At timing T8, the CAS signal is turned on, and at timing T9, the WE double signal is turned on to complete the writing of data Do to MEM3.

Using the TIO timing, MAL4 is counted down by DWO5 and the number of transfers is set to n-1.

T□. At this timing, WAL9 is counted up by WUPIO and the next write address WAO+1 is set.

In this way, the above operation is continued until DET6 detects "O" from the output of MAL4. The output of MAL4 becomes "0" at the timing of Tn+2.

As a result, TERM is turned on at timing Tn+3, and MOVEC is turned off at timing Tn+4, indicating that data transfer in the memory space has been completed.

〔Effect of the invention〕

As explained above, the present invention has a data transfer count register, a read address register, and a write address register, reads data from the main storage device to the data register, writes it to the main storage device immediately after that, and counts the data transfer every time one transfer is completed. By counting down the register, counting up the read address register and write address register, and continuing data transfer until the data transfer count register reaches O, there is an effect that the data transfer can be made faster.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
It is a time chart explaining the operation|movement of a figure. 1... Central processing unit, 2... Main memory control device, 3.
...Main memory device, 4...Address latch for data transfer count, 5...Countdown circuit, 6...0 detection circuit, 7...Read address latch, 8, 10...
・Count up circuit, 11...Selection circuit, 12...
・Data latch.

Claims (1)

[Claims] means for requesting a read request and a data transfer request from the central processing unit when reading the main memory, means for simultaneously setting the main memory read address in a read address register, and a data transfer count register for setting the amount of data transferred. means for setting the read end before reading data from the main memory, means for requesting a write to the main memory controller after the operation, and writing the main memory write address at the same time. means for setting an address in the main memory; means for reporting completion of writing before writing data to the main memory; means for the main memory controller to control a RAM strobe signal of the main memory; a data register for holding read data; means for writing the data into the main storage device at an address indicated by the write address register without transferring the data to the central processing unit; and terminating each data transfer. means for counting up the read address register and the write address register; means for counting down the data transfer count register; means for continuing data transfer until the value of the data transfer count register becomes 0; A high-speed data transfer processing device comprising: means for terminating data transfer when the value of the transfer count register becomes 0.