JPH04170645A - Interrupt request input circuit of interrupt arbiter - Google Patents

Abstract

PURPOSE:To simplify an adder circuit by providing this interruption request input circuit with a means for superposing a square wave pulse of an 'L' level (or 'H' level) to an interruption request input based upon an external interruption request. CONSTITUTION:An external interruption request 13 is inverted by a NOT circuit 4 to form an interruption request input 1i to an interruption arbitrator 1 and the input 1i is always held at 'H' level. In the case of outputting an interruption request, the request 13 is inverted and sent t the arbitrator 1 as an 'L' level pulse, the arbitrator 1 recognizes an interruption by the rise of the trailing edge of the pulse, the active ('H' level) state of the request 1i is continued thereafter, and then an interruption processing request 14 is stably outputted from the arbitrator 1 to a CPU 2. Then, an interruption response signal 15 is outputted from the CPU 2 and the arbitrator 1 resets the request 14. Consequently, the constitution of an interruption input circuit to the interruption arbitrator is simplified.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a circuit that inputs an interrupt request to an edge input type interrupt arbiter that provides an interrupt processing request to the CPU based on an external interrupt request, and particularly an interrupt that can simplify the configuration and operation. This invention relates to an interrupt request input circuit for an arbiter. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 3 shows an example of the configuration of this type of interrupt request input circuit. In the figure, 2 is a CPU, 1 is an edge input type interrupt arbiter, and 3 is a D-type flip-flop. Also, Figure 4 shows the 3rd
It is a time chart for explaining the operation of the main part of the figure. This type of edge input type interrupt arbiter 1 issues an interrupt processing request 14 to the CPU 2 by detecting a rising edge of an arbiter input interrupt request 11 as an interrupt request input. The arbiter input interrupt request 11 at this time is
It is necessary to keep the interrupt processing request 14 stable by holding it until the two-part interrupt acceptance response signal 15 is returned, and if the request 11 is dropped before responding, the correct interrupt will not be accepted. For this reason, as shown in FIGS. 3 and 4, the interrupt request 13 from the outside is temporarily input to the type flip-flop 3, and the sampling clock 34 is applied to this flip-flop 3 to launch the interrupt request 13. The arbiter input interrupt request 11 latched in this way is input to the interrupt arbiter 1, and the interrupt response signal 15 from the CPU 2 is returned to the interrupt arbiter 1 to process interrupt processing requests 1 and 4. In addition to resetting the response signal 15, the response signal 15 is also applied to the flip-flop 3 to clear the latched interrupt request 11, thereby forming a correct interrupt sequence.

[Problem to be solved by the invention]

As mentioned above, in the conventional interrupt input method, in order to create a correct interrupt acceptance sequence, the rising edge of the arbiter input interrupt request 1 quantity and the rising edge of the interrupt acceptance response signal 15 from the CPU 2 in FIG. It is stipulated that the latched interrupt request 11 is kept in the active state (■) until the return of (■), and in order to satisfy this condition, an additional circuit of the D-type flip-flop 3 shown in FIG. 3 was required. . Therefore, it is an object of the present invention to provide an interrupt request input circuit for an interrupt arbitrator that can simplify this additional circuit.

[Means to solve the problem]

In order to solve the above problem, the interrupt request input circuit of claim I) provides an interrupt request input circuit (arbitrator manual request 14, etc.).
After the rising (falling) edge of Interrupt acceptance response signal from the CPU (15
In an edge input type interrupt arbiter (such as 1) that resets the interrupt processing request by inputting a signal (e.g., In the interrupt request input circuit according to claim 2, the interrupt request input circuit includes means for superimposing an L level (H level) square wave pulse on the interrupt request input based on an external interrupt request 13, etc. In the interrupt request input circuit according to claim 1), ``the means includes a NOT circuit (4).
etc.).

[For use]

The H level (positive) square wave pulse of external interrupt request 13 is
By inverting through the OT circuit 4 and setting it as the interrupt request input 11 to the interrupt arbiter 1, the interrupt request input 11 to the II interrupt arbiter 1 is always kept at H level, and the external interrupt request 13
By superimposing an L level (negative) square wave pulse on the interrupt request power 11 to the arbiter 1, the interrupt to the interrupt arbiter 1 is input conditions.

Embodiment 1 FIG. 1 is a block diagram of an interrupt input circuit as an embodiment of the present invention, and corresponds to FIG. 3. Further, FIG. 2 is a time chart for explaining the operation of the main part of FIG. 1. In FIG. 1, the D-type flip-flop is omitted compared to FIG. 3, and a NOT circuit 4 is simply used instead.6 In the present invention, the edge input type interrupt arbiter 1 is used to meet the correct interrupt input conditions. ``Rising edge j'' of arbiter input interrupt request 11 and ``interrupt acceptance response signal 15 from CPU 2
Focusing on the two conditions of holding the arbiter input interrupt request 11 until it returns, the arbiter input interrupt request 11 obtained by inverting the external interrupt request 13 by the NOT circuit 4 is input to the interrupt arbiter 1. By doing so, as shown in Fig. 2, the arbiter input interrupt request 1
The amount is changed from "no request" to active (H level) (■). At this time, since there is no rising edge of the arbiter input interrupt request 11, the interrupt request is not recognized by the arbiter 1. Next, when making an interrupt request, by inverting the external interrupt request 13 and sending it to the arbiter 1 as a negative pulse ■, an interrupt will be sent to the arbiter 1 at the rising edge ■ of the trailing edge of this negative pulse ■. Recognized and active state of arbiter input interrupt request 11 ■
This will continue from now on, and the conditions necessary for the edge input type interrupt arbiter 1 to recognize an interrupt input can be satisfied. As a result, the interrupt processing request 14 is stably output from the interrupt arbitrator 1 to the CPU 2. An interrupt response signal 15 is output from the 1cPU 2, and the interrupt processing request 14 is reset by the interrupt arbitrator 1 manually inputting the interrupt response signal 15. Effects of the Invention According to the present invention, after detecting the rising edge of the arbiter input interrupt request 11, the arbiter input interrupt request 11 is maintained at the H level, thereby stably processing the interrupt processing request 14. In an edge input type interrupt arbiter 1 that outputs to a CPU 2 and resets the interrupt processing request 14 by inputting an interrupt acceptance response signal 15 from the CPU 2, the arbiter input interrupt request 11 is always set to H. level, and the arbiter input interrupt request 11 is set to L based on the external interrupt request 13 as a square wave pulse of H level (positive).
NOT circuit 4 that superimposes level (negative) square wave pulses
This not only simplifies the configuration of the interrupt input circuit for the interrupt arbiter, but also latches interrupt requests upon the occurrence of an interrupt event.
It becomes unnecessary to issue an interrupt response signal from the CPU to the latch circuit and to clear the launched interrupt request using the response signal.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the main parts of Fig. 1, and Fig. 3 is a conventional block circuit diagram corresponding to Fig. 1. , FIG. 4 is a time chart for explaining the operation of the main part of FIG. 3. ■ = Interrupt arbiter, 11 = Arbitrator input interrupt request, 2:C
PU, 4: NOT circuit, 13: external interrupt request, 14: interrupt processing request, 15: interrupt response signal. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1) After detecting the rising (falling) edge of the interrupt request input, the interrupt request input is maintained at the H level (L level) to send a stable interrupt processing request to the CPU. In an edge input type interrupt arbiter that resets the interrupt processing request by inputting an interrupt acceptance response signal from the CPU, the interrupt request input is always maintained at H level (L level). An interrupt request input circuit for an interrupt arbitrator, further comprising means for superimposing an L level (H level) square wave pulse on the interrupt request input based on the original interrupt request. 2) An interrupt request input circuit for an interrupt arbitrator according to claim 1, wherein the means comprises a NOT circuit.