JPS59140559A - Buffer register - Google Patents

Abstract

PURPOSE:To reduce delay of propagation, speed up operation and to simplify structure in a buffer register that performs change of clock by forming a clock for bridging from phase relation between an input clock and an output clock. CONSTITUTION:An intermediate register L2 that holds output at least for the time corresponding to set up of an output register L3 is provided between an input register L1 of one step that takes in input data synchronizing with an input clock CKW and the output register L3 of one step in which data are taken in synchronizing with an output clock CKR. Then, the intermediate register L2 outputs the input as it is when the phase relation between two clocks CKM, CKR satisfies conditions fixed by the input data before set up time of the output register L3. When conditions are not satisfied, the output of input register L1 is delayed by the clock CKM, and supplied to the output register L3.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a buffer register for exchanging data between digital devices.

"Background technology and its problems" Digital video equipment that handles digital video data (
The system clock used in a video switcher, digital VTR, etc.) is synchronized with the host signal source and has the same clock rate (for example, 4f, where f is the color subcarrier frequency). However, the clock phase between digital video equipment is 1. If they are not always regulated equally and receive video data and clocks from other digital video equipment, the receiver must be reclocked to use the clock of the receiving device. Also, depending on the device,
Some systems use the input clock as it is as the system clock, but it is not uncommon for the clock to have jitter due to the length of the transmission cable, and in that case, the clock must be replaced.

Buffer registers called FIFOs have been developed in the past that enable locks to be exchanged in this manner, but those implemented as ICs have the following drawbacks.

The first drawback is the propagation delay g (Throughout D
elay ) is so large that the maximum value extends to several μsec.

A second disadvantage is that it operates slowly and cannot be used to process high transmission rate data, such as digital video data. The third drawback is that they are expensive.

[Object of the Invention] The object of the present invention is to provide a buffer register that has a small propagation delay, can operate at high speed, and has a simple configuration.

"Essentials of the invention" This invention receives and receives an input clock and input data,
It outputs data synchronized with the clock (output clock) of the device. This invention provides a one-stage input register that receives input data in synchronization with an input clock, a one-stage output register that receives data in synchronization with an output clock, and a space between the input register and the output register. It is inserted and consists of at least the setup time of the output register and an intermediate register that holds the output data.

"Embodiment" An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, Ll indicates an input register that takes in input data in synchronization with the input clock CKW.

In the case of video data, the input data is 8-bit parallel. An intermediate register L2 is connected to this manual register L1. An output register is connected to this intermediate register L2. The output data of this output register L3 is supplied to a data processing device (digital VTR, video switcher, etc.). Data is taken into the output register L3 by the system clock, that is, the output clock CKRK of this data processing device.

Clock CKM is supplied to intermediate register L2. When this clock CKM is H (high novel), input data appears as output data as it is, and this is L (
(low level), the data up to that point is held. If the set-up time of the output register is tsu, then the output clock CKR supplied to the output register L3
It is necessary that the input data be determined at least tsu before the start-up time of . Two clocks CKM and C
There are cases in which the phase relationship of KR satisfies this condition and cases in which it does not. When this condition is satisfied, the clock 02 is always at H, and the intermediate register L2 operates to output the input as is. On the other hand, when this condition is not satisfied, the output of the C1 manual register L1 is delayed by the clock CKM and is supplied to the output register L3.

A D flip-flop F is used to detect the phase relationship between the input clock CKW and the output clock CKH.

F2. F3, date circuits Gl, G, G3, and inverters N1 to N8 are provided.

The D-fritzo F is always supplied with H as a digital power, the input clock CKW is input as a clock, and its output Q is delayed through the inverter N1゜N1+Na and supplied to the reset terminal. It is. When the input clock CIGV shown in FIG. 2A is supplied, the output F1Q (FIG. 2B) rises and inverts N□, N, at its rising edge.

After a delay time of N8, the output FIQ falls. The output Q of this flip-flop F1 is output as a pulse X (FIG. 2C) l1in, and is supplied to ANDf)G1.

4- Also, the inverter N2 is used as the clock input of the D7 lip flop F2 to which H is always given as the data input.
(FIG. 2D) is supplied.

The output F2Q of the D flip flop F2 with is NANDr
- is fed back to the reset terminal via gate G2 and inverter N4. Therefore, as shown in FIG. 2E, the output F2Q of the D flip-flop F2 falls a little later than the rising edge of the pulse shown in the second diagram.
9, NAND data) It rises after the delay time caused by G2 and inverter N4 and its own delay time. Rising 9 edges of pulse X and 7 lips F2 output F2
The time difference τ between the rising edge of Q and the rising edge of Q is the width of the hysteresis.

The output F2Q of this D flip flop F2, pulse X and dEANDr-)GK are supplied, and the AND date G.

From this, a pulse Y shown in FIG. 2F is generated. This pulse Y has a hysteresis width τ compared to the pulse X, and its L
period has been increased.

The output Y of this AND '7' -) G1 is used as a data input to a D flip-flop F for phase comparison. Also, 6- FIG. 2G shows the output clock CKR. In the time chart of Fig. 2, because the rising edge of the input clock CKW (Fig. 2 A) and the rising edge of the output clock CKR are close, the data taken into the input register L is output at that time. When given to registers I and a, the set-up time ts of this output register L8
This shows a case where u cannot be secured.

This output clock CKR is applied to the inverter N5. N6.
Clock CKR1 delayed by N7°N (Fig. 2M)
is used as the clock input of the D-Fritzo 70F3. t
s indicates the setup time of this D7 Rizzo F3. In the case shown in FIG. 2, since the pulse Y becomes L before this set-up time ts, the output pulse 2 of the D flip-flop F3 becomes H as shown in FIG. 2I. This pulse 2 is NAND 'f
) G2. GaK supply tL le. NANDf”-toG
3 is supplied with the output clock appearing at the output of the inverter N5, and the clock tone (M in Fig. 2) is supplied to the output of the inverter N5.
occurs.

The output of the input register Ll is synchronized with the input clock CKW and receives data D shown in FIG. 2K. , Dl, D2...
... appears. Also, when the clock CKM is H,
Intermediate register L2 outputs the input as is, and this is L
At this time, the intermediate register L2 holds the data up to that point. Therefore, output data delayed by the pulse width of the clock CKM is generated from the intermediate register L2, as shown in the second diagram. Then, since the output of this intermediate register L2 is resampled by the output clock CKR, the second
The data shown in Figure M appears.

In addition, the time chart in Fig. 3 is based on the input clock CKW.
(Figure 3A) rising edge 9 and output clock CKR (
This is a case in which the rising edge in FIG. 3G) is optically separated and the set up register Cmt of the output register Ls can be secured. From the input clock CKWu to the output FQ of the Frituno flop F (M in Figure 3) 1
1 forms the pulse X (FIG. 3C) as described above.

7- In addition, in the case of the time chart of Fig. 3, as shown in Fig. 3I, the output pulse 2 of the frituno flop F3 is always L, and the frituno flops are always in the reset state, and their output As shown in Figure 3M, F2Q is always H.
becomes. Therefore, the L period of the pulse Y generated at the output of the AND date Gl is not extended as shown in FIG. 3M, and therefore the output pulse 2 is always L.

Therefore, NAND I' −) Ga(Q output K
CKM is always H as shown in FIG. 3M.

As shown in FIG. 3K, the data sampled by the input clock CKW and appearing at the output of the input register L1 is directly used as the output data of the intermediate register L2.

The output of the intermediate register L2 shown in FIG. 1X3 is resampled by the output clock CKR, and the data shown in FIG. 3M is taken out from the output register.

[Effects of the Invention] According to the present invention, it is possible to shorten the propagation delay and simplify the configuration compared to the conventional IC-based FIFO buffer register. In other words, the conventional F
In the IFO register, the internal clock formed from the input clock CKW is propagated one after another to the preceding registers.
Since the configuration reaches the final stage register, in order to ensure phase independence between the input clock CKW and the shift clock of the final stage register (i.e. output clock CKR),
It required multiple stages of registers. Therefore, the propagation delay became large, it was difficult to increase the internal clock propagation speed, and the configuration was complicated.

In contrast, in this invention, the bridging clock CKM is formed by the phase relationship between the input clock 0 and the output clock CKR, so that only one stage of intermediate registers is required, and the above-mentioned problem can be solved. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIGS. 2 and 3 are time charts used to explain the operation of an embodiment of the present invention. L, -... Input register, Lm...
...Song...Intermediate register, L3...--
...Output register. Agent Tadashi Sugiura Figure 1 11- Figure 2 CKW FlQ MOUT DODI D2 Figure 3 LL2DI D2 D3 LIT ML3Do DI D2 D3UT

Claims (1)

[Claims] inserted between a one-stage input register that takes in input data in synchronization with an input clock, a one-stage output register that takes in data in synchronization with an output clock, and the input register and the output register, A buffer register comprising an intermediate register that holds the output data for at least a time corresponding to the set-up time of the output register.