JPH04170224A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce an A/D conversion time by deciding the value of register of an output digital signal having plural bits by one clock cycle. CONSTITUTION:The value of registers 3, 4 is outputted by using a clock pulse from a clock pulse generator 12. When D/A converters 5, 6 receive the value of resisters, a level appears respectively at a signal line 13, nodes 14, 15, 16 and a signal line 7 by bleeder resistances R1-R4. Thus, comparators 7, 8, 9 compare respectively a level of the nodes 14, 15, 16 with an input level VIN at an input terminal 1 and when the input level VIN is higher as a result, the comparators output a level '1' and when lower, they output a level '0'. An encoder 2 receives outputs of the comparators 7-9 and outputs a prescribed value to output signal lines 10, 11.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an A/D converter, and particularly to a voltage comparison type A/D converter.
Regarding converters.

[Conventional technology]

Conventionally, successive approximation type A/D converters are often used as voltage comparison type A/D converters.

Figure 2 shows an example of a conventional successive approximation type n-pi) A/D.
FIG. 2 is a block diagram of a converter.

As shown in FIG. 2, the conventional successive approximator A/D converter includes a comparator 7 that compares an analog/four-da signal (VIN) from an analog input terminal 1 with a predetermined voltage, and an output of this comparator 7. a digital output signal register 3 that sequentially stores the data and outputs a digital output when the register is full; and a D/A converter 5 that converts this digital output into an analog signal and converts the analog output into the predetermined voltage of the comparator 7. and a clock pulse generator 12 that supplies pulses to the digital output signal register 3, the register 3 is supplied with a reset signal 19 for resetting, and the D/A converter 5 is supplied with a reference voltage V.
REF is supplied. The n-bit digital output signal register 3 is set to all “0°” by the reset signal 19.
has been reset to .

First, the most significant bit of register 3 is set to 1'' by a clock pulse from clock pulse generator 12. The D/A converter 5 receiving the output of this register 3 connects the potential of 1/2 Vnv,p (V) to the signal line (VD
AC) l Output to 3. As a result, the comparator 7 compares the potential of the signal line 13 and the potential (VfN) of the analog signal input from the analog input terminal 1, and
It outputs ++1u when DAo, and outputs "0" when VDAC, <VDAC. The most significant bit of this register 3 is updated to this value.

With the next clock pulse, the second highest bit of register 3 is set to 1"1'°, and similarly updated to the output value of comparator 7.

By repeating these operations n times, the digital output value can be determined. That is, it takes n cycles of clock pulses to complete the A/D conversion.

[Problem to be solved by the invention]

The conventional A/D converter described above can only set the output digital signal register value for 1 bit during 1-0 clock pulse. The disadvantage is that it takes a long time.

An object of the present invention is to provide an A/D conversion time that can shorten the A/D conversion time.
/D converter.

[Means to solve the problem]

The A/D converter of the present invention includes a plurality of comparators that compare an input analog signal and a predetermined divided reference voltage, and receives outputs from the plurality of comparators and outputs a plurality of bits at a time. first and second registers that store outputs of the encoder; first and second D/A converters that convert bit signals read from the first and second registers; A converter, and a plurality of voltage dividing resistors connected in series between the first and second D/A converters, the node voltage of the voltage dividing resistors is set to the predetermined reference voltage, and the encoder is configured to be set in the first register for each of a plurality of bits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an A/D converter showing one embodiment of the present invention.

As shown in FIG. 1, this embodiment includes comparators 7 to 9 that compare the analog voltage from analog input terminal 1 and a predetermined voltage divided by resistors R1 to R4, and the outputs of these comparators 7 to 9. Encoder 2 that encodes , and 2 of encoder 2
A digital output signal register 3 and a register 4 that input and store bit outputs 10° and 11, and a D/A converter 5 that converts the outputs of these registers 3 and 4 into analog signals.
and 6, and a clock pulse generator 12 that supplies clock pulses to the registers 3 and 4. Further, in this embodiment, the voltage dividing resistors R1, R2, R3, and R4 connected between the D/A converters 5 and 6 have the same resistance value. Further, registers 3 and 4 are n-bit registers, and are set to all "1" and all "0" by the set signal and reset signal from the set signal input terminal 18 and reset signal input terminal 19, respectively.
has been reset to .

First, the register values of registers 3 and 4 are output by a clock pulse from the clock pulse generator 12.

When the D/A converters 5 and 6 receive this register value, the signal line 13, nodes 14, 15 .
'16 and signal line 17, respectively VREF, 3
/4VREF, 2/4VRBF.

1/dVR, a potential of 0 (V) appears. This results in
Comparators 7 and 8.9 respectively compare the potentials of nodes 14 and 15.16 with the input potential vIN of input terminal 1, and as a result, if the input potential VIN is high, it outputs 111++, and if it is low, it outputs 0%. Output.

Table 1 Table 1 shows the relationship between input values and output values of encoder 2. Encoder 2 receives the outputs of comparators 7 to 9 and outputs the values shown in Table 1 to output signal line 10.11. Therefore, n
The most significant and second most significant bits of bit registers 3 and 4 are updated to the bit values from signal lines 10 and 11, respectively.

Next, each register 3, 4 performs a similar operation in synchronization with the pulse from the clock pulse generator 12, and determines the third and fourth bits from the most significant, respectively. In this way, when this operation is repeated (1/2)n times,
All n bits of registers 3 and 4 are determined, and the output digital signal is determined.

In this embodiment, since the output signal register value for 2 bits is determined in one clock cycle, the output digital value is determined in half the time of the conventional A/D conversion time.

〔Effect of the invention〕

As explained above, since the A/D converter of the present invention can determine the output digital signal register value of multiple bits in one clock cycle, it is possible to reduce the conventional A/D conversion time to less than half. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an A/D converter showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional A/D converter. 1...Analog signal input terminal, 2...
Encoder circuit, 3... Digital output signal register, 4... Register, 5, 6...
D/A converter, 7-9... Voltage comparator, 10.
11... Encoder output signal line, 12...
...Clock pulse generator, 18...Set signal input terminal, 19...Reset signal input terminal, R1
-R4...Resistance element. Agent: Patent Attorney Osamu Uchihara

Claims (1)

[Claims] 1. A plurality of comparators that compare an input analog signal and a predetermined divided reference voltage, and an encoder that receives the outputs of the plurality of comparators and outputs a plurality of bits at a time. , first and second registers for storing the output of the encoder, and first and second D/A converters for D/A converting the bit signals read from the first and second registers.
A converter, and a plurality of voltage dividing resistors connected in series between the first and second D/A converters, the node voltage of the voltage dividing resistor is set to the predetermined reference voltage, and the voltage dividing resistor is set to the predetermined reference voltage. An A/D converter, wherein the encoder sets the first register for each of a plurality of bits. 2. The A/D converter according to claim 1, wherein the first and second registers output digital signals for each of a plurality of bits in synchronization with a clock pulse.