JPS62155621A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To attain the constitution suitable for monolithic circuit integration comprising a MOS transistor (TR) structure by making a resistor placed at both ends of a resistor array variable constituting a voltage divider supplying a reference voltage with simple constitution. CONSTITUTION:A high voltage divider 100 consists of plural resistors 11-19, and connecting points between resistors form outputs 20-27. Resistors 11, 19 are variable resistors and the resistance of the resistor 11 is varied into R/2 and R, and the resistance of the resistor 19 is varied into R/2 and 0. Further, the voltage divider 100 is connected between the 1st reference voltage VR and the 2nd reference voltage GND. Plural outputs 20-27 of the voltage divider 100 are connected respectively to comparison reference inputs of plural comparators 30-37. The comparator 37 among the said plural comparators is provided to detect the over range. In changing the resistance of the resistors 11, 19 placed at both ends of the resistor array to apply plural number of times of A/D conversion and the result of the plural number of times of A/D conversion is combined by a code conversion circuit 151 to obtain the result of A/D conversion with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an analog-to-digital (hereinafter referred to as an A/D converter) converter, and particularly to a parallel comparison type A/D converter using a voltage divider.

[Prior art]

The parallel comparison type A/D converters simultaneously apply an analog input voltage V to 2N-1 comparators using different output voltages of voltage dividers that divide the reference voltage input by 2N as comparison standards.
s is applied, each comparator determines whether it is larger or smaller than the reference value, and the result is encoded as a digital output.
rew G, F, Dingwal 1's paper “
Monolithic Expandable 6Bi
t 20MHzCMO8/SO8A/D Converter
ter″ IEEE Journalof 5o11d
-8tate C1rct+its, Vol, SC
-14, P&L6°Dec, 1979, etc. are known.

Figure 1 shows an example of the configuration of a parallel comparison type A/D converter with N=3.
This is the case. Here, N is the number of bits that the A/D converter has. In the figure, 10 is a voltage divider with multiple resistors 11
~19, and the connection points between these resistors form outputs 20-26, respectively. The resistance values of the resistor 11 and the resistor 19 are each Ⅰ/2, the resistance values of the other resistors 12 to 18 are all R, and the overall resistance value of the voltage divider 10 is 2NR.
1, that is, 8R. Further, the voltage divider 10 is connected between the reference voltage v8 and the ground potential GND. Furthermore, a plurality of outputs 20~ of the voltage divider 10
26 is connected to the comparison reference input terminals of the plurality of comparators 30 to 36, respectively. Reference numeral 50 denotes a position detection logic circuit, which is composed of a plurality of logic gates 40-46, and the output of the position detection logic circuit 50 is connected to a code conversion circuit 51 having digital outputs 510-512.

The operation will be explained below according to FIG.

First, analog input voltage (1) 8 is simultaneously applied to a plurality of comparators 30 to 36 having different comparison standards.

Then, the output of the comparator where the analog input voltage VS is higher than the comparison reference becomes a low level, that is, "0", and conversely, the output of the comparator whose analog input voltage VS is smaller than the comparison reference becomes a high level, that is, "1". . Therefore, the plurality of comparators 30 to 36 are divided into comparators whose output is "0#" and comparators whose output is "1" depending on the value of the analog input voltage V8. ” and the comparator that is “1” are detected, and the output of the gate corresponding to the boundary among the logic gates 40 to 46 is set to “1”. This position detection logic circuit 5
The output of 0 is encoded by a code conversion circuit 51 to obtain a digital output.

By the way, as mentioned earlier, this parallel comparison method
Letting the number of bits of a D converter be N, it has 2N-1 comparators, and as N increases to improve conversion accuracy, the number of comparators increases.For example, each time N increases by 1, approximately twice as many comparators as before are installed. Moreover, since a comparator with high resolution is required, such a comparator inevitably has a complex circuit. This has the drawback of increasing area and power consumption.

[Purpose of the invention]

An object of the present invention is to increase the number of bits of an A/D converter by making variable the resistances located at both ends of a resistor string constituting a voltage divider that supplies a reference voltage. A high-resolution parallel comparison type A/
The purpose of the present invention is to provide a D converter.

[Structure of the invention]

The A/D converter according to the present invention includes an input means for an analog input signal, a voltage voltage divider connected between a first reference voltage and a second reference voltage, and an output from the voltage voltage divider. A parallel comparison type A comprising a plurality of comparators used as reference values, a position detection logic circuit that receives the output of the comparator, and a code conversion circuit that receives the output of the position detection logic circuit and converts it into a digital value. The /D converter is characterized in that it has a comparator for over-range detection in addition to a comparator for digital encoding, and the voltage divider is constituted by a resistor string consisting of a plurality of resistors, and It is configured such that the resistance values of the resistors located at both ends of the resistor array can be varied, and A/D conversion is performed multiple times by changing the resistance values of the resistors located at both ends of the resistor array, respectively. The present invention is characterized in that a highly accurate A/D conversion result is obtained by combining the A/D conversion results of the above in the code conversion circuit.

The details of the present invention will be explained below with reference to the drawings.

[Explanation of Examples]

FIG. 2 shows an example of the configuration of a parallel comparison type A/D converter according to the present invention, where N=3 and A=1.

Here, N is the number of bits that the A/D converter has before implementing the present invention, and A is the number of bits increased by implementing the present invention. In the figure, reference numeral 100 denotes a high-voltage voltage divider, which is composed of a plurality of resistors 11 to 19, and the connection points between these resistors form outputs 20 to 27, respectively. Resistor 11 and resistor 19 are each variable resistors, and the resistance value of resistor 11 is 几/2.
The resistance of resistor 19 (IN can be varied between 1 mo/2 and 0, and the resistance of resistor 11
The sum of the respective resistance values of the resistor 19 and the resistor 19 is always varied so as to be average. The resistance values of all other resistors 12-18 are all 2N11. .

In other words, it is set to 8B. Further, the voltage divider 100 is connected between the first reference voltage 8 and the second reference voltage GND. Furthermore, the plurality of outputs 20-27 of the voltage divider 100 are connected to comparison reference input terminals of the plurality of comparators 30-37, respectively. By the way, the comparator 37 among the plurality of comparators is provided for overrange detection. A position detection logic circuit 150 is composed of a plurality of logic gates 40 to 47, and the output of the position detection logic circuit 150 is connected to a code conversion circuit 151 having digital outputs 510 to 513 and an overrange output 514. Further, 110 is a sampling circuit that samples an analog input signal, and a sampling clock f
8.

The operation will be explained below according to FIG.

First, the resistances at both ends of the resistor string constituting the positive voltage divider 100, that is, the resistance value of the resistor 11 is set to about /2, and the resistance value of the resistor 19 is set to about /2. Next, the analog input voltage (1) 8 is sampled by the sampling circuit 110 and held for a certain period of time, and the held analog voltage is simultaneously applied to a plurality of comparators 30 to 37 each having a different comparison standard. Then, the output of the comparator whose held analog voltage is greater than the comparison reference becomes a low level, that is, "O", and conversely, the output of the comparator whose held analog voltage is smaller than the comparison reference becomes a high level, that is, "
Therefore, the output of the plurality of comparators 30 to 37 becomes "09" depending on the value of the held analog voltage.
The position detection logic circuit 150 detects the boundary between the comparator whose output is "0" and the comparator whose output is "1". ,
The output of the gate corresponding to the boundary among the logic gates 40 to 47 is set to "1". The output of this position detection logic circuit 150 is encoded by a code conversion circuit 151 to obtain a first conversion result having a resolution of 3 bits.

By the way, since the A/D converter according to the present invention has a comparator 37 for overrange detection, its human/D conversion characteristics are different from conventional A/D conversion characteristics, and the number of conversion steps in which the digital code changes is 1. There are many. Therefore, the overall conversion characteristics of the analog input are (2n-1) as shown in Figure 3A.
)/16 (n=1.2...8) This is the first conversion characteristic in which the digital code changes at each point.

Next, the resistances at both ends of the resistor string configuring the voltage divider 100,
In other words, the resistance value of resistor 11 is 几, and the resistance value of resistor 19 is 0.
Set n for each. At this time, a plurality of comparators 30 to 37
Since the held analog voltage remains applied to , only the comparison reference of each comparator has changed. In this state, the same conversion operation as the previous one is repeated to obtain a second conversion result with a resolution of 3 bits. The conversion characteristic at this time becomes a second conversion characteristic in which the digital code changes at each point of 2n/16 (n=1.2...8) of the analog input, as shown in FIG. 3B.

The code conversion circuit 151 combines the first conversion result and the second conversion result to output a 4-bit digital signal having the conversion characteristics shown in FIG.
513. This is because by making the resistance values of the resistors at both ends of the resistor string that makes up the voltage divider variable, the number of voltage dividers increases by twice as many as in a conventional voltage divider, and at equal intervals. This is possible because standards can be created. Further, when the code conversion circuit 151 receives the second conversion result, if the output of the comparator 37 for overrange detection is at a low level, that is, "0", the held analog voltage is higher than the reference voltage VR. It is determined that the overrange signal is large, and an overrange signal is output to the output terminal 514.

As explained above, in a parallel comparison type A/D converter that originally only has a resolution of 3b1, the resistance values of the resistors at both ends of the resistor string constituting the voltage divider are made variable in two values, and By simply adding one comparator to detect the range and changing the position detection logic circuit and code conversion circuit, the resolution increases by 1 bit, resulting in a total of 4 bits.
Moreover, the parallel comparison type A/ has an automatic range detection function.
It can be a D converter. In addition, in order to make the resistance values of the resistors at both ends of the resistor string constituting the voltage divider variable in two values, the resistor 11 is shown in FIG. 4 (al), and the resistor 19 is shown in FIG. 4 (b). In this way, a circuit consisting only of a resistor having the same resistance value as the other resistors 12 to 18 and the switch SW can be used.

Incidentally, although the description has been made so far assuming that the number of bits N that the parallel comparison type A/D converter has before implementing the present invention is 3, it is clear that N can take any integer value. Also, so far we have explained that the resistance values of the resistors at both ends of the resistor string that make up the voltage divider are variable in two values, but by combining the results of four conversions as variable in four values. , 92 bits increase, p 3 bits increase by combining the conversion results of 8 times as 8-value variables, and in general, [Abit increases by combining 2A conversion results as 2A value variables it is obvious. Assuming this, the resistance value of the lowest end of the resistors located at both ends of the resistor string that constitutes the voltage divider, that is, the resistor connected to the second reference voltage, is the resistance value of the other resistors, where R is 2A-k)・几/2A(k=o, 1.2...
2A-1), the resistance value of the resistor connected to the top end, that is, the first reference voltage, is -R.
/2A (k=0.1.2...2A-1) is fine. Here, A is the number of bits increased by implementing the present invention, and can be any integer value.

FIG. 5 shows another embodiment of the present invention in which N=2. This is the case when A=2. Here, N is the number of bits that the A/D converter has before implementing the present invention, and A is the number of bits increased by implementing the present invention. In the figure, reference numeral 100 denotes a voltage divider, which is composed of a plurality of resistors 11 to 16 and 19, and the connection points between these resistors form outputs 20 to 23, respectively. The resistance values of resistor 12 and resistor 16 are both R/2, and resistor 1
All resistance values from 3 to 15 are R. Resistor 11 and Resistor 1
The resistance value of 9 can be changed to 60R, 103, 69n, and IR, and the sum of the resistance values of resistor 11 and resistor 19 is 6OR, 28R, 121 (, 4). Therefore, the overall resistance value of the voltage divider 100 is 641(,,32R,16)
? ,.

It will be one of 8R. Therefore, by setting the resistance values of the resistors at both ends of the voltage divider array that constitute the voltage divider 100, that is, the resistance values of the resistor 11, to be OR, and the resistance value of the resistor 19 to approximately 60, the overall resistance value of the voltage divider 100 is set to 64.几, the conversion characteristic becomes the first conversion characteristic shown in FIG. 6A, and
The resistance value of resistor 11 is 3 - R1 The resistance value of resistor 19 is 103
If the overall resistance value of the voltage divider 100 is set to 32R, the conversion characteristic will be the second conversion characteristic shown in FIG. 6B, and the step width will be twice that of the first conversion characteristic. becomes. By sequentially changing the resistance values of the resistor 11 and the resistor 19, the conversion characteristics become as shown in the third conversion characteristic shown in Fig. 6C and the fourth conversion characteristic shown in Fig. 6, and the step width is also changed. They are four times and eight times the first conversion characteristic, respectively. Therefore, the overall conversion characteristic is 4b as shown in Figure 6.
It becomes a nonlinear characteristic with IT resolution.

Further, the plurality of outputs 20 to 23 of the voltage divider 100 are connected to comparison reference input terminals of the plurality of comparators 30 to 33, respectively. By the way, the comparator 33 is provided for overrange detection. A position detection logic circuit 150 is composed of a plurality of logic gates 40 to 43, and the output of the position detection logic circuit 150 is connected to a code conversion circuit 151 having digital outputs 510 to 513 and an overrange output 514. Further, 110 is a sampling circuit that samples the analog input signal, and operates according to the sampling clock f8.

The operation will be explained below according to FIG. First, resistor 11
The first conversion is performed by setting the resistance of the OR% resistor 19 to 60, respectively, to obtain a first conversion result having a resolution of 2 bits. If an overrange is detected in the first conversion,
A second conversion is performed by setting the resistance value of the resistor 11 to one value and the resistance value of the resistor 19 to four values to obtain a second conversion result having a resolution of 2 bits. If no overrange is detected in the second conversion, the code conversion circuit 151 converts the first conversion result and the second conversion result into 4b.
It outputs the digital signal of it to output terminals 510-513. Conversely, if overrange is detected in the second conversion,
Set the resistance value of resistor 11 to T[1 and set the resistance value of resistor 19 to 69R.
Set each and repeat the conversion. In this way, by sequentially changing the resistance values of resistor 11 and resistor 19 and repeating the conversion until no overrange is detected, the sixth
Nonlinear A/D conversion with 4-bit resolution can be performed with the conversion characteristics shown in the figure. Also, by having a comparator for overrange detection, each conversion can be smoothly connected to the next conversion.

By the way, in FIG. 5, the resistors 11 and 12 are combined into one resistor 11', and the resistors 16 and 19 are combined into one resistor 19', and the resistors 11' and 19'
and can be made variable resistances, respectively, and the resistance 1
It goes without saying that different conversion characteristics can be obtained by changing the way the resistance values of resistor 1 and resistor 19 or resistor 11' and resistor 19' are changed.

As explained above, the present invention, like the conventional parallel comparison type A/D converter, requires about twice as many comparators as before for each bit of increase in resolution. Since no other special circuit is required, it is possible to provide a parallel comparison type A/D converter that is relatively simple and easy to configure as a monolithic integrated circuit, and the effects of the present invention are very large.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an A/D converter using a conventional parallel comparison method, and FIG. 2 is a circuit diagram showing an example of a parallel comparison type A/D converter according to the present invention.
The circuit diagram of the converter, Figure 3, is the parallel comparison type A/
FIG. 4 is a circuit diagram showing an example of the configuration of a variable resistor; FIG. 5 is a circuit diagram showing another embodiment of the parallel comparison type A/D converter according to the present invention; Figure 6 is the 5th
It is a figure which shows the conversion characteristic of the parallel comparison type A/D converter shown in a figure. In addition, in the same figure, 10, 100 ...... voltage divider 11 ~
19 ......Resistance 30-37 ......Comparator 50.150
......Position detection logic circuit 51.151
...... Code conversion circuit 110 ...
......It is a coupling circuit. Agent Patent Attorney Gomoku Uchihara, VRVs Vcc Figure 1 VRV5 y6 Figure 72 Over lens 70 input Figure 3 tz (a) (b) Figure 4 VRVs VC Figure 75

Claims (1)

[Claims] (1) An input means for an analog input signal, and outputs from respective connection points of a plurality of resistors connected in series between the first reference voltage and the second reference voltage are compared with the analog input signal as a reference value. A parallel comparison type analog-to-digital conversion device comprising a plurality of comparators for comparing the magnitudes of , a position detection logic circuit that receives the outputs of the plurality of comparators, and a code conversion circuit that receives the outputs of the position detection logic circuits. The resistor is configured such that the resistance values located at both ends of the resistor string can be varied, and the resistance values of the resistors located at both ends of the resistor string are changed to perform analog-to-digital conversion multiple times, Those multiple analogs
A parallel comparison type analog-to-digital converter characterized in that digital conversion results are synthesized by a code conversion circuit.