JPH04160446A - Multi-port memory - Google Patents

Abstract

PURPOSE:To shorten an access time without any conflict with an access request from another port by sending data from a data register to a port by a read controller and sending no read request to a bank. CONSTITUTION:At a read request, a port controller 25 commands respective controllers 5 - 8 to read data out of their banks corresponding to an address ALH while ignoring an address ALL when a comparison result signal SS indicates a discrepancy. At the same time, data buffers of banks corresponding to the address ALL are commanded to send data to an A port. Further, the controller 25 commands the data buffers of the banks corresponding to the address ALL to send data to the A port if the signal SS indicates a coincidence when the read request is made. Further, the controller 25 sends a command for writing the data in entries corresponding to the address ALH when a write request is made.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a multiport memory, and more particularly, to a multiport memory having multiple ports and interleaved banks.

[Conventional technology]

An example of a conventional multi-port memory of this type is shown in FIG. This multi-port memory 51 has A port 52°B port) 53. It has three ports of C port 54, and
Four interleaved banks 10.11, 12.
It has 13. That is, each bank 10, 11, 1
2.13 data addresses are consecutive, and in one bank, data addresses are every three. Controllers 55, 56, provided for each bank.
57 and 58 control access to each bank based on the control signal CC and address AL from each port. It also controls which of the data buffers 65, 66, 67, and 68 data is sent to the port. Next, the operation will be explained. The A port 52 has a lower address AL and an upper address AH.
Assume that a read request is made by control signal C. The A port 52 determines whether data to be read exists in the multiport memory 51 based on the upper address AH. When the address is in the multiport memory 51, the lower address AL is output to the controllers 55, 56, 57, and 58. It also outputs a read request as a control signal CC. Each controller 55, 56, 57, 58 determines whether the data to be read is in its own bank based on the lower address AL. Assuming that the data is currently in the bank 10, the controller 55 reads the data to be read from the bank 10, and transfers the data to the Δ port 52 via the data buffer 65.
Send the read data to. Other consoles) Roller 5
6,57°58 does nothing. When there is an access request from another port to data in a bank that is being accessed by one port, the controller waits for the access request from the other port until the access from the one port is completed. let Additionally, when multiple ports request access to data in the same bank at the same time, the controller
A predetermined high priority port is made accessible and access requests from other ports are made to wait.

[Problem to be solved by the invention]

As described above, in conventional multi-port memories, when access conflict occurs between multiple ports, access may not be possible and the memory may be forced to wait. For this reason, there is a problem in that the access time appears to be long at the port on the waiting side. SUMMARY OF THE INVENTION An object of the present invention is to provide a multiport memory that reduces the probability of access conflicts and shortens the apparent access time.

[Means to solve the problem]

The multi-port memory of the present invention has a multi-port memory having a plurality of ports and a plurality of interleaved banks, and provides a data register in each of the plurality of banks corresponding to at least one port selected from the plurality of ports. In addition, in response to a read request from the selected port, it is determined whether or not the data to be read exists in the data register, and if there is, the data is sent from the data register to the selected port, and if there is not, the data is read. The target data and the data following it are read from each bank and stored in the data buffer, and the data to be read is sent to the selected port, while in response to a read request from a port other than the selected port. The device is characterized in that it is provided with a read controller that executes control to read the data to be read from one of the banks and send it to the port. In the above configuration, it is preferable that the port selected from among the plurality of ports is a port that successively accesses data at consecutive addresses, such as a DMA port. Preferably, the read controller further includes timer management means for managing the validity period of data read from the bank and stored in the data register.

[Operation] When a read request is received from a selected port, data including the data to be read and having consecutive addresses is simultaneously read from all banks. Each read data is stored in a data register corresponding to each bank. When a read request is made for certain data, there is a high probability that the next read request will be issued for data whose address is continuous with that data, but that data has already been stored in the data register. When the data to be read is stored in the data register, the read controller sends the data from the data register to the port and does not issue a read request to the bank. Therefore, the probability of conflict with access requests from other ports is reduced. That is, the probability that each port is made to wait is reduced, and the above access time is apparently shortened.

【Example】

Hereinafter, this invention will be explained in more detail with reference to embodiments shown in the drawings. Note that this invention is not limited to this. FIG. 1 shows a multiport memory 1 according to an embodiment of the present invention.
FIG. In this multiport memory 1, the C port 54 and banks 10 to 13 are the same components as those in the conventional multiport memory 51 described above. Note that each bank 10 to 13 may be a DRAM,
High speed SRAM may also be used. A port 2 and B port 3 have the following configuration. However, since A port 2 and B port 3 have the same configuration, only A port 2 will be explained. As shown in FIG. 2, the A port 2 includes an address decoder 21, an address register 22, and an address latch 23.
and address comparator 24. It consists of a port controller 25 and a timer 26. The address decoder 21 decodes the upper address AH, and when the address corresponds to banks 10 to 13,
A selected signal SL is output. The address register 22 reads and outputs the lower address AL when the selection signal SL is output. The address ALL on the output side is the lower two bits of the address AL, and corresponds to each bank 10-13. Address A
LH is the bits excluding the lower two bits of address AL,
It corresponds to the address of data in each bank 10-13. The address latch 23 stores the previous value of the address ALH. The address comparator 24 is connected to the address latch 23.
The previous address ALH and the current address A stored in
L'H and the comparison result signal S of match or mismatch.
Output S. If the comparison result signal SS does not match when a read request is made by the control signal C, the port controller 25 sends the address ALL to each of the controllers 5 to 8.
The control signal CCX instructs the bank to read the data of the own bank corresponding to the address ALH while ignoring the address ALH. At the same time, the read control signal RC instructs the data buffer of the bank corresponding to the address ALL to send data to the A port. Further, when a read request is made by the control signal C, the port controller 25 outputs the control signal CCX if the comparison result signal SS matches the address ALL.
A read control signal RC instructs the data buffer of the bank corresponding to the bank to send data to the A port. Further, when the port controller 25 receives a write request using the control signal C, it instructs the port controller 25 to write data to the entry corresponding to the address ALH in the bank corresponding to the address ALL using the control signal CCX. At the same time, data from port A is read into the data buffer of the bank corresponding to address ALL.
Command is given by read control signal RC. Furthermore, at this time, if the comparison result signal SS from the comparator 24 is a match, the address latch 23 and the timer 26 are cleared,
The data stored in the data registers of data buffers 15 to 18 are invalidated. The timer 26 “ignores address ALL and
After issuing the command to read the data of the own bank corresponding to LH, if there is a read request again within a predetermined time and the condition that the comparison result signal SS matches is not established at that time, the address latch 23 is cleared. and data bar
The data stored in the data registers of the amplifiers 15 to 18 are invalidated. It is preferable that the time of the timer 26 be set to a time slightly longer than the read interval in the case of continuous reading via the A port 2. In the case of DMA, it is on the order of several μsec. Note that the address latch 23. Comparator 24° port controller 25 and timer 26 include the function of a read controller. Returning to FIG. 1, controllers 5 to 8 receive control signals CCX
is decoded, and if the content is "a command to ignore address ALL and read data corresponding to address ALH", it is followed. Other than this function, it is the same as before. That is, except in the case of the above-mentioned command, the address ALL of the address latch is decoded, and only when the value corresponds to the own bank, it operates according to the command of the control signal CCX or CC. Further, the corresponding data buffers 15 to 18 are notified of information on which port is accessed to the own bank and information on the contents of the access (read/write). Further, the controllers 5 to 8 arbitrate access conflicts. In addition, whether it is A port 2 or B port 3, "Address AL
For example, if the C port 54 is accessing the bank 11 when the command to ignore L and read the data corresponding to the address ALH is issued, the controller 6 will read the data corresponding to the address ALH until the access by the C port 54 is completed. port 2
Alternatively, the controller 5, 7.8 makes the read request from the B port wait, but at this time, if the other banks 10, 12.13 are not being accessed, the controller 5, 7.8 receives the read request from the A port 2 or the B port. and execute the command immediately. The data buffers 15 to 18 have a register corresponding to the A port, a register corresponding to the B port, and a buffer corresponding to the 7C port. Then, when the information notified by controllers 5 to 8 is "read request from A port", the register corresponding to A port is
Set the data read from the bank. Data is sent from the register to A port 2 in accordance with read control signal RC from A port. Also, the information notified by the controllers 5 to 8 is “B
If it is a read request from a port, the data read from the bank is set in the register corresponding to the B port. Data is sent from the register to B port 2 in accordance with read control signal RC from B port. Also, the information notified by the controllers 5 to 8 is “C
If it is a read request from a port, the data read from the bank is sent to the C port 54 via the buffer corresponding to the C port. Furthermore, the data buffers 15 to 18 are connected to the controller 5.
When the information notified in steps 8 to 8 is a "write request from port A" or "write request from port B," the data from the port is written to the register. Then, write from the register to the corresponding bank. When the information notified by controllers 5 to 8 is "write request from C port", the data from C port is
Read through the buffer and write into the bank. In the multi-port memory 1 described above, when A port 2 or B port 3 sequentially reads data at consecutive addresses, three out of four read requests are sent to banks 10 to 13.
Since data is read from the register of the data buffer without accessing the data buffer, the probability that access conflict with other ports will occur is 1/4. Therefore, the access time is apparently reduced. Furthermore, since data is read from the faster registers rather than from the slower banks 10 to 13, the access time is shortened in this respect as well. Furthermore, when writing data from the A port 2 or the B port, the port controller 25 can complete the handshake with the outside at the time the data is written to the register. will also be shortened. Other embodiments include those in which the number of banks is other than four. The effect of this invention becomes more significant as the number of banks increases. Additionally, there are devices with a number of ports other than three.

【Effect of the invention】

According to the multiport memory of the present invention, the probability of access conflict occurring is reduced, and the apparent access time can be shortened. Furthermore, in the case of a read/write operation using a port provided with a data register, the access time can be shortened due to the high speed of the data register.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multi-port memory according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the A port in the multi-port memory shown in FIG. 1, and FIG. 3 is a block diagram of a conventional multi-port memory. It is a block diagram of an example.

[Explanation of symbols]

1...Multi-port memory 2...A port 3...B port 54 ・C ports 5 to 8...Controller 10 to 13...Banks 15 to 18...Data buffer 21...Address Decoder 22...Address register 23...Address latch 24...Comparator 25...Port controller roller 26...Timer. Applicant Yokogawa Medical System Co., Ltd. Agent
Patent attorney: Shinshibe Aruchika Patent attorney: Katsufumi Izumi

Claims (1)

[Claims] 1. In a multi-port memory having a plurality of ports and a plurality of interleaved banks, a data register is provided in each of the plurality of banks corresponding to at least one port selected from the plurality of ports. In addition, in response to a read request from the selected port, it is determined whether or not the data to be read exists in the data register, and if there is, the data is sent from the data register to the selected port, and if there is not, the data is read. The target data and the data following it are read from each bank and stored in the data register, and the data to be read is sent to the selected port, while in response to a read request from a port other than the selected port. A multi-port memory characterized in that it is provided with a read controller that executes control to read data to be read from one of the banks and send it to the port. 2. The multi-port memory according to claim 1, wherein the read controller further comprises timer management means for managing the validity period of data read from the bank and stored in the data register.