JPH04155928A - Production of semiconductor device - Google Patents

Abstract

PURPOSE:To make flat the surface consisting of an interlayer insulating film and metal wirings of the first layer to prevent disconnection to be generated at the stepped region of a metal wiring of the first layer by forming a groove corresponding to a pattern of the metal wiring of the first layer to an interlayer insulating film between a lower wiring layer formed on a semiconductor substrate surface and the metal wiring of the first layer and also forming an aperture between the lower wiring layer and the metal wiring of the first layer at the prescribed area of the groove, forming a metal film and organic film on the entire surface, then etching back these films to form the metal wiring of the first layer. CONSTITUTION:An oxide film 2 is formed on the surface of a silicon substrate 1 and moreover a silicon electrode 3 and source/drain diffused layer 4 are formed. Thereafter, grooves are formed to the region other than the metal wiring forming area at the surface of an insulating film 5 deposited on the entire surface. After forming an aperture 7a on an insulating film 5a and an oxide film 2 of the groove, a metal film 8a is deposited on the entire surface. An organic film 10 is coated on the entire part and is then etched back. Thereby, the groove and aperture 7a are filled with the metal film 8a, a metal wiring 9a is formed and thereby the surface of semiconductor substrate is flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming lower layer metal wiring in a semiconductor device having multilayer metal wiring.

[Conventional technology]

An example of a conventional method for forming lower layer metal wiring in a semiconductor device having multilayer metal wiring will be described using vertical cross-sectional views in the order of steps shown in FIGS. 2(a) to 2(e). This conventional semiconductor device manufacturing method consists of a silicon gate electrode, a source and
This is an example of a method for forming a first layer of metal wiring in a lower wiring layer made of a drain diffusion layer.

First, as shown in FIG. 2(a), the surface of the silicon substrate 1 is oxidized by a gate oxide film and a field oxide film. 2
are formed, a silicon gate electrode 3 is formed, and a source/drain diffusion layer 4 is formed.

Thereafter, an insulating film 5 that will become a glabellar insulating film is deposited on the entire surface.

Next, as shown in No. 21g(b), the silicon gate electrode 3. Openings 7 are then formed in the insulating film 5 and oxide film 2 on predetermined positions of the source/drain diffusion layer 4 using isotropic etching and anisotropic etching.

Next, as shown in FIG. 2(c), a metal film 8 is deposited over the entire surface.

Subsequently, as shown in FIG. 2(d), a photosensitive resin film 6 corresponding to the pattern of the metal wiring is formed on the surface of the metal film 8.

Finally, as shown in FIG. 2(e), the metal film 8 is etched using the photosensitive resin film 6 as a mask.
is removed, and a metal wiring 9 made of the metal film 8 is formed.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, at the stage when the first layer of metal wiring is formed, the film thickness of the metal wiring becomes a step on the surface of the semiconductor substrate, and further metal wiring is formed in the upper layer to form a multilayer metal wiring. When creating a wiring structure, the presence of this step causes disconnection of the upper layer metal wiring.

In addition, from the perspective of the photolithography process, patterns are becoming finer every year, and the two-width spacing between metal interconnects is also becoming smaller. In the process, the presence of the above-mentioned steps lowers the resolution of the photosensitive resin film, contributing to the suppression of miniaturization.

There is also a method of using an SOG film as an insulating film between the eyebrows between multilayer metal wiring, but in this case, dust generated by the SOG film, cracks in the SOG film, and thermal stress applied to the underlying metal wiring during heat treatment of the SOG film are also available. There were other problems.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the step of forming a metal wiring on a semiconductor substrate having a predetermined lower wiring layer and an insulating film, the step of forming a groove in the insulating film in a region where the metal wiring is to be formed; A process of providing an opening reaching the lower wiring layer at a predetermined position of the trench, a process of depositing a metal film on the entire surface, a process of coating an organic film on the entire surface, and etching back to form the edge and the opening as described above. The method includes a step of forming an embedded metal wiring using a metal film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(i) are longitudinal cross-sectional views showing steps in order to explain an embodiment of the present invention. This embodiment is a method of manufacturing a semiconductor device in which a first layer of metal wiring of a multilayer metal wiring is formed on a lower wiring layer consisting of a silicon gate electrode and source/drain diffusion layers.

First, an oxide film 2 consisting of a gate oxide film and a field oxide film is formed on the surface of a silicon substrate 1, a silicon gate electrode 3 is formed, and a source/drain diffusion layer 4 is formed. After that, an insulating film 5a that will become a glabellar insulating film is deposited on the entire surface [
As shown in FIG. 1(a), the thickness of this insulating film 5a is greater than that of the conventional insulating film by an amount corresponding to the thickness of the first layer of metal wiring.

Next, a pattern made of a photosensitive resin film 6a is formed on the surface of the insulating film 5a in a region other than the metal wiring forming region [FIG. 1(b)]. This pattern is an inverted pattern of the metal wiring pattern. Subsequently, the photosensitive resin film 6a
is used as a mask, and grooves are formed by anisotropic etching such as RIE. The depth of this groove is equal to the film thickness of the metal wiring [FIG. 1(C)], and then the photosensitive resin film 6a is removed [FIG. 1(d)].

Next, silicon gate electrode 3. Then, an opening 7a is formed in the insulating film 5a and the oxide film 2 in the groove portion above the predetermined position of the source/drain diffusion layer 4 using isotropic etching and anisotropic etching [Fig. e)).

Subsequently, a metal film 8a is deposited on the entire surface [FIG. 1(f)]
. Here, the thickness of the metal film 8a is set so that the surface of the metal film 8a is higher than the upper end of the groove in the groove portion.

Subsequently, an organic film 10 for planarization is applied to the entire surface [
Figure 1 (g)]. The organic film 10 is, for example, a photosensitive resin film,
It consists of a styrene resin film, etc.

Finally, etchback is performed by anisotropic etching [FIG. 1(h)]. This etch process is continued until the surface of the insulating film 5a other than the groove portion is exposed. As a result, the groove and the opening 7a are filled with the metal film 8a, and a metal wiring 9a is formed [FIG. 1(i)]. At this stage, the surface of the semiconductor substrate is planarized.

Although this embodiment describes the method for forming the first layer of metal wiring in a multilayer metal wiring, it is also possible to apply the present invention to the metal wiring in the upper layer of the multilayer metal wiring.

Furthermore, although this embodiment has been described with respect to a method of manufacturing an MO8 semiconductor device having a multilayer metal wiring structure, the present invention can also be applied to a method of manufacturing other devices, such as a method of manufacturing a bipolar semiconductor device.

〔Effect of the invention〕

As explained above, the present invention provides a method for forming a first layer of metal wiring in a semiconductor device having a multilayer metal wiring structure, in which a lower wiring layer formed on a surface of a semiconductor substrate and a first layer of metal wiring are formed. A groove corresponding to the pattern of the first layer metal wiring is formed in the insulating film between the eyebrows, and an opening between the lower wiring layer and the first layer metal wiring is formed at a predetermined location in the groove, and the entire surface is A first layer of metal wiring is formed by forming a metal film and an organic film and performing etchback.

As a result, an insulating film between the eyebrows is formed between the lower wiring layer and the first layer of metal wiring formed on the surface of the semiconductor substrate.

The surface formed by the first layer of metal wiring and the first layer of metal wiring is flattened.

As a result, in the metal wiring formed on the first layer metal wiring, the disconnection that occurs due to the step difference in the first layer metal wiring no longer occurs.

In addition, in the photolithography process for forming the metal wiring formed on the first layer metal wiring, since the base is flat, factors that inhibit the resolution of the photosensitive resin are removed, and miniaturization is facilitated. It becomes possible.

Furthermore, according to the present invention, there is no need to intentionally use an SOG film as an insulating film between the eyebrows, and dust generated by the SOG film can be removed.
Problems such as cracks in the SOG film and thermal stress imparted to the underlying metal wiring when heat-treating the SOG film can be avoided.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) are vertical cross-sectional views in order of steps for explaining an embodiment of the present invention, and FIGS. 2(a) to (e) are for explaining a conventional method of manufacturing a semiconductor device. FIG. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Silicon gate electrode, 4... Source/drain diffusion layer, 5°5a... Insulating film, 6.6a... Photosensitive resin film , 7°7a...opening, 8,8a...metal film, 9,9a...
...Metal wiring, 10...Organic film.

Claims (1)

[Scope of Claims] A step of forming a metal wiring on a semiconductor substrate having a predetermined lower wiring layer and an insulating film, a step of forming a groove in the insulating film in a region where the metal wiring is to be formed; A step of providing an opening that reaches the lower wiring layer at a predetermined position, a step of depositing a metal film on the entire surface, a step of applying an organic film on the entire surface, and a step of etching back to form the trench and the opening. A method for manufacturing a semiconductor device, comprising the steps of: forming the metal wiring by embedding the metal film.