JP2555958B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a multi-layer wiring.

[0002]

2. Description of the Related Art With the miniaturization of LSIs, the wiring pitch has been reduced, and at the same time, the number of wiring layers has been increased. This increase in the number of wiring layers causes a height difference (elevation difference) in the interlayer film (interlayer insulating film). Therefore, in a lithography technique on such an uneven interlayer film, for example, a patterning process for forming an upper aluminum wiring or a through hole, the step difference of the interlayer film affects the patterning accuracy of the photoresist film.

Next, patterning characteristics in a stepped region will be described.

As a factor that impedes pattern accuracy when patterning a photoresist film coated on a surface having a difference in altitude, there are variations in the film thickness of the photoresist film in the vicinity of the step portion, and a high altitude region and a low altitude region. There is a difference in the focal length.

Generally, the pattern shape of the photoresist film is determined by the exposure image, the exposure intensity, and the reflection exposure intensity from the base.

In the photoresist film in the high altitude region,
The pattern shape of the photoresist film is determined by the exposure image and the exposure intensity. In particular, in a positive photoresist film in an area having an altitude higher than the depth of focus margin, thinning of the pattern shape due to the spread of the exposure image poses a problem, and changes in exposure intensity can be almost ignored. On the other hand, in a low-altitude region near the step, the decrease in resolution due to an increase in the photoresist film thickness becomes a problem, and it is necessary to flatten the interlayer film when forming multilayer wiring.

The interlayer film process can be roughly classified into a local planarization process utilizing the flatness of the coating film and a global planarization process utilizing a technique other than the coating film.

Examples of the local flattening process include resist etchback using a resist coating film and SOG (spin).
on-glass) coating film process is common.
These interlayer flattening techniques suppress local fluctuations in the photoresist film thickness, and thus can suppress a decrease in focus margin due to fluctuations in the photoresist film thickness. Therefore, the local planarization technique has been used for a device in which the problem of the depth of focus due to the reduction in the wiring pitch and the increase in the wiring film thickness does not occur.

FIG. 4 shows a device having a three-layer wiring specification.
It is a figure which shows the minimum design dimension dependence of the maximum device height difference generated under layer wiring, and the pattern size dependence of the depth of focus margin.

As shown in FIG. 4, as the minimum design dimension is reduced, the photoresist film thickness is also reduced. Therefore, 3
The wiring film thickness generated under the layer wiring must be thin,
The device maximum altitude difference also decreases. However, if the depth of focus is reduced due to the reduction in the minimum design pattern size beyond the reduction in the maximum elevation difference, the photoresist films in the high and low elevation regions cannot be patterned at the same time. That is,
Devices with a minimum device design dimension of 0.8 μm or less cannot be realized without the introduction of global planarization technology.

The global interlayer flattening technology is as follows:
Chemical mechanical polishing (Chemica)
There is a selective oxide film growth method using a chemical mechanical deposition (CVD) method or a chemical vapor deposition method (hereinafter referred to as CVD), or a block resist method using an inversion mask of an underlying wiring pattern. Among them, the block resist method can realize global planarization without introducing a new device, and therefore, the IEE Transactions on Electron Device (I
EEE Transactions on Elect
ron Devices, 1988, 135, 1829, or IEE Transactions on Semiconductor Manufacturing (IEEE Transactions on).
Semiconductor Manufactur
ng) Widely used as described in 1988, page 140, etc.

FIGS. 5A to 5D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first example of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 5A, a metal film is deposited and patterned on a silicon oxide film 2 provided on a silicon substrate 1 to form wiring 3, and a surface including the wiring 3 is formed. A silicon oxide film 4 is formed as an interlayer film by a plasma CVD method.
Is deposited.

Next, as shown in FIG. 5B, the first photoresist film 5 is applied on the silicon oxide film 4, and then the photoresist film 5 is formed by a lithography technique using a reversal mask of the pattern of the wiring 3. Pattern.

Next, as shown in FIG. 5C, a second resist film 6 is applied to the surface including the photoresist film 5 to flatten the surface.

Next, as shown in FIG. 5D, the selection ratio between the photoresist films 5 and 6 and the silicon oxide film 4 is 1: 1.
Etch back by anisotropic etching, and etching is performed until the surface of the silicon oxide film 4 under the photoresist film 5 is exposed to planarize the surface.

FIG. 6 is a diagram showing the relationship of the flatness of the interlayer film with respect to the distance between the wiring pattern and the inversion mask pattern at this time.

As shown in FIG. 6, when a block resist film is formed in a region where the silicon oxide film 4 near the wiring pattern and the reverse mask pattern overlap, the silicon oxide film 4 is protected during etching back, and a step is formed. On the other hand, if the space between the wiring pattern and the reverse mask pattern is too wide,
A recess is formed on the coated surface of the second photoresist film 6 to form a step in the interlayer film (generally called bat wing), and the shape of the photoresist film is transferred to the interlayer film.
Therefore, the inversion mask pattern needs to have a margin from the wiring pattern by the thickness of the interlayer film. As a method of eliminating the margin problem between the inversion mask pattern and the wiring pattern, there is an example of using isotropic etching of an oxide film in the process (see Japanese Patent Laid-Open No. 60-245225).

FIGS. 7A to 7C are sectional views of a semiconductor chip in the order of steps for explaining the second example of the conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 7A, the wiring 3 is formed on the silicon oxide film 2 on the silicon substrate 1 by the same process as the above-mentioned first example, and the surface including the wiring 3 is formed. After the silicon oxide film 4 is formed on the silicon oxide film 4, a photoresist film 5 is applied on the silicon oxide film 4 and patterned by using an inversion mask having an inversion pattern of the pattern of the wiring 3.

Next, as shown in FIG. 7B, the surface of the silicon oxide film 4 is isotropically etched with hydrofluoric acid to a thickness corresponding to the step by using the photoresist film 5 as a mask and removed.

Next, as shown in FIG. 7 (c), the photoresist film 5 is removed to form an interlayer film which eliminates the difference in elevation on the upper surface.

[0023]

In the conventional method of manufacturing a semiconductor device, in the first example, it is necessary to prepare the reversal mask by the number of layers of the interlayer film. Furthermore, since the margin between the wiring pattern of the inversion mask and the inversion mask pattern to be created depends on the interlayer film thickness in the interlayer film formation process,
A mask is required for each interlayer film process. Further, in the margin area between the wiring pattern and the inversion mask pattern, due to the limitation of the minimum size of the resist pattern, an area where the block resist is not formed is formed, and there is a problem that the planarization of the interlayer film locally deteriorates.

Further, in the second example, hydrofluoric acid, which is widely used for isotropic etching of a silicon oxide film, etches an aluminum film of a wiring material, and therefore isotropic at a thickness larger than that of the grown silicon oxide film. Cannot be etched. as a result,
There is a problem that a corrugated step is formed in the interlayer film, and an etching residue is generated due to a variation in the coverage of the aluminum film in the patterning of the upper layer aluminum wiring, which easily causes a short circuit between wirings.

[0025]

According to a first method of manufacturing a semiconductor device of the present invention, an interlayer insulating film is formed on a surface including the wiring after selectively forming wiring on an insulating film formed on a semiconductor substrate. Is deposited thicker than the thickness of the wiring, and a height of the interlayer insulating film is increased by using a mask in which a positive type first photoresist film is applied on the interlayer insulating film and then stripe patterns are arranged on the entire surface. Exposing and developing by focusing on a low-temperature region of the interlayer insulating film to form a stripe pattern of the first photoresist film only on the low-elevation region of the interlayer insulating film; and a surface including the first photoresist film. And then planarizing the surface by applying a second photoresist film to the surface of the interlayer insulating film until the surface of the low-elevation region of the interlayer insulating film is exposed to planarize the upper surface of the interlayer insulating film. Including Constructed.

The second semiconductor device manufacturing method of the present invention is
A step of selectively forming wiring on an insulating film formed on a semiconductor substrate and then depositing a first interlayer insulating film on the surface including the wiring to a thickness smaller than the thickness of the wiring; After applying a photosensitive polyimide resin film on the film, using a mask in which stripe-shaped patterns are arranged on the entire surface, exposure and development are performed by focusing on a low-elevation region of the interlayer insulating film to increase the elevation of the interlayer insulating film. A step of forming a stripe pattern of a photosensitive polyimide resin film only in a low region, and a step of applying a polyimide resin film on the surface including the photosensitive polyimide resin film to form a second interlayer insulating film and planarizing the upper surface. It is configured to include and.

[0027]

The present invention utilizes the fact that the depth of focus in exposure of the photoresist film is equal to the elevation difference of the interlayer film, so that the photoresist film in the low altitude region of the interlayer film is exposed in a self-aligned manner. Is flattened.

FIG. 9 is a diagram showing the focus offset dependence of the resist pattern size when a 3.0 μm thick resist film is patterned on the surface of a wafer having an altitude difference of 3 μm.

As shown in FIG. 9, the characteristic of the resist pattern in the high altitude region moves to the lens side by 2 μm from the low altitude region. Therefore, when the focus offset is −2.0 μm or more, the photoresist pattern formed on the high-elevation region is focused, so that the resist pattern is formed on the high-elevation region. On the other hand, 0 μm
In the above focus offset, the resist film existing in the low altitude region is focused, so that the resist film is patterned in the low altitude region, and in the high altitude region, the exposure image spreads and the film slips and the pattern disappears. To do. Here, the conditions for forming a resist film that is selectively formed in a region of low altitude are determined by the mask size, focus offset, photoresist film thickness, and exposure dose.

FIG. 10 is a diagram showing the dependency of the focus offset and the mask size on the wiring film thickness.

As shown in FIG. 10, the wiring film thickness is 1.0 μm.
When the mask size is 1.0 μm, the focus offset is set to 1.5 μm, and when the wiring film thickness is 3.0 μm, the focus offset is 2.0 μm when the mask size is 2.0 μm. By setting it, the photoresist film can be selectively formed in a region having a low altitude. Here, as the photoresist film thickness increases, the depth of focus margin decreases as the exposure amount increases, so the photoresist film thickness is preferably 5 μm or less, and the exposure amount is a thick photoresist generated at the step portion. An exposure amount that allows the film to be resolved is desirable.

[0032]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1A, a metal film such as an aluminum film is deposited to a thickness of 1 μm on a silicon oxide film 2 provided on a silicon substrate 1 and then patterned to form a wiring 3 To form plasma C on the surface including the wiring 3.
The silicon oxide film 4 is formed to a thickness of 2 μm by the VD method.

Next, as shown in FIG. 1B, a positive photoresist film 5 is applied on the silicon oxide film 4 to a thickness of about 3 μm.

Next, as shown in FIG. 1C, for example, 1
Using a mask in which stripe patterns are arranged in a stripe pattern over the entire surface with a width and interval of μm, the focus of the stepper is aligned with the low-elevation area of the silicon oxide film 4 and exposed with energy of 300 mJ / cm ² , and developed and silicon oxide A photoresist film 5a patterned in a stripe shape is formed only on the low-elevation region of the film 4, and the photoresist film 5 in the high-elevation region of the silicon oxide film 4 is removed.

Next, as shown in FIG. 1D, a photoresist film 6 having a thickness of 2 μm is applied on the entire surface to planarize the upper surface. Here, as shown in FIG. 8, the dependence of the local step on the upper surface of the photoresist film on the second photoresist film thickness is as follows.
When the line spacing of the stripe mask is narrower than the line width, the volume in which the second photoresist film is embedded is small, so that the embedding property of the second photoresist film is good. As a result, the flatness after the formation of the interlayer film is also advantageous when the mask line interval is smaller than the line width.

Next, as shown in FIG. 6E, the silicon oxide film is formed under the conditions that CF ₄ and oxygen are used as etching gases and the etching selection ratio between the photoresist film and the silicon oxide film is 1: 1. The entire surface is etched back to flatten the upper surface until the surface of the low-elevation region is exposed.

2 (a) to 2 (c) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

First, as shown in FIG. 2A, after the wiring 3 is selectively formed on the silicon oxide film 2 formed on the silicon substrate 1 by the same process as in the first embodiment, The silicon nitride film 7 with good adhesion to the polyimide resin film
The wiring 3 is deposited to a thickness of nm, and the photosensitive polyimide resin film 8 is applied on the silicon nitride film 7 to a thickness of 2 μm.

Next, as shown in FIG. 2B, a mask in which stripe patterns are arranged in stripes on the entire surface with a width and interval of 1 μm is used, and the focus of the stepper is set on the low-elevation region of the silicon nitride film 7. A total of 300 mJ / cm ² of energy is applied for exposure and development is performed to form a photoresist film 5a patterned in a stripe pattern only on the low-elevation region of the silicon nitride film 7.

Next, as shown in FIG. 2 (c), 300 ° C.
After the heat treatment for about 5 minutes, a polyimide resin film 9 is formed on the entire surface.
It is applied to a thickness of μm and heat-treated at 300 ° C. to form an interlayer insulating film having a flat upper surface.

3 (a) to 3 (d) are sectional views of the semiconductor chip shown in the order of steps for explaining the third embodiment of the present invention.

First, as shown in FIG. 3A, after the wiring 3 is selectively formed on the silicon oxide film 2 formed on the silicon substrate 1 in the same process as in the first embodiment, the wiring is formed. Three
A silicon oxide film 4 is formed on the surface including the silicon by a plasma CVD method. Next, a positive type photoresist film is applied on the silicon oxide film 4 and a mask in which stripe-shaped patterns are arranged is used to align the focus with the low-elevation area of the silicon oxide film 4 to expose and develop it into stripes. The patterned photoresist film 5a is formed only in the low-elevation region of the silicon oxide film 4.

Next, as shown in FIG. 3B, the surface of the silicon oxide film 4 is etched by a thickness equivalent to the height difference of the silicon oxide film 4 using the photoresist film 5a as a mask to form a stripe pattern. Form corresponding grooves.

Next, as shown in FIG. 3C, the photoresist film 5a is ashed and removed by plasma treatment in an oxygen atmosphere.

Next, as shown in FIG. 3D, a silicon oxide film 10 having a thickness of about 600 nm is formed on the surface of the silicon oxide film 4 having a groove formed by atmospheric pressure CVD using tetraethoxysilane and ozone-containing oxygen as source gas. To form an interlayer insulating film having a thickness of 3 .ANG.

[0048]

As described above, according to the present invention, the slip-like pattern of the photoresist film is formed in a self-aligning manner only in the region of the unevenness of the interlayer film where the unevenness is low. The block resist can be formed without forming a mask, and the step of planarizing the interlayer film can be simplified.

[Brief description of drawings]

1A to 1D are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention.

2A to 2D are sectional views showing a process sequence for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view shown in order of steps for explaining a third embodiment of the present invention.

FIG. 4 is a diagram showing a minimum design dimension dependence of a maximum device height difference and a pattern size dependence of a depth of focus margin occurring under a three-layer wiring in a device with three-layer wiring specifications.

FIG. 5 is a cross-sectional view for explaining a first example of a conventional method of manufacturing a semiconductor device, which is shown in a process order.

FIG. 6 is a diagram showing a relationship of the flatness of an interlayer film with respect to a distance between a wiring pattern and a reverse mask pattern in a conventional example.

7A to 7C are sectional views showing the second example of the conventional method for manufacturing a semiconductor device, in the order of steps for explaining the second example.

FIG. 8 is a diagram showing the second photoresist film thickness dependence of a local step on the upper surface of the photoresist film.

FIG. 9 is a diagram showing focus offset dependency of resist pattern size.

FIG. 10 is a diagram showing a wiring step dependency of an optimum focus offset.

[Explanation of symbols]

 1 Silicon Substrate 2,4,10 Silicon Oxide Film 3 Wiring 5,5a, 6 Photoresist Film 7 Silicon Nitride Film 8 Photosensitive Polyimide Resin Film 9 Polyimide Resin Film

Claims (2)

(57) [Claims] 1. A step of selectively forming wiring on an insulating film formed on a semiconductor substrate and then depositing an interlayer insulating film on the surface including the wiring to a thickness greater than the thickness of the wiring, and the interlayer insulating film. The positive type first photoresist film is coated on the surface of the interlayer insulating film, and then the mask is formed by arranging stripe-shaped patterns on the entire surface of the interlayer insulating film. Forming a stripe pattern of the first photoresist film only on the low-elevation area of the substrate, and after applying the second photoresist film to the surface including the first photoresist film to flatten the surface. A step of etching back the entire surface of the interlayer insulating film until the surface of the low-elevation region is exposed to planarize the upper surface of the interlayer insulating film. 2. A step of selectively forming wiring on an insulating film formed on a semiconductor substrate and then depositing a first interlayer insulating film on the surface including the wiring to a thickness smaller than the thickness of the wiring.
After coating a photosensitive polyimide resin film on the first interlayer insulating film, a mask having stripe-shaped patterns arranged all over the surface is used to focus and expose and develop a low-elevation region of the interlayer insulating film. A step of forming a stripe pattern of a photosensitive polyimide resin film only in a region of the interlayer insulating film having a low altitude, and a polyimide resin film is applied to a surface including the photosensitive polyimide resin film to form a second interlayer insulating film. And a step of planarizing the upper surface of the semiconductor device.