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JPH04149783A - Circuit diagram editor - Google Patents

Circuit diagram editor

Info

Publication number
JPH04149783A
JPH04149783A JP2276072A JP27607290A JPH04149783A JP H04149783 A JPH04149783 A JP H04149783A JP 2276072 A JP2276072 A JP 2276072A JP 27607290 A JP27607290 A JP 27607290A JP H04149783 A JPH04149783 A JP H04149783A
Authority
JP
Japan
Prior art keywords
circuit diagram
symbols
pair information
pin pair
tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2276072A
Other languages
Japanese (ja)
Inventor
Nobuko Tanimoto
谷本 伸子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2276072A priority Critical patent/JPH04149783A/en
Publication of JPH04149783A publication Critical patent/JPH04149783A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To speed up the input of a circuit diagram by selecting the start and end points of a connection line after arranging symbols and executing automatic wiring. CONSTITUTION:A user starts plotting by means of a circuit diagram forming tool 103, accesses symbols registered in a cymbol library 102 and arranges the accessed symbols on a screen. In the case of arranging the symbols by means of the tool 103 and drawing a connection line, the start and end points of the connection line are selected in a state almost completing the arrangement of the symbols and the two selected points are stored in a pin pair information storing means 104 as pin pair information. In each arrangement of a symbol, an arranging area is additionally stored in a wiring inhibition area storing means 105. Thus, an automatic wiring means 106 mutually connects the start and end points by a rectangularly bent continuous line based on the obtained pin pair information and the wiring inhibition area. Consequently, a time required for wiring can be shortened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電気系コンピュータ設計支援(CAD)シス
テムの回路図エディタに関し、特に、その配線手段に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit diagram editor for an electrical computer design aid (CAD) system, and particularly to its wiring means.

〔従来の技術〕[Conventional technology]

従来、この種の回路図エディタは、配線を行う時には、
シンボルの位置や全体のバランス等を考えて、線を直角
に曲げる位置も自分で決めてタブレットやマウス等のデ
バイスを用いて一本一本配線をしている。
Traditionally, when wiring, this type of circuit diagram editor
I consider the position of the symbols and the overall balance, decide where to bend the wires at right angles, and wire each wire one by one using a device such as a tablet or mouse.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

−1−述したように従来の回路図エディタでは、配線を
行う時には、シンボルの位置や全体のバランス等を考え
て、線を直角に曲げる位置も自分で決めてタブレッl−
やマウス等のデバイスを用いて一本一本配線をしていく
ため、−本配線するのにも時間がかかり、配線を終わっ
た後に、再び、修正しなければならないという欠点があ
る。
-1- As mentioned above, with conventional circuit diagram editors, when wiring, you have to consider the position of symbols and overall balance, and decide where to bend the lines at right angles.
Since the wires are wired one by one using a device such as a computer or a mouse, there is a drawback that it takes time to wire the wires one by one, and it is necessary to make corrections again after the wires are completed.

〔課題を解決するための手段〕[Means to solve the problem]

本発明J)回路図エディタは、電気系CADシステムで
、論理素子等のシンボルを作成するためのシ〉ポル作成
・編集ツールと、シンボル作成・編集ツールで作成され
たシンボルを格納するシンボルライブラリと、シンボル
ライブラリのシンボルを両面上に配置し接続線を引く回
路図作成ツールと、画面上のシンボルや接続線の移動・
複写・削除を行う回路図編集ツールと、回路図編集ツー
ルで作画された作画データを出図するプロッタ出図ツー
ルとを有する回路図エディタにおいて、回路図作成ツー
ルの接続線を引く機能が接続線の始点と終点の2点のみ
を順次選択し、その2点をピンペア情報とIで格納する
ピンペア情報格納手段と、シンボルが配置されている配
線禁」F領域を記憶する配線禁止領域記憶手段と、配線
禁止領域記憶手段に記憶されている配線禁止領域を避け
て、ピンペア情報格納手段に格納されているピンペア情
報に従って、始点と終点を直角に折れ曲がる連続直線で
結んでいく自動配線手段とを有し、ている。
The circuit diagram editor of the present invention is an electrical CAD system, and includes a symbol creation/editing tool for creating symbols such as logic elements, and a symbol library for storing symbols created with the symbol creation/editing tool. , a schematic creation tool that places symbols from the symbol library on both sides and draws connection lines, and a tool that allows you to move and move symbols and connection lines on the screen.
In a circuit diagram editor that has a circuit diagram editing tool that performs copying and deletion, and a plotter drawing tool that outputs drawing data drawn with the circuit diagram editing tool, the function of drawing connection lines of the circuit diagram creation tool is changed to the connection line. pin pair information storage means that sequentially selects only two points, a start point and an end point, and stores the two points as pin pair information and I; and wiring prohibited area storage means that stores a wiring prohibited area F in which the symbol is arranged. and an automatic wiring means that avoids the wiring prohibited area stored in the wiring prohibited area storage means and connects the start point and the end point with a continuous straight line bent at right angles according to the pin pair information stored in the pin pair information storage means. are doing.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の回路図エディタの構成図、
第2図はどの2点がピンペア情報として選択されたかを
表示している図、第3図は自動配線を行った結果の図で
ある。
FIG. 1 is a configuration diagram of a circuit diagram editor according to an embodiment of the present invention.
FIG. 2 is a diagram showing which two points have been selected as pin pair information, and FIG. 3 is a diagram showing the results of automatic wiring.

第1図において、本実施例の回路図エディタは、シンボ
ル作成・編集ツール1−o]、シンボル・ライブラリ1
02、回路図作成ツール103、回路図編集ツール10
7、プロッタ出図ツール108で構成されている。
In FIG. 1, the circuit diagram editor of this embodiment includes a symbol creation/editing tool 1-o], a symbol library 1
02, Circuit diagram creation tool 103, Circuit diagram editing tool 10
7. Consists of a plotter drawing tool 108.

また、回路図作成ツール103は、ピンペア情報格納手
段104、配線禁止領域記憶手段1゜5、自動配線手段
】−06より構成されている。
Further, the circuit diagram creation tool 103 is composed of a pin pair information storage means 104, a wiring prohibited area storage means 1.5, and an automatic wiring means ]-06.

次に、その動作について以下に説明する。Next, the operation will be explained below.

まず、使用者は、回路図作成ツール103を用いて作画
を始め、シンボル・ライブラリ102に登録されている
シンボルを呼び出して画面上に配置1iLでいく。この
時、もしシンボル・ライブラリ102に登録されていな
いシンボルを使いたいというゲースが生じた場合には、
シンボル作成 編集ツール101を用いてシンボルを作
成し、シンボル・ライブラリ]、02に登録する。
First, the user starts drawing using the circuit diagram creation tool 103, calls up symbols registered in the symbol library 102, and places them 1 iL on the screen. At this time, if a game arises where you want to use a symbol that is not registered in the symbol library 102,
Create a symbol Create a symbol using the editing tool 101 and register it in the symbol library].02.

次に、回路図作成ツール103を用いてシンボルを配置
すると共に、接続線を引でいく。接続線を引く場合、あ
る程度シンボルの配置が済んでいる状態で、接続線の始
点と終点を選択し、選択した2点をピンペア情報とし、
てピンペア情報格納手段104に格納する。そして、こ
のピンペア情報格納手段104を用いて、現在画面上に
描かれているシンボル間のピンペア情報を順次格納して
いく。
Next, using the circuit diagram creation tool 103, symbols are placed and connection lines are drawn. When drawing a connection line, select the start and end points of the connection line after the symbols have been placed to some extent, set the selected two points as pin pair information,
and stored in the pin pair information storage means 104. Then, using this pin pair information storage means 104, pin pair information between symbols currently drawn on the screen is sequentially stored.

また、シンボルを配置する毎に、配線禁止領域記憶手段
105によって配置される領域を追加して記憶していく
、このようにして得られたピンペア情報と配線禁止領域
によって、自動配線手段106を用い、始点と終点を直
角に折れ曲がる連続直線を結ぶ。
Furthermore, each time a symbol is placed, the area to be placed is added and stored in the wiring prohibited area storage means 105, and the automatic wiring means 106 is used based on the pin pair information and wiring prohibited area obtained in this way. , connects the starting point and ending point with a continuous straight line that bends at right angles.

以−トのような手順で接続線を自動生成する。Automatically generate connection lines by following the steps below.

また、回路図編集ツール107を用いて、シンボルや接
続線を移動・複写・削除等を行う。このようにして回路
図を作成し、プロッタ出図ツール108を用いてその作
画データを出図する。
Further, the circuit diagram editing tool 107 is used to move, copy, delete, etc. symbols and connection lines. A circuit diagram is created in this way, and the drawing data is printed using the plotter drawing tool 108.

ここで、第2図は、ピンペア情報格納手段104を用い
て、接続線の始点と終点の情報を格納していく際、画面
上で、どの2点がピンペアとして選択されたかがわかる
ように始点と終点を一本の直線で結んだものを表示して
いる。
Here, FIG. 2 shows the starting point and the ending point on the screen so that it can be seen which two points have been selected as a pin pair when the pin pair information storage means 104 is used to store information on the starting point and ending point of the connection line. The end points are displayed with a single straight line.

また、第3図は、第2図のようになっているピンペア情
報をもとに自動配線手段106を用いて配線を行った結
果を示している。
Further, FIG. 3 shows the result of wiring using the automatic wiring means 106 based on the pin pair information shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、シンボル配置後、
接続線の始点と終点を選択することにより、自動配線を
行うことにしたので、新規配線を−本一本人力していく
手間がなくなり、回路図の入力をスピードアップするこ
とができるという効果がある。
As explained above, according to the present invention, after symbol placement,
Since we decided to perform automatic wiring by selecting the start and end points of the connection lines, we no longer have to manually create new wiring each time, which has the effect of speeding up the input of circuit diagrams. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図エディタの構成図、
第2図はどの2点がピンペア情報として選択されたかを
表示している図、第3図は自動配線を行った結果の図で
ある。 101・・・シンボル作成・編集ツール、102・・・
シンボル・ライブラリ、103・・・回路図作成ツール
、104・・・ピンペア情報格納手段、105・・・配
線禁止領域記憶手段、106・・・自動配線手段、10
7・・・回路図編集ツール、108・・・プロッタ出図
ツール。
FIG. 1 is a configuration diagram of a circuit diagram editor according to an embodiment of the present invention.
FIG. 2 is a diagram showing which two points have been selected as pin pair information, and FIG. 3 is a diagram showing the results of automatic wiring. 101...Symbol creation/editing tool, 102...
symbol library, 103... circuit diagram creation tool, 104... pin pair information storage means, 105... wiring prohibited area storage means, 106... automatic wiring means, 10
7... Circuit diagram editing tool, 108... Plotter drawing tool.

Claims (1)

【特許請求の範囲】  電気系コンピュータ設計支援システムで、論理素子等
の、シンボルを作成するためのシンボル作成・編集ツー
ルと、前記シンボル作成・編集ツールで作成されたシン
ボルを格納するシンボルライブラリと、前記シンボルラ
イブラリのシンボルを画面上に配置し接続線を引く回路
図作成ツールと、前記画面上のシンボルや接続線の移動
・複写・削除を行う回路図編集ツールと、前記回路図編
集ツールで作画された作画データを出図するプロッタ出
図ツールとを有する回路図エディタにおいて、 前記回路図作成ツールの接続線を引く機能が接続線の始
点と終点の2点のみを順次選択し、その2点をピンペア
情報として格納するピンペア情報格納手段と、 前記シンボルが配置されている配線禁止領域を記憶する
配線禁止領域記憶手段と、 前記配線禁止領域記憶手段に記憶されている前記配線禁
止領域を避けて、前記ピンペア情報格納手段に格納され
ている前記ピンペア情報に従って、始点と終点を直角に
折れ曲がる連続直線で結んでいく自動配線手段とを有す
ることを特徴とする回路図エディタ。
[Scope of Claims] An electrical computer design support system, comprising: a symbol creation/editing tool for creating symbols such as logic elements, and a symbol library that stores the symbols created by the symbol creation/editing tool; A circuit diagram creation tool that places symbols from the symbol library on the screen and draws connection lines, a circuit diagram editing tool that moves, copies, and deletes the symbols and connection lines on the screen, and a circuit diagram editing tool that is used to create a drawing. In a circuit diagram editor that has a plotter drawing tool that outputs drawn drawing data, the connection line drawing function of the circuit diagram creation tool sequentially selects only two points, the start point and the end point, of the connection line, and pin pair information storage means for storing as pin pair information; wiring prohibited area storage means for storing a wiring prohibited area in which the symbol is arranged; and automatic wiring means for connecting a start point and an end point with continuous straight lines bent at right angles according to the pin pair information stored in the pin pair information storage means.
JP2276072A 1990-10-15 1990-10-15 Circuit diagram editor Pending JPH04149783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2276072A JPH04149783A (en) 1990-10-15 1990-10-15 Circuit diagram editor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2276072A JPH04149783A (en) 1990-10-15 1990-10-15 Circuit diagram editor

Publications (1)

Publication Number Publication Date
JPH04149783A true JPH04149783A (en) 1992-05-22

Family

ID=17564413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2276072A Pending JPH04149783A (en) 1990-10-15 1990-10-15 Circuit diagram editor

Country Status (1)

Country Link
JP (1) JPH04149783A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014503868A (en) * 2010-11-09 2014-02-13 チップワークス, インコーポレイテッド Visualization of circuits using flight lines

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139868A (en) * 1981-02-25 1982-08-30 Fujitsu Ltd Circuit diagram wiring system
JPS60230268A (en) * 1984-04-27 1985-11-15 Yokogawa Hokushin Electric Corp Automatic searching method of path
JPS61245280A (en) * 1985-04-23 1986-10-31 Sharp Corp Automatic wiring method for logic circuit diagram

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139868A (en) * 1981-02-25 1982-08-30 Fujitsu Ltd Circuit diagram wiring system
JPS60230268A (en) * 1984-04-27 1985-11-15 Yokogawa Hokushin Electric Corp Automatic searching method of path
JPS61245280A (en) * 1985-04-23 1986-10-31 Sharp Corp Automatic wiring method for logic circuit diagram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014503868A (en) * 2010-11-09 2014-02-13 チップワークス, インコーポレイテッド Visualization of circuits using flight lines

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