JPH0414228A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make possible the formation of a two-electrode direct connection structure of a partially overlapping form, to improve the step coverrage and flatness of other electrode and to prevent the generation of a disconnection and the deterioration of current conduction by a method wherein a recess part of a thickness thinner than the thickness of the part other than a part, at which one electrode formed on a semiconductor substrate is directly connected with the other electrode, of the one electrode is formed at the part, at which the one electrode is directly connected with the other electrode, and the one electrode and the other electrode are directly connected with each other. CONSTITUTION:A recess part 6 of a thickness thinner than the thickness of the part other than a part, at which a gate electrode 3 is directly connected with a source electrode 4, of the electrode 3 is formed at the part, at which the electrode 3 is directly connected with the electrode 4, and the electrodes 3 and 4 are directly connected with each other at this part 6 to form a source and gate direct connection part 7. As the step coverage and flatness of the electrode 4 formed into a form to overlap partially with the electrode 3 are improved, the generation of a disconnection is eliminated in the direct connection part 7 and as there is a margin in the sectional area of the part 7, to which a current flows, element characteristics are not deteriorated at the time of current conduction. Moreover, as the step ( d) of the part 7 is small, the generation of the trouble of a short-circuit between different layers is prevented in an upper layer wiring formation process and the reliability of a semiconductor device is improved.

Description

Detailed Description of the Invention (i) A direct connection structure of two electrodes formed on a semiconductor substrate in which one electrode and another electrode are directly connected in a partially overlapping shape, with step coverage and flatness. In a two-electrode direct connection structure in which one electrode formed on a semiconductor substrate is directly connected to another electrode in a partially overlapping shape, the purpose is to improve the connection and prevent wire breakage and deterioration due to current conduction. A recessed part is formed in the part of one electrode that is directly connected to the other electrode, and the thickness is thinner than the other part, and the one electrode and the other electrode are directly connected in the recessed part. Configure.

(Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a two-electrode direct connection structure in which one electrode formed on a semiconductor substrate and another electrode are directly connected in a partially overlapping shape.

With the miniaturization of semiconductor devices 5 and higher integration, the technology of forming fine wiring on a semiconductor substrate and directly connecting two wirings has become important.

[Conventional technology] (Conventional example 1) FIG. 7 is a diagram showing conventional example 1.

3A shows a circuit element, FIG. 1B shows a pattern layout, and FIG. 1C shows an X-Y cross-sectional view.

In FIG. 7, 201 is a GaAs substrate, 202 is an active layer region doped with impurities and forms a source region, a channel, and a drain region, 203 is a gate electrode, 204 is a source electrode, 205 is a drain electrode, and 206 is a source/drain region.
This is a direct gate connection.

In an integrated circuit including a field effect transistor (EFT), as shown in FIG. 7(a), there are many circuit elements that directly connect a gate electrode and a source electrode. In this case, the pattern layout is such that the configuration in which the source electrode 204 runs over the gate electrode 203 (overlamp) is extremely advantageous in minimizing the device area, as shown in 7th [F (b), and is therefore frequently used. ing.

The XY cross-sectional view of the pattern layout shown in FIG. 7(b) becomes as shown in FIG. 7(c). As can be seen from the figure, the step coverage of the source electrode is poor due to the step difference at the edge portion of the gate electrode 203. That is, one step difference (Δd) is large. Therefore, the cross-sectional area of the metal wiring through which the current flows becomes very small, and the characteristics of the element deteriorate when the current is applied. There was a problem.

(Conventional Example 2) FIG. 8 is a diagram showing Conventional Example 2, which was made to solve the drawbacks of Conventional Example 1 shown in FIG.

In FIG. 8, 301 is a GaAs substrate, 302 is an active N region doped with impurities and forms a source region, a channel 5 and a drain region, 303 is a gate electrode, and 304 is an active N region doped with impurities.
305 is a source electrode, 305 is a drain electrode, and 306 is a source/gate direct connection portion.

In this conventional example, the step coverage of the source electrode 304 is improved by increasing the thickness of the source electrode 304.

As can be seen from FIG. 8, the step coverage of the source electrode 304 is better than that of the conventional example 1 shown in FIG. However, as a result of the thickening of the source electrode 304 and drain electrode 305, a large step is generated on the GaAs substrate 301, which is one of the causes of interference between different layers in the subsequent upper layer wiring formation process, and the semiconductor Significantly reduces device reliability.

[Problem to be solved by the invention]

In Conventional Example 1, the step coverage of the source electrode is poor due to the step difference in the edge portion of the gate electrode, and the cross-sectional area of the metal wiring through which current flows becomes extremely small, resulting in deterioration of the characteristics of the element when energizing is carried out twice. There was a problem.

In Conventional Example 2, the source electrode and the train electrode become thick, resulting in a large step on the semiconductor substrate, and in the subsequent upper layer wiring formation process, a cross-layer failure occurs, reducing the reliability of the semiconductor device. Significantly reduces sexual performance. There was a problem.

The present invention solves the above-mentioned problems and improves one-step coverage and flatness to prevent wire breakage and deterioration due to current conduction. The object of the present invention is to provide a direct connection structure of two electrodes that are directly connected in a partially overlapping shape.

[Means for Solving the Problems] In order to achieve the above object, a semiconductor device according to the present invention has a shape in which one electrode and another electrode formed on a semiconductor substrate partially overlap. In a direct connection structure of two electrodes that are directly connected, a recessed part that is thinner than the other part is formed in the part of one electrode that is directly connected to the other electrode, and in the recessed part, one electrode and the other electrode are connected directly. Constructed to make direct connection with other electrodes.

[For production]

The present invention forms a recessed portion thinner than the other portions in a portion of one electrode that is directly connected to two other electrodes formed on a semiconductor substrate, and in this recessed portion, one electrode By making a direct connection between the electrode and the other electrode, a two-electrode direct connection structure is realized in which one electrode and the other electrode are directly connected in a partially overlapping shape.

Therefore, the step coverage of the other electrode, which is formed in a shape that partially overlaps with the first electrode, is improved, and the flatness is also improved, so that disconnection does not occur at the direct connection between the two electrodes. disappears. Further, since there is sufficient cross-sectional area of the metal wiring through which current flows, element characteristics do not deteriorate during one energization.

In addition, since no large step difference is generated on the semiconductor substrate, short-circuit failure between different layers does not occur in the process of forming upper layer wiring, and the reliability of the semiconductor device is significantly improved.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 5A shows a circuit element, FIG. 6B shows a pattern layout, and FIG. 6C shows an X-Y cross-sectional view.

In Figure 1, 1 is a GaAs substrate, 2 is an impurity-doped substrate.
3 is a gate electrode, 4 is a source electrode, 5 is a drain electrode, and 6 is a recessed portion 7 which is a source/gate direct connection portion.

In an integrated circuit including a field effect transistor (EFT), as shown in FIG. 1(a), there are many circuit elements that directly connect a gate electrode and a source electrode. In this case, the pattern layout is as shown in Figure 1(b).
A source electrode 4 is configured to overlap the gate electrode 3.

The XY cross-sectional view of the pattern layout shown in FIG. 1(b) is as shown in FIG. 1(c).

As shown in the figure, in this embodiment, a recessed portion 6 which is thinner than other portions is formed in the portion where the gate electrode 3 is directly connected to the source electrode 4.
By making a direct connection between the source electrode 4 and the source electrode 4, a source/gate direct connection portion 7 is formed.

Therefore, the step coverage of the source electrode 4, which is formed in a shape that partially overlaps with the gate electrode 3, is improved, and the flatness is also improved. disappears. In addition, there is sufficient cross-sectional area of the source-gate direct connection portion 7 through which current flows.

Element characteristics do not deteriorate when energized.

Furthermore, since the level difference (Δd) of the source/gate direct connection portion 7 is small, it is possible to prevent short-circuit failure between different layers in the process of forming the upper layer wiring, thereby improving the reliability of the semiconductor device. can.

Next, a method for manufacturing a semiconductor device according to this embodiment will be explained in order of steps using FIGS. 2V to 6.

In each figure, 1(a) is a plan view, and 1(b) is a sectional view.

(Step 1. See Figure 2) A GaAs substrate 101 is doped with impurities (e.g., P, As) of a predetermined conductivity type (e.g., N type) to form an active layer region 102 that forms a source region, a channel, and a drain region. form.

Next, a gate electrode 103 made of W Si or the like is formed on the channel of the active layer region 102 .

(Step 2. See 3rd time) After applying the first resist 104 to the surface, a first opening 105 is formed so that a part of the gate electrode 103 is exposed.

(Step 3. See FIGS. 3 and 4) First resist 04 is used as a mask to remove a portion of the gate electrode 103 by plasma etching to form a recessed portion 106.

An example of etching conditions is shown below.

Gas composition SF6 Gas pressure 0.10 Torr RF power 100W Etching speed ~2000 people/min In addition to the above SF6, CF4+02 is used as the etching gas.
, CF, +CHF], CHF3+0□, etc. can be used.

(Step 4. See FIG. 5) A lift-off spacer 5i02 layer 1°7 is formed on the surface.

Next, after applying a second resist 108, a second opening 109 for forming a source electrode and a third opening 110 for forming a drain electrode are formed.

(Step 5. See FIGS. 5 and 6) Using the second resist 108 as a mask, the second opening 1
The lift-off spacer SiO2 layer 107 exposed in the third opening 110 is removed by etching with diluted hydrofluoric acid or the like.

Then, an ohmic metal such as AuGe/Ni/Au is deposited.

Then, the ohmic metal remaining on the second resist 108 is removed by a lift-off method to form a source electrode 111 and a drain electrode 112.

Through the above process, a source/gate direct connection part 11 is formed in which the gate electrode 103 and the source electrode 111 are directly connected at the recessed part 106 formed in a part of the gate electrode 103.
A GaAs E F T having 3 is completed.

Although this embodiment shows an example in which the present invention is applied to a GaAs E F T, the present invention is not limited to this, and can be applied to other compound semiconductor devices and further to silicon devices.

[Effects of the Invention] In the present invention, a recessed portion having a thickness thinner than the other portion is formed in a portion of one electrode formed on a semiconductor substrate that is directly connected to another electrode, and the recessed portion is thinner than the other portion. By making a direct connection between one electrode and the other electrode, a two-electrode direct connection structure is realized in which one electrode and the other electrode are directly connected in a shape that partially overlaps. There is an effect.

■ The other electrode, which is formed in a shape that partially overlaps the first electrode, has good step coverage and also has good flatness, so there is no possibility of disconnection occurring at the direct connection between the two electrodes. There is no.

■ There is plenty of room in the cross-sectional area of the metal wiring through which the current flows, so 9
Element characteristics do not deteriorate when energized.

(2) Since there are no large steps on the semiconductor substrate, short-circuit failures between different layers do not occur in the process of forming upper layer wiring, and the reliability of the semiconductor device is significantly improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. Sections 2 to 6 show each step of the method for manufacturing a semiconductor device according to the present invention. FIG. 7 shows Conventional Example 1. FIG. 8 shows Conventional Example 2. In FIG. 1, 1+GaAs substrate 2: active layer region 3: gate electrode 4: source electrode 5: train electrode 6-recess portion 7, two source/gate direct connection portions, 4σ discharge/1-1-on 1. It's a lot of $1121 (C1) It's a lot (b) It's a lot of money 211$ 6 Figure

Claims (1)

[Claims] In a two-electrode direct connection structure in which one electrode formed on a semiconductor substrate and another electrode are directly connected in a partially overlapping shape, the other electrode of the one electrode 1. A semiconductor device comprising: forming a recess portion thinner in thickness than other portions in a portion directly connected to the semiconductor device; and directly connecting one electrode to another electrode at the recess portion.