JPH03169026A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance reliability by a method wherein a film thickness of an interconnection whose resistance needs to be low from a viewpoint of a high-frequency operation is made thick and a film thickness of one part of a redundant interconnection from a viewpoint of a route of an electric current is made thin. CONSTITUTION:One part of an N<+> diffusion layer 6 and one part of a P-type diffusion layer 3 as a diffusion layer of a back gate are exposed from an opening part 8; a platinum silicide film 9 is formed in the opening part 8; a first photoresist 12 is then patterned; after that, a first source electrode 13 and a source interconnection 14 are formed. Then, the first photoresist 12 is removed; a second photoresist 17 is patterned; a source electrode 18 is formed. A film thickness of gold at the source electrode 18 is made partially thick; gold is not deposited additionally on the source interconnection 14. This is because the source interconnection 14 in this part is a redundant interconnection which is intended to prevent impurities from creeping to a periphery of a gate electrode part and to fix a potential of a drain region directly under a gate oxide film 4 and because no problem is caused at a high-frequency operation even when its resistance is high. Thereby, reliability is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a source electrode/wiring and a gate lead-out wiring of a vertical MOS/FET.

[Conventional technology]

The source electrode and source wiring of conventional vertical MOS-FETs mainly have one of the following two types of structures.

(1) A structure in which almost the entire surface above the active region of the semiconductor element, including above the gate electrode, is covered with AI2 or the like, and this is used as the source electrode and source wiring 21 (FIG. 3).

(2) The source electrode and source wiring do not overlap on the entire surface above the gate electrode, but some of them overlap the gate electrode with an insulating film in between, or are placed very close to the gate electrode. In addition, the thickness of the source wiring is equivalent to the thickness of the source electrode (Fig. 4).

[Problem to be solved by the invention]

These conventional vertical MOS-FETs each have the following problems.

(1) The structure in which the source electrode and source wiring 21 (FIG. 3) cover the entire surface of the gate electrode reduces the capacitance between the source electrode and source wiring 21 and the gate electrode 5, that is, F
The input capacity of ET is large.

Therefore, when the FET operates, the amount of gate charge is large and the drive loss is also large, so it cannot be used as a high frequency and high output device. Specifically, this vertical MOS-F
It is several tens of times that an output of about 100W can be obtained with ET.
It is limited to frequencies up to MHz.

(2) As shown in FIG. 4, the structure in which the entire upper surface of the gate electrode is not covered with the source electrode 22 or the source wiring 23, and the thickness of the source electrode 22 and the source wiring 23 are the same, is 100M because the input capacitance between sources is small
Although it is possible to configure a semiconductor device with an output of IOOW or higher even at a high frequency of Hz or higher, it is necessary to reduce the gate resistance and source resistance in order to create a high-frequency semiconductor device. 5 has a thickness of about 1 μm, and the thickness of the source electrode 22 and source wiring 23 is 1.5 μm.
It is thicker than μm.

Therefore, the source wiring located on the PSG film (phosphorus glass film) 7, which is partially raised due to the presence of the source electrode, becomes very high from the semiconductor surface, and is not coated like the polyimide film 20. If a protective film formed by this method is used in this device, a part of the source wiring 24 will be formed that is not covered by the polyimide film, which will cause reliability problems such as moisture resistance and impurity penetration into the element region. be.

When a PSG film (not shown) is used as a protective film and Aj2 is used as a source wiring, the molar concentration of phosphorus in the PSG film must be kept low to prevent corrosion of Au. The PSG film is prone to cracking at steep step portions of the source wiring, and this case also poses reliability problems.

In addition, in order to improve the reliability of the source electrode and the source wiring, these may be formed by A1 <Au plating, but the thickness of the gate oxide film 4 is 150 nm, and the gate electrode 5
The thickness of the PSG film 7 is 1.0 μm, and the thickness of the PSG film 7 is 0.0 μm. 7μ
m, the thickness of the source electrode 22 and source wiring 23 is 1.5
If the thickness is 1.5 μm, the thickness of the photoresist serving as a mask must be at least 1.5 μm above the gate electrode when partially plating Au, so the thickness above the opening of the N+ diffusion layer 6 is 3.65 μm. Therefore, a special manufacturing method such as a multilayer resist method must be used, which creates restrictions from a manufacturing standpoint.

The source wiring 23 shown in FIG. 4 fixes the potential of the drain region in the vicinity of the gate electrode 5 directly under the gate oxide film 4 and prevents alkali ions (positive charges) from entering around the gate electrode 50. It is set up for the purpose of (When the enhancement type MOS-FET operates, the gate electrode 5
is higher than the potential of the source wiring 23).

Therefore, in order to solve the problem that a part of the source wiring is not covered with the polyimide film 20 due to the steep step difference, the source wiring 23 should be separated from the gate electrode 5 so as not to rest on the raised part of the PSG film 7. Separating them is counterproductive and meaningless in terms of characteristics and reliability (Figure 5)
.

[Means to solve the problem]

The vertical MOS/FET of the present invention, which has a drain electrode on the back surface of the chip, a gate electrode with a thickness of 800 nm or more, and an insulating film covering the gate electrode, is partially The thickness of the source electrode, source wiring, and gate lead-out wiring located on the raised part of the insulating film that is raised on the surface is 700 nm or less, and the thickness of the source electrode, source wiring, and gate formed on the other part is The thickness of the lead wiring is partially 1 μm or more.

〔Example〕

Next, the present invention will be explained, including a manufacturing method for realizing the present invention.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor substrate showing the structure of the source electrode and source wiring of the present invention and the main manufacturing steps thereof.

FIG. 1(a) shows a vertical MOS-FET in the middle of the manufacturing process, where a part of the N+ diffusion layer 6, which will become the source region, and a part of the P-type diffusion layer 3, which will be the back gate diffusion layer, are opened. This is exposed by section 8.

The gate oxide film 4 has a thickness of 0.15 μm, and the gate electrode 5 is made of low resistance molybdenum or tungsten to enable high frequency operation, and has a thickness of 1.0 μm. Further, the thickness of the PSG film 7 covering the electrode 5 is 0.7 μm.

FIG. 1(b) shows a platinum silicide film 9 in the opening so that each diffusion layer and the metal of the source electrode are in ohmic contact.
After forming titanium to a thickness of about 150 nm and platinum to a thickness of 30 nm,
The thickness is about 2.6 μm, and then the thickness is 2.6 μm.
After patterning a certain single-layer first photoresist 12, gold is deposited to a thickness of 0.5 μm by electrolytic plating using the titanium and platinum laminated film 11 as a conductive bus, thereby forming a first source electrode 13 and a source wiring l4. has just been formed.

Gold is deposited closest to the upper surface of the first photoresist 12 at a position above the gate electrode 5, but even at this position, the upper surface of the deposited film and the first photoresist 12
Since the height difference from the top surface is still 0.25 μm, problems such as plating pattern collapse will not occur during gold plating.

FIG. 1(C) shows that the first photoresist is peeled off and the second photoresist is removed.
After patterning the photoresist 17, gold was deposited to a thickness of 1.0 μm by electrolytic plating to form the source electrode 18.

The second gold plating makes the gold film thicker in only the source electrode part, and the reason why no additional gold is deposited on the source wiring in the part shown in this figure is because the source wiring in this part is not attached to the area around the gate electrode, as mentioned above. This is because this is a redundant wiring for the purpose of preventing impurities from entering the gate oxide film 4 and fixing the potential of the drain region directly under the gate oxide film 4, and even if it has a high resistance, it does not pose a problem in high frequency operation.

FIG. 1(d) shows that after removing the second photoresist and etching the portion of the titanium and platinum laminated film 11 that is not under either the first source electrode l3 or the source wiring 14, A polyimide film 20 as a protective film on the surface of a semiconductor chip has been formed by a coating method.

In the structure of the source electrode and source wiring of the present invention, surface irregularities are suppressed compared to the conventional example, so that the polyimide film 20 can sufficiently cover the entire chip surface. Moreover, even if a low concentration PSG film is used as a protective film, the occurrence of cracks can be suppressed. FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor substrate showing the structure of a gate lead-out wiring according to the present invention and its main manufacturing steps.

FIG. 2(a) is a cross section of the semiconductor substrate in the direction perpendicular to the paper (gate width direction) at the position of line A-A' in FIG. 1(b), showing the PSG film covering the gate electrode 5. After forming a gate lead-out opening 10 in 7, a first gate lead-out wiring 16 was formed by gold plating at the same time as forming the first source electrode and source wiring in FIG. 1(b). . Therefore, the film thickness of this wiring is also 0.5 μm. For reference, in FIG. 2, the presence of the first source electrode or source wiring 15 located at the back or front of the page is indicated by broken lines.

In FIG. 2(b), the second gate lead wiring 19 is formed by gold plating at the same time as the second source electrode in FIG. 1(C) is formed.

Before coating the second photoresist 17, the opening on the source diffusion layer, which is the most concave part adjacent to the gate electrode, is filled with the first source electrode, so the gate electrode The thickness of the second photoresist 17 on the upper PSG film 7 can be approximately 1.0 μm even by using a single layer resist method.

Therefore, if the second gate lead wiring 19 is formed on the PSG film in the protruded portion due to the presence of the gate electrode, even if the thickness is 1.0 μm, the second photoresist 17
Since the height difference between the upper surface and the upper surface of the second gate lead-out wiring l9 can be secured by 0.2 μm, the plating pattern does not collapse during gold plating.

FIG. 2(c) shows a polyimide film 20 formed by a coating method as a protective film for a semiconductor chip. In the gate lead wiring structure of the present invention, the unevenness on the semiconductor chip surface is sufficiently reduced compared to the conventional technology, so that the polyimide film 20 can sufficiently cover the entire chip surface.

C. Effects of the Invention] As explained above, the present invention can be applied to a part of the source electrode, a part of the source wiring (not shown), a gate electrode, and a gate lead-out wiring, which need to have low resistance for high-frequency operation. The thickness of the source wiring is increased, and the thickness of a part of the source wiring and a part of the gate lead-out wiring, which have the purpose of fixing the potential of the drain region and are redundant from the viewpoint of the current path, is made thinner. As a result, the structure suppresses unevenness on the surface of the semiconductor chip without deteriorating the high frequency characteristics of the semiconductor device, which has the effect of improving the coverage of the protective film on the chip surface and, in turn, improving the reliability of the semiconductor device. .

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views of a semiconductor substrate in the gate length direction showing an embodiment of the present invention and its main manufacturing process, and FIGS. 2(a) to (c) are cross-sectional views of other embodiments of the present invention. A cross-sectional view of a semiconductor substrate in the gate width direction showing an example and its main manufacturing process,
3, 4, and 5 are cross-sectional views in the gate length direction of a semiconductor substrate of a conventional embodiment. 1...N+ type silicon substrate, 2...N
Type 1 epitaxial layer, 3...P type diffusion layer, 4
...Gate oxide film, 5...Gate electrode, 6...N+ type diffusion layer, 7...PSG
Membrane, 8... Opening part, 9... Platinum silicide film, 10... Opening part for gate extraction, 11
...Laminated film of titanium and platinum, 12...
First photoresist, 13...first source electrode, 14...source wiring, l5...
First source electrode or source wiring, 16...
First gate lead wiring, l7... second photoresist, 18... second source electrode, 19...
...Second gate lead wiring, 20...
Polyimide film, 21...source electrode and source wiring, 22...source tL23...source wiring, 24...one of the source wirings not covered with the polyimide film Department.

Claims (2)

[Claims] (1) In a vertical MOS/FET that has a drain electrode on the back surface of the chip and an insulating film covering the gate electrode, the insulating film is partially raised due to the presence of the gate electrode. The thickness of the source electrode, source wiring, and gate lead-out wiring located on the raised portion is thin, and the thickness of the source electrode, source wire, and gate lead-out wiring formed in other parts is partially thick. A semiconductor device characterized by (2) In a vertical MOS/FET that has a drain electrode on the back surface of the chip, a gate electrode with a thickness of 800 nm or more, and an insulating film covering the gate electrode, due to the presence of the gate electrode. The thickness of the source electrode, source wiring, and gate lead wiring located on the partially raised part of the insulating film is 700 nm or less, and the thickness of the source electrode and source wiring formed in the other part is 700 nm or less. and a semiconductor device characterized in that the thickness of the gate lead-out wiring is partially 1 μm or more.