JPH04134831A - Manufacturing method of MOS type semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to MOS type semiconductor devices, particularly gate-drain overlamp type MOS type semiconductor devices. ! It is related to the method of sending.

(Prior Art) FIG. 2 shows a conventional method for manufacturing a gate-drain overlap type MOS semiconductor device disclosed in IEDM87 P38-41. a) As shown in Figure 4, a gate oxide film 2 as thin as about 150 layers is formed on a P-type silicon substrate 1. Next, P-type impurities are implanted into the entire surface of the substrate 1 through the gate oxide film 2 for the purpose of threshold control, punch-through stop, or both. Specifically, ion species 1184.
Injection amount 1. Boron is implanted under the conditions of 2 E 12 ions/c4 and implant energy of 30 KeV. Thereafter, a first film is applied to the entire surface of the gate oxide film 2. A second polysilicon film 3.4 is grown. At this time, polysilicon film 3
, 4, a natural oxide film 5 of 5 to 10 layers is grown. Thereafter, an oxide film is grown on the entire surface by the CVD method, and then a pattern 6 of the CVD oxide film is formed on the second polysilicon film 4 by photolithography and etching.

Next, the second polysilicon film 4 is isotropically etched using the CVD oxide film pattern 6 as a mask (see FIG. 2).
Proceed as shown. At this time, etching is performed using the natural oxide film 5 as an etching stopper. After this, CVD
Using the oxide film pattern 6 as a mask, the ion implanter implants ion species fflp* implantation amount 5 E 12 ions.
An n-diffusion layer 7 is formed in the substrate 1 by implanting phosphorus into the substrate 1 under the conditions of /cd and an implant energy of 13QKeV.

After that, an oxide film is grown again on the entire surface using the CVD method.
By etching this using an anisotropic etching method, sidewall spacers 8 are formed on the side walls of the CVD oxide film pattern 6 and the remaining second polysilicon film 4, as shown in FIG. 2(c). Thereafter, the first polysilicon film 3 is etched using the sidewall spacer 8 and the CVD oxide film pattern 6 as a mask, thereby forming the gate electrode 3a.

Thereafter, the side edges of the gate electrode 3a are thermally oxidized as shown in FIG.
After converting the oxide film 9 into an oxide film 9 as shown in FIG. SAs*. By implanting arsenic into the substrate 1 at an implantation dose of 4 E 15 ions/cd and an implantation energy of 40 KeV, an n' diffusion layer 10 is formed in the substrate 1 .

With the above steps, a gate-drain overlamp type MOS type semiconductor element (MOS type transistor) is completed.

(Problem to be Solved by the Invention) However, in the conventional manufacturing method as described above, P-type impurity implantation is performed over the entire surface of the substrate 1 for threshold control, punch-through stop, or both. Therefore, the source/drain n-diffusion N1
When forming a (low-concentration impurity diffusion layer), it is necessary to increase the amount of n-type impurity implanted to remove the influence of the P-type impurity, and as a result, defects occur in the diffusion layer and leakage current In addition, if the entire surface of the substrate 1 is highly doped by implanting P-type impurities, the source/drain diffusion layer (n-diffusion layer 7 and n°
Since the junction capacitance between the diffusion layer 10) and the substrate 1 increases, there is also a problem that the operating speed of the device becomes slow.

Furthermore, the conventional manufacturing method described above is applicable to the first and second polysilicon WIj! 3. It is necessary to precisely grow a very thin natural oxide film 5 of 5 to 10 layers within 4 hours, and furthermore, the natural oxide film 5 is used as an etching stopper for the second etching process.
When etching a polysilicon film 4, for example, if the second polysilicon film 4 is etched by 1000 etches and the natural oxide film 5 is etched by 10 etches, a high selectivity of 100 or more is required, which is technically difficult. The problem was that it was difficult.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a gate-drain overlamp type MOS semiconductor device that can eliminate the above-mentioned conventional problems.

(Means for Solving the Problems) The present invention provides a gate-drain overlap type MO
In a method for manufacturing an S-type semiconductor device, impurity implantation for threshold control, punch-through stop, or both is performed only in the channel region of the substrate, and conductive etching is performed using a natural oxide film as an etching stopper. This makes it possible to form elements without a film etching process. Specifically, the manufacturing method is as follows.

First, a gate oxide film, a conductive film, and an oxide film are sequentially formed on a semiconductor substrate, and an opening is formed in the oxide film corresponding to a chaffle region of the substrate. Impurities for threshold control, punch-through stop, or both are implanted into the channel region of the substrate through the opening. Thereafter, a conductive film pattern is formed within the opening by forming a conductive film on the entire surface and etching back. Thereafter, after removing the oxide film, impurities are implanted into the substrate using the conductive film pattern as a mask to form low concentration impurity diffusion layers for sources and drains in the substrate.

Thereafter, a sidewall spacer of an insulating film is formed on a sidewall of the conductive film pattern. Using the sidewall spacer and the conductive film pattern as a mask, the conductive film on the substrate is etched to form a gate electrode. Thereafter, impurities are implanted into the substrate using the sidewall spacers and the conductive film pattern as a mask to form high concentration impurity diffusion layers of source and drain in the substrate.

(Function) In the present invention described above, impurity implantation for threshold voltage control, punch-through stop, or both is selectively performed only in the channel region of the substrate. Therefore, this impurity implantation does not affect the subsequent formation of low concentration impurity diffusion layers for the source and drain, and the amount of impurity implantation for forming the diffusion layers can be frozen. Furthermore, if only the channel region is made highly doped by the impurity implantation described above, most of the source/drain diffusion layer will be in contact with the low concentration region 2 of the substrate, so the junction capacitance between the source/drain diffusion layer and the substrate will decrease. .

In addition, in the present invention, a conductive film pattern is buried in the opening of the oxide film by forming a conductive film on the entire surface and etching back, thereby achieving conductivity similar to the conventional etching process using a natural oxide film as an etching stopper. Inverted T of sexual membrane
1(d) and (e), and the gate/drain overflow can be achieved without using the conventional etching process of a conductive film using a native oxide film as an etching stopper. It becomes possible to form a wrap-type element.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In one embodiment, first, as shown in FIG. 1(a), 15
A gate oxide film 22 is formed by about 100 g of growth.

Next, a first polysilicon film 23 of about 500 layers is grown on the gate oxidation film 22 by LPCVD or the like, and a silicon oxide film 24 of about 300 layers is further grown thereon by CVD.

Next, an opening 25 is formed in the silicon oxide film 24 using a photolithography/etching process, corresponding to the channel region of the substrate 21, as shown in FIG. 1(b). and,
Through its opening 25, a
Alternatively, impurity ions are implanted into the chaffle region of the substrate 21 for punch-through stop or both.

Here, for threshold control, boron ions are implanted under the conditions of, for example, an ion species of +173+ and a 50XeV dose of 1.2E12ions/CI1+. At this time, if it is necessary to implant boron ions for punch-through stop, for example, ion type B, energy 80 KeV, dose I
Perform injections at E 12fons/aA. As a result of this ion implantation, a P-type high concentration region 26 is formed in the channel region of the substrate 21.

Next, Silicon Oxide II! As shown in FIG. 1(c), a second polysilicon film 27 of approximately 3,500 layers is grown on the entire surface of the second polysilicon film 24 using the LPCVD method or the like, and the opening 25 is filled with the second polysilicon film 27. .

Thereafter, by etching back the entire surface of the second polysilicon film 27 until the surface of the silicon oxide film 24 is exposed, the second polysilicon film 27 is changed into a polysilicon film as shown in FIG. Opening 2 as pattern 27a
Leave only within 5.

Thereafter, the silicon oxide film 24 is removed using a hydrofluoric acid aqueous solution or the like, and then the first polysilicon film 23 and the polysilicon film pattern 27a are doped with phosphorus using pact as a diffusion source to make them conductive.

After that, using the polysilicon film pattern 27a as a mask, phosphorus is removed as an ion species. lp+, energy 80KeV
By implanting into the substrate 21 using an ion implanter at a dose of IE 13ions/c-, source/drain n-diffusion layers 28 are formed in the substrate 21 as shown in FIG. 1(e). Form.

Next, a PSG film is deposited on the entire surface using the CVD method and etched using an anisotropic etching method to form a polysilicon film pattern 27a as shown in Fig. 1.
A side wall spacer 29 having a width of about 0.15 nm is formed on the side wall of the substrate.

Then, by etching the first polysilicon film 23 using the sidewall spacer 29 and the polysilicon film pattern 27a as a mask, a gate electrode 23a is formed as shown in FIG. The film pattern 27a is slightly etched.The remaining polysilicon film pattern 27a becomes a part of the gate electrode.

Finally, using the sidewall spacer 29 and the polysilicon film pattern 27a as a mask, arsenic is added to the ion species 'T'.
By implanting ions into the substrate 21 under the conditions of ``SAS'', energy 40KeV, and dose 4E15ions/c4, the ions shown in FIG.
As shown in (to), the source/drain n″″ diffusion layer 3
form 0.

With the above steps, a gate-drain overlap type MOS semiconductor device according to an embodiment of the present invention is completed.

Although the above embodiment is a case of an N-channel MOS type semiconductor element, a P-channel MOS type semiconductor element can also be manufactured in exactly the same manner by changing the conductivity types of the substrate and impurities.

(Effects of the Invention) As described in detail above, according to the manufacturing method of the present invention, impurity implantation for threshold control, punch-through stop, or both is selected only in the channel region of the substrate. Since the impurity implantation is performed in a consistent manner, this impurity implantation does not affect the subsequent formation of the source/drain low concentration impurity diffusion layer, and the amount of impurity implantation for forming the diffusion layer can be reduced. As a result, the occurrence of defects and leakage current in the diffusion layer can be prevented.

Furthermore, if only the channel region is highly doped by the impurity implantation described above, most of the source/drain diffusion layer will be in contact with the low concentration portion of the substrate, so the junction capacitance between the source/drain diffusion layer and the substrate can be reduced. It is possible to increase the operating speed of the device.

Furthermore, according to the manufacturing method of the present invention, a conductive film pattern is buried in the opening of the oxide film by forming a conductive film on the entire surface and etching back, thereby eliminating the conventional etching process using a natural oxide film as an etching stopper. A conductive film structure similar to the above is obtained, making it possible to form a gate-drain overlamp type device with high yield through a simple and highly reliable process without the need for conventional technically difficult processes.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a MOS type semiconductor device according to the present invention, and FIG. 2 is a process cross-sectional view showing a conventional manufacturing method. 21... P-type silicon substrate, 22... Gate oxide film, 23... First polysilicon film, 23a... Gate electrode, 24... Silicon oxide film, 25... Opening part, 26... P-type preconcentration region, 27... Second polysilicon film, 27a... Polysilicon film pattern, 28
...n-diffusion layer, 29...side wall spacer 30...n-diffusion layer. Patent Applicant: Oki Electric Industry Co., Ltd. Agent: Patent Attorney: Hiromoto Kikuchi Embodiment of the Invention Figure 2? σ One embodiment of the present invention Fig. 1

Claims (1)

[Claims] A step of sequentially forming a gate oxide film, a conductive film, and an oxide film on a semiconductor substrate, forming an opening in the oxide film corresponding to a channel region of the substrate, and passing the opening through the opening. A step of implanting impurities into the channel region of the substrate for threshold control, punch-through stop, or both, and then forming a conductive film on the entire surface and etching back to make the opening conductive. After that, after removing the oxide film, implanting impurities into the substrate using the conductive film pattern as a mask to form a source/drain low concentration impurity diffusion layer in the substrate; Thereafter, a step of forming a sidewall spacer of an insulating film on the sidewall of the conductive film pattern, and etching the conductive film on the substrate using the sidewall spacer and the conductive film pattern as a mask to form a gate electrode. and then implanting impurities into the substrate using the sidewall spacers and the conductive film pattern as a mask to form high concentration impurity diffusion layers for sources and drains in the substrate. A method for manufacturing a drain overlap type MOS type semiconductor device.