JPS6410952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device.

One of the basic characteristics of an insulated gate field effect semiconductor device is the dependence of the threshold voltage on the substrate bias, and a channel doping method is a method for reducing the dependence on the substrate bias. The channel doping method is as shown in Figure 1.
The substrate bias dependence is improved using
In this method, a region having a higher concentration than the substrate, that is, a channel doped region 9, having the same conductivity type as the substrate is provided in order to prevent punch-through between the substrate and the drain 3 and to obtain the required threshold voltage. However, if the substrate concentration is too low, punch-through between the source 2 and drain 3 occurs at the interface between the channel region 9 and the substrate region 1, which is a drawback.

SUMMARY OF THE INVENTION The object of the present invention is to provide a new insulated gate field effect semiconductor device that overcomes the above-mentioned drawbacks.

A feature of the present invention is that, in order to prevent the punch-through described above, a high concentration impurity region having the same conductivity type as the substrate surrounding at least one of the source and drain regions is provided, and this high concentration impurity region is Therefore, in order to connect the cut channel to the source or drain, an opposite conductivity type region is provided along one main surface of the substrate extending from the source or drain to the channel portion, that is, the channel doped region. Further, this region of opposite conductivity type has a higher concentration than the region of one conductivity type surrounding the source/drain, and the depth of this region of opposite conductivity type is shallower than that of the channel doped region.

Next, embodiments of the present invention will be described based on the drawings.

In the following embodiments, N-channel MOS
Although described for transistors, other types of transistors are similarly described.

FIGS. 2a to 2g are cross-sectional views in the middle of explaining the first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 2a, an oxide film 11 is formed on the surface of the high resistivity P-type substrate 1 by vapor phase growth and photolithography, leaving only the regions that will become the source and drain regions of transistors in the future. A field oxide film 5 is grown by oxidizing in an oxygen atmosphere, and then a region where P ⁺ is diffused (in this case, as shown in FIG. 2b) is formed.
After removing the nitride film and oxide film on the drain region (only the drain region) and diffusing or ion-implanting P type impurities, heat treatment is performed to form the P ⁺ region 10. Next, as shown in FIG. 2c, the source side The nitride film and oxide film are removed, and a source 2 and drain 3 are formed which are shallower than the P ⁺ region 10, which is an N-type high concentration impurity region.
Next, the gate region 4 is formed by photolithography and oxidation.
2d, and then, as shown in FIG. 2e, P-type ions, such as boron, are implanted through the gate oxide film to dope the channel surface with P-type at a higher concentration than the substrate. A region 9 is formed, and then the channel region is covered with a ^photoresist 14 as shown in FIG ^. Invert the surface of the region to N ⁺ region 13. At this time, N ⁺ area 1
It is necessary to adjust the energy so that the depth of channel doped region 3 is not greater than the depth of channel doped region 10. The reason for this is that if the N ⁺ region 13 and the substrate 1 directly collide, the punch-through of the source 2 and drain 3 will be determined by the concentration of the substrate. Second
FIG. g shows a cross-sectional view of a completed semiconductor device after completing the steps of activating the implanted ions, opening contact holes, and forming metal interconnections 6, 7, and 8, following the above steps.

The first embodiment described above only applies to the drain side.
We explained how to create a P ⁺ area, but next,
A manufacturing method in which P ⁺ regions are formed on the source/drain side and is different from the first embodiment will be described.

FIGS. 3A to 3G are cross-sectional views at intermediate steps to explain the second embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 3a, an oxide film 22 and a nitride film 2 are formed on the surface of a high-resistivity semiconductor substrate 21 in which regions that will become sources and drains in the future are opened.
A double layer of No. 3 was formed by an oxidation method, a vapor phase growth method, a photoetching method, etc., and then as shown in FIG. 3b,
P-type ions, such as boron, are diffused or ion-implanted through the above-mentioned opening and heat-treated to form the P ⁺ region 24.
make. Next, the oxide film 22 is side-etched using a solution that etches only the oxide film 22 without etching the nitride film 23, such as hydrofluoric acid, so that the opening of the oxide film is made larger than the P ⁺ region 24. This situation is shown in Figure 3c. Next, as shown in FIG. 3d, the nitride film 23 is removed using phosphoric acid or the like, and an N ⁺ region 25 with a higher concentration than the P ⁺ region 24 and shallower than the P ⁺ region is formed in the opening by ion implantation. establish. Next, an oxide film is formed on the surface by an oxidation method, and then an opening for forming a high concentration source/drain region is formed by a photolithography method, and the P ⁺ region 24 is formed as shown in FIG. 3e. A source 26 and a drain 27 in a highly doped N ⁺⁺ region having a shallower depth than the above are formed by a diffusion method and heat treatment. Next, as shown in FIG. 3f, a gate oxide film 28 is formed by photolithographic oxidation, and as shown in FIG. do. Also in this embodiment, the N ⁺ region 25 is the channel doped region 29.
must be shallower than

In the second embodiment described above ^, the source and drain are formed in the N ⁺⁺ regions 26 and 27, but as in the third embodiment shown in FIG. It can also be used as a drain. It goes without saying that the P ⁺ region 34 is used as a channel stopper.

From the above description, it can be seen that by using the present invention, a high-performance insulated gate field effect semiconductor device with less dependence on substrate bias can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional insulated gate field effect semiconductor device. FIGS. 2a to 2g are cross-sectional views showing the manufacturing process of the first embodiment of the present invention in the order of steps. FIGS. 3a to 3g are cross-sectional views showing the manufacturing process of the second embodiment of the present invention in the order of steps. FIG. 4 is a sectional view showing a third embodiment of the present invention. In the figure, 1, 21, 31...P-type high resistivity substrate, 2, 26...N ⁺⁺ lease area, 3, 2
7...N ⁺⁺ drain region, 4, 28... gate oxide film, 5... field oxide film, 6... source electrode, 7... drain electrode, 8... gate electrode,
9,29,39...P-type channel doped region,
10, 24, 34...P ⁺ high concentration area, 11, 2
2...Oxide film, 12,23...Nitride film, 13,2
5, 35...N ⁺ area, 14...photoresist.

Claims (1)

[Claims] 1. A source region and a drain region of opposite conductivity type are provided on one main surface of a semiconductor substrate of one conductivity type, and a gate electrode is provided on the surface of the channel region between the source and drain regions with a gate insulating film interposed therebetween. In an insulated gate field effect semiconductor device including a channel doped region of one conductivity type with higher concentration than the semiconductor substrate, at least one of the source region and the drain region has one conductivity type with higher concentration than the channel doped region. is provided in the high concentration region of the one conductivity type, and is higher in concentration than the one conductivity type high concentration region so as to cover one main surface of the one conductivity type high concentration region existing between the one region and the channel doped region. An insulated gate type field effect semiconductor device, characterized in that an opposite conductivity type region is provided with a higher concentration and shallower than the channel doped region, and a gate electrode is provided on the surface of the shallow opposite conductivity type region with a gate insulating film interposed therebetween.