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JPH04132256A - Manufacturing method of semiconductor laminated substrate - Google Patents

Manufacturing method of semiconductor laminated substrate

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Publication number
JPH04132256A
JPH04132256A JP25345390A JP25345390A JPH04132256A JP H04132256 A JPH04132256 A JP H04132256A JP 25345390 A JP25345390 A JP 25345390A JP 25345390 A JP25345390 A JP 25345390A JP H04132256 A JPH04132256 A JP H04132256A
Authority
JP
Japan
Prior art keywords
main surface
silicon substrate
substrate
film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25345390A
Other languages
Japanese (ja)
Other versions
JP2764466B2 (en
Inventor
Kohei Eguchi
江口 公平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP25345390A priority Critical patent/JP2764466B2/en
Priority to US07/763,302 priority patent/US5238865A/en
Publication of JPH04132256A publication Critical patent/JPH04132256A/en
Application granted granted Critical
Publication of JP2764466B2 publication Critical patent/JP2764466B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To make it possible to sufficiently bond the main surface of laminated semiconductor substrates to one another and to control a second semiconductor substrate that becomes an active domain to have a constant thickness by preparing sunken sections on the main surface of the second semiconductor substrate corresponding to the protrusions that are present on the main surface of a first semiconductor substrate. CONSTITUTION:SiO2 film 2 is prepared on the main surface of silicon substrate 1, followed by selectively etching the SiO2 film 2 taking a photoresist pattern as mask to prepare a plurality of protrudent sections 6 relative to the SiO2 film 2. On the other hand, the main surface of a second silicon substrate 3 is selectively etched to prepare sunken sections 7 thereon. Here, positions of sunken sections 7 are corresponding to positions of protrudent sections 6 prepare on the SiO2 film 2. The main surface of a first silicon substrate 1 and the main surface of the second silicon substrate 3 are put together and heated to bond them together, further followed by grinding the back surface of the second silicon substrate 3 until the protrudent sections 6 of Silicon O2 film 2 are partly exposed to prepare silicon film 3 as an active domain on the SiO2 film 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体積層基板の製造方法に関し、特に、貼り
合わせ法を用いたSol基板の製造方法に適用して好適
なものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor multilayer substrate, and is particularly suitable for application to a method for manufacturing a Sol substrate using a bonding method.

〔従来の技術〕゛ 貼り合わせ法を用いたS OT (Silicon O
n In5ulator)基板の製造方法は、従来、次
のようにして行われていた。
[Conventional technology] SOT (Silicon O) using the bonding method
Conventionally, a method for manufacturing a substrate (In5lator) has been carried out as follows.

まず、第2図(a)に示すように、第1のシリコン基板
lの主面に熱酸化法によりSing膜2を形成する。
First, as shown in FIG. 2(a), a Sing film 2 is formed on the main surface of a first silicon substrate l by thermal oxidation.

次に、第2図(b)に示すように、この第1のシリコン
基板lの主面に第2のシリコン基板3の主面を貼り合わ
せ、熱処理することによりシリコン基板同士を互いに接
着する。
Next, as shown in FIG. 2(b), the main surface of the second silicon substrate 3 is bonded to the main surface of the first silicon substrate 1, and the silicon substrates are bonded to each other by heat treatment.

次に、第2図(C)に示すように、第2のシリコン基板
3をその裏面側から研磨していき、Sing膜2上に能
動領域として薄いシリコン膜3を残して、SO夏基板を
形成する。
Next, as shown in FIG. 2(C), the second silicon substrate 3 is polished from the back side, leaving a thin silicon film 3 as an active region on the Sing film 2, and forming an SO summer substrate. Form.

しかしながら、この方法では、最後の研磨工程において
研磨量をモニターすることが難しく、このため、残存さ
せるシリコン膜3の膜厚を精密にコントロールすること
が困難であった。
However, with this method, it is difficult to monitor the amount of polishing in the final polishing step, and therefore it is difficult to accurately control the thickness of the silicon film 3 to remain.

この問題を解決するために、次のような方法がとられて
いる。
In order to solve this problem, the following methods have been taken.

まず、第3図(a)に示すように、第1のシリコン基板
1の主面全面に熱酸化法によりSiO□Ml!2を形成
する。一方、第2のシリコン基板3の主面の一部を熱酸
化して、局部的にSiO□4を形成する。
First, as shown in FIG. 3(a), SiO□Ml! is applied to the entire main surface of the first silicon substrate 1 by thermal oxidation. form 2. On the other hand, a part of the main surface of the second silicon substrate 3 is thermally oxidized to locally form SiO□4.

このSto、 4の表面は、シリコン基板3の主面の表
面から凸状に突出しており、また、SiO□4とシリコ
ン基板3との境界面は、シリコン基vi3の主面の表面
よりも深いところにある。
The surface of this Sto, 4 protrudes convexly from the surface of the main surface of the silicon substrate 3, and the interface between SiO□4 and the silicon substrate 3 is deeper than the surface of the main surface of the silicon substrate vi3. It's there.

次いで、第3図(b)に示すように、第1のシリコン基
板lと第2のシリコン基板3との主面同士を互いに貼り
合わせ、熱処理により接着する。
Next, as shown in FIG. 3(b), the main surfaces of the first silicon substrate 1 and the second silicon substrate 3 are bonded to each other and bonded by heat treatment.

次いで、第3図(C)に示すように、第2のシリコン基
板3の裏面側から研磨する。この時、研磨速度はシリコ
ンよりもSiO2の方がかなり小さいため、シリコン基
板3に形成した5iOz4がストッパーとして働き、S
iO□膜2上に能動領域として残存させるシリコン膜3
の膜厚を一定にすることができる。
Next, as shown in FIG. 3(C), the second silicon substrate 3 is polished from the back side. At this time, since the polishing rate of SiO2 is much lower than that of silicon, the 5iOz4 formed on the silicon substrate 3 acts as a stopper, and the S
Silicon film 3 left on the iO□ film 2 as an active region
The film thickness can be kept constant.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、第3図に示した方法では、第2のシリコ
ン基板3の主面上にSiO□4の突起が存在するため、
第3図(b)に示すように基板同士を貼り合わせた時に
、突起の周囲に空隙が生じて接着性が悪くなったり、突
起の周辺のシリコン基板3の主面が平面を保てずに撓ん
でシリコンの結晶性が悪くなる等の問題があった。
However, in the method shown in FIG. 3, since there are protrusions of SiO□4 on the main surface of the second silicon substrate 3,
As shown in FIG. 3(b), when the substrates are bonded together, voids may occur around the protrusions, resulting in poor adhesion, or the main surface of the silicon substrate 3 around the protrusions may not be able to maintain a flat surface. There were problems such as deterioration of silicon crystallinity due to bending.

本発明は上述の問題点に鑑みてなされたものであって、
能動領域となるシリコン膜の膜厚を一定にコントロール
することができ、且つ、結晶性や接着性を損なうことな
くSOI基板を製造することができる方法を提供しよう
とするものである。
The present invention has been made in view of the above-mentioned problems, and includes:
The present invention aims to provide a method in which the thickness of a silicon film serving as an active region can be controlled to be constant, and an SOI substrate can be manufactured without impairing crystallinity or adhesiveness.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するために、本発明の半導体積層基板の
製造方法は、 第1の半導体基板の主面に酸化膜を形成する工程と、 上記酸化膜の一部を除去することにより、上記酸化膜に
相対的に凸部を形成する工程と、第2の半導体基板の主
面の上記第1の半導体基板の凸部と対応する位置に、凹
部を形成する工程と、 上記第1の半導体基板の凸部が上記第2の半導体基板の
凹部に嵌合するように、上記第1及び第2の半導体基板
の主面同士を貼り合わせて、熱処理により互いに接着す
る工程と、 酸化膜が露出するまで上記第2の半導体基板をその裏面
側から研磨する工程とを有するものである。
In order to solve the above problems, the method for manufacturing a semiconductor multilayer substrate of the present invention includes a step of forming an oxide film on the main surface of a first semiconductor substrate, and removing a part of the oxide film. a step of forming a convex portion relative to the film; a step of forming a concave portion on the main surface of the second semiconductor substrate at a position corresponding to the convex portion of the first semiconductor substrate; bonding the main surfaces of the first and second semiconductor substrates to each other so that the convex portions of the substrates fit into the concave portions of the second semiconductor substrate, and bonding them to each other by heat treatment; exposing the oxide film; and polishing the second semiconductor substrate from the back surface side thereof.

〔作用〕[Effect]

本発明においては、第1の半導体基板の主面に存在する
突起に対応する第2の半導体基板の主面の位置に凹部を
形成して−いるので、第1及び第2の半導体基板を互い
に貼り合わせた時に、各々の主平面同士が充分に密着す
る。従って、突起近傍の空隙や、第2のシリコン基板の
主面の撓みは生じない。
In the present invention, since the recess is formed at the position of the main surface of the second semiconductor substrate corresponding to the protrusion existing on the main surface of the first semiconductor substrate, the first and second semiconductor substrates are separated from each other. When bonded together, their respective principal planes are in close contact with each other. Therefore, no voids are formed in the vicinity of the protrusions, and no deflection of the main surface of the second silicon substrate occurs.

そして、第1の半導体基板の土面に設けた酸化膜の突起
が、第2の半導体基板を研磨する時のストッパーとして
働くので、能動領域として残す第2の半導体基板の膜厚
を一定にコントロールすることができる。
Since the protrusions of the oxide film provided on the soil surface of the first semiconductor substrate act as a stopper when polishing the second semiconductor substrate, the film thickness of the second semiconductor substrate that remains as the active region can be controlled at a constant level. can do.

〔実施例] 以下、本発明の実施例を第1図を参照して説明する。〔Example] Embodiments of the present invention will be described below with reference to FIG.

まず、第1図(a)に示すように、シリコン基板1の主
面に熱酸化法により2.5μm厚のSiO□膜2を形成
する。
First, as shown in FIG. 1(a), a 2.5 μm thick SiO□ film 2 is formed on the main surface of a silicon substrate 1 by thermal oxidation.

次いで、SiO□膜2上に7オトレジストパターンを形
成し、これをマスクとして、SiO□膜2をバッファ弗
酸溶液中で5000人の深さだけ選択エツチングし、そ
の後、フォトレジストを除去して、第1図(b)に示す
ように、SiO□膜2に相対的に凸部6を複数個形成す
る。
Next, 7 photoresist patterns were formed on the SiO□ film 2, and using this as a mask, the SiO□ film 2 was selectively etched to a depth of 5000 nm in a buffered hydrofluoric acid solution, and then the photoresist was removed. As shown in FIG. 1(b), a plurality of protrusions 6 are formed relative to the SiO□ film 2. Then, as shown in FIG.

一方、第2のシリコン基板3の主面にフォトレジストパ
ターンを形成し、これをマスクとして、シリコン基板3
の表面をプラズマエツチング法により5000人の深さ
だけ選択エツチングし、その後、フォトレジストを除去
して、第1図(C)に示すように、シリコン基板3の表
面に凹部7を形成する。ここで、シリコン基板3の表面
に形成する凹部7の位置は、第1と第2のシリコン基板
1及び3の主面同士を貼り合わせた時に、第1のシリコ
ン基板l上のSiO□膜2に形成した凸部6の位置に対
応する。
On the other hand, a photoresist pattern is formed on the main surface of the second silicon substrate 3, and using this as a mask, the silicon substrate 3 is
The surface of the silicon substrate 3 is selectively etched to a depth of 5000 mm by plasma etching, and then the photoresist is removed to form a recess 7 on the surface of the silicon substrate 3, as shown in FIG. 1(C). Here, the position of the recess 7 formed on the surface of the silicon substrate 3 is determined when the main surfaces of the first and second silicon substrates 1 and 3 are bonded together. This corresponds to the position of the convex portion 6 formed in .

次いで、第1図(d)に示すように、第1のシリコン基
板1と第2のシリコン基板3との主面同士を貼り合わせ
、熱処理を行うことにより、両者を接着する。この時、
第1のシリコン基板1上に形成されたSing膜2の凸
部6は、第2のシリコン基板3に形成された凹部7内に
収まるため、第1のシリコン基板lの凸部6を除く平面
部と第2のシリコン基板3の凹部7を除く平面部同士は
充分に密着する。また、第2のシリコン基板3が撓んだ
りすることがなく、従って、その結晶性を損なうことも
ない。
Next, as shown in FIG. 1(d), the main surfaces of the first silicon substrate 1 and the second silicon substrate 3 are bonded together, and heat treatment is performed to bond them together. At this time,
Since the convex portion 6 of the Sing film 2 formed on the first silicon substrate 1 fits within the concave portion 7 formed on the second silicon substrate 3, the flat surface excluding the convex portion 6 of the first silicon substrate l The planar parts of the second silicon substrate 3 and the second silicon substrate 3, excluding the recessed part 7, are in close contact with each other sufficiently. Further, the second silicon substrate 3 is not bent, and therefore its crystallinity is not impaired.

次いで、第1図(e)に示すように、SiO□膜2の凸
部6の一部が露出するまで第2のシリコン基板3をその
裏面側から研磨することにより、Sin。
Next, as shown in FIG. 1(e), the second silicon substrate 3 is polished from the back side until a portion of the convex portion 6 of the SiO□ film 2 is exposed, thereby forming a Si layer.

膜2上に能動領域として約5000λ厚のシリコン膜3
が形成される。
A silicon film 3 with a thickness of approximately 5000λ is formed as an active region on the film 2.
is formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、貼り合わせ法に
よって半導体積層基板を製造する際に、第1の半導体基
板の上に形成された酸化膜と、その上に貼り合わされる
第2の半導体基板との間の接着性が高く、また、能動領
域としての第2の半導体基板の結晶性を損なうことがな
い。
As explained above, according to the present invention, when manufacturing a semiconductor multilayer substrate by a bonding method, an oxide film formed on a first semiconductor substrate and a second semiconductor bonded thereon are bonded together. It has high adhesion to the substrate, and does not impair the crystallinity of the second semiconductor substrate as an active region.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明の一実施例による半導体
積層基板の製造方法を工程順に示す断面図、第2図(a
)〜(C)は従来の半導体積層基板の製造方法を工程順
に示す断面図、第3図(a)〜(c)は従来の別の半導
体積層基板の製造方法を工程順に示す断面図である。 なお、図面に用いた符号において、 l ・・・・−・・・・ 第1のシリコン基板2  ・
・・・・・・・・ 3  ・・・・・・・・・ 6  ・・・・・・・・・ 7  ・・・・・・・・・ である。 Sin、膜 第2のシリコン基板 凸部 凹部
1(a) to 1(e) are cross-sectional views showing the manufacturing method of a semiconductor multilayer substrate according to an embodiment of the present invention in the order of steps, and FIG. 2(a)
) to (C) are cross-sectional views showing a conventional method for manufacturing a semiconductor multilayer substrate in order of steps, and FIGS. 3(a) to (c) are cross-sectional views showing another conventional method for manufacturing a semiconductor multilayer substrate in order of steps. . In addition, in the reference numerals used in the drawings, l...--First silicon substrate 2.
・・・・・・・・・ 3 ・・・・・・・・・ 6 ・・・・・・・・・ 7 ・・・・・・・・・Sin, film second silicon substrate convex part concave part

Claims (1)

【特許請求の範囲】 第1の半導体基板の主面に酸化膜を形成する工程と、 上記酸化膜の一部を除去することにより、上記酸化膜に
相対的に凸部を形成する工程と、第2の半導体基板の主
面の上記第1の半導体基板の凸部と対応する位置に、凹
部を形成する工程と、 上記第1の半導体基板の凸部が上記第2の半導体基板の
凹部に嵌合するように、上記第1及び第2の半導体基板
の主面同士を貼り合わせて、熱処理により互いに接着す
る工程と、酸化膜が露出するまで上記第2の半導体基板
をその裏面側から研磨する工程とを有する半導体積層基
板の製造方法。
[Claims] A step of forming an oxide film on the main surface of a first semiconductor substrate; a step of forming a relatively convex portion in the oxide film by removing a portion of the oxide film; forming a recess on a main surface of a second semiconductor substrate at a position corresponding to the projection of the first semiconductor substrate; and the projection of the first semiconductor substrate is formed in the recess of the second semiconductor substrate. A step of bonding the main surfaces of the first and second semiconductor substrates to each other so that they fit together and bonding them to each other by heat treatment, and polishing the second semiconductor substrate from the back side until the oxide film is exposed. A method for manufacturing a semiconductor multilayer substrate, comprising the steps of:
JP25345390A 1990-09-21 1990-09-21 Manufacturing method of semiconductor laminated substrate Expired - Lifetime JP2764466B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP25345390A JP2764466B2 (en) 1990-09-21 1990-09-21 Manufacturing method of semiconductor laminated substrate
US07/763,302 US5238865A (en) 1990-09-21 1991-09-20 Process for producing laminated semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25345390A JP2764466B2 (en) 1990-09-21 1990-09-21 Manufacturing method of semiconductor laminated substrate

Publications (2)

Publication Number Publication Date
JPH04132256A true JPH04132256A (en) 1992-05-06
JP2764466B2 JP2764466B2 (en) 1998-06-11

Family

ID=17251608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25345390A Expired - Lifetime JP2764466B2 (en) 1990-09-21 1990-09-21 Manufacturing method of semiconductor laminated substrate

Country Status (1)

Country Link
JP (1) JP2764466B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008516439A (en) * 2004-10-06 2008-05-15 コミツサリア タ レネルジー アトミーク Method for manufacturing a mixed laminate structure having various insulating regions and / or local vertical conductive regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008516439A (en) * 2004-10-06 2008-05-15 コミツサリア タ レネルジー アトミーク Method for manufacturing a mixed laminate structure having various insulating regions and / or local vertical conductive regions

Also Published As

Publication number Publication date
JP2764466B2 (en) 1998-06-11

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