JPH04132086A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten precharge time and to improve operation speed by changing the continuity of a load transistor between the initial reading period and the other period. CONSTITUTION:A continuity operation means 13 deteriorating the continuity of load transistors 10 and 11 in the initial reading period of a memory cell 12 and raising the continuity of the load transistors 10 and 11 in the period other than the initial reading period is provided. Thus, in the early stages of the reading period, the supply of the load current to bit lines is suppressed, and the start of the opening of the initial bit line potential is speeded, and the supply of the load current to the bit lines is permitted in the period other than the initial reading period. The opening width of the bit line potential accompanied by the reading is suppressed, and the time necessary for the precharge of the next cycle is shortened.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to shorten the precharge time and further improve the read/write speed, especially regarding a semiconductor memory device in which bit lines are precharged using an AC loading method. A load transistor that connects between a power supply line and a bit line, a memory cell that connects to the bit line, and a conductivity of the load transistor is reduced at the beginning of a read period of the memory cell, while a period other than the beginning of the read period. and a conductivity operating means for increasing the conductivity of the load transistor, or a load transistor that connects between a power supply line and a bit line, a memory cell that connects to the bit line, potential generation means for generating a first potential and a second potential lower than the first potential; and potential selection means for selecting the first potential or the second potential and applying it to the control electrode of the load transistor. a first potential is selected at least during a precharge period of the bit line, and a second potential is selected at an early stage of a read period for the memory cell.
It is characterized by selecting the potential of .

[Industrial application field]

The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that precharges bit lines using an AC loading method.

In recent years, there has been a tendency for the operating speeds of semiconductor integrated circuits such as microcomputers to be significantly improved, but memories connected to such circuits are required to further improve their operating speeds.

[Conventional technology]

One method for improving the operating speed of a semiconductor memory device is to precharge bit lines using a load transistor. This is the following rDC loading method' and rAC
It is divided into "loading method".

In the Uni-level system shown in FIG. 7(a), the pair of bit lines BL, BL are as follows.
It is connected to a constant power supply line Vcc via N-channel transistors (hereinafter referred to as load transistors) la and 1b.

Here, the gates of load transistors 1a and 1b are connected to constant power supply line Vcc, and therefore bit line B
L and BL are the potentials of the constant power supply line (for convenience, it is assumed to be Vcc)
to the threshold voltage of the load transistor (vtg--Vt
It is precharged to a potential lowered by Mb).

That is, the precharge potential of BL is given by VccVTHa, and the precharge potential of BL is given by VCCV
Given in THII. In addition, the threshold voltage ■THa,
The size of VTl11+ is determined from the structure of the load transistor, and is approximately the same value.

In addition, FIG. 7(b) shows another example of the "rDC load method", in which P-channel type transistors are used as load transistors 2a and 2b that connect between the pair of bit lines BL, 10τ and the constant power supply line Vcc. The gates of the load transistors 2a and 2b are connected to GND (OV). The potential of the pair of bit lines BL, BL can be precharged to 0+threshold voltage.

According to these rDC loading methods, the potential of the pair of bit lines BL, BL is pre-prepared to a constant potential (VCC-L threshold voltage, or 0 + threshold voltage) lower than Vcc and higher than Ov. It can be charged and data can be transferred/written at high speed.

By the way, in such an rDC load method, the load transistors la, lb (or 2a.

2b) is always in a conductive state, a load current is supplied to the bit line via the load transistor even at the beginning of the read period. As a result, for example, as shown in FIG. 8, when reading data from a memory cell, There is a drawback that the potential development of the pair of bit lines is delayed.

On the other hand, in the AC load method, as shown in FIGS. 9(a) and 9(b), the load transistors 3a and 3b are connected between the pair of bit lines BL and π wire and the constant power line Vcc. (or 4a, 4b
) is turned on/off by a precharge signal Φ (or an inverted signal Φ of Φ), and a pair of bit lines BL, B
L and the constant power supply line Vcc can be connected only during the precharge period. According to this, for example, as shown in FIG. 10, when reading data from a memory cell, the potentials of a pair of bit lines can quickly start to open.

[Problem to be solved by the invention]

However, in a semiconductor memory device that adopts the "rAC load method," the potential difference between a pair of bit lines accompanying read/write (see FIG. (See VΔ)
This has the disadvantage that the precharge time for the next cycle becomes too large and the precharge time for the next cycle is prolonged, which is a problem that needs to be solved in terms of further improvement of the operating speed.

The present invention has been made in view of the above problems, and aims to shorten the precharge time and further improve the operating speed.

[Means to solve the problem]

In order to achieve the above object, the present invention has a block diagram of the principle shown in FIG.
, the load transistor 10.11 connecting between BL and BL.
and the memory cell 12 connected to the T line BL, Tf'''r-, and the load transistor 10.11 at the beginning of the read period of the memory cell 12.
or between a power supply line and a bit line. a memory cell connected to the bit line; a potential generation means for generating a first potential and a second potential lower than the first potential; and a potential selection means for selecting a first potential and applying it to the control electrode of the load transistor, the first potential being selected at least during the precharging period of the bit line, and the first potential being selected at the beginning of the read period for the memory cell. is the second
It is characterized by selecting the potential of .

[Effect]

In the present invention, the conductivity of the load transistor is reduced at the beginning of the read period. Therefore, during this time,
The supply of load current to the bit line is suppressed, and the opening of the bit line potential at the initial stage of reading is accelerated.

Furthermore, the degree of conductivity of the load transistor is increased during periods other than the initial period of the read period. Therefore, during this time,
As a result of allowing the supply of load current to the bit line, the width of the bit line potential difference due to reading is suppressed, and the time required for precharging in the next cycle can be shortened.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 2nd ~
FIG. 6 is a diagram showing an embodiment of the semiconductor memory device according to the present invention, and is an example of application to S-RAM (static random access memory).

In FIG. 2, II to 1. are m memory cells arranged in the column direction, BL, , BL, -BL,.

BLτ represents memory cells 11 to 1 . Each pair of bit lines is connected to a pair of bit lines BL, , ■1 -
~BL,, f section (hereinafter sometimes expressed as BL,, f section, where i is 1.2,...n) is 4 per column.
N-channel transistors (hereinafter referred to as load transistors) T1, T2, T3, T4 (~T!, T?, T
s, T9) to the power supply line ■cc.

That is, one bit line BL in the first column is connected to Vcc via load transistors TI and T2, and the other bit line BL in the first column is connected to Vcc via load transistors T and T4. And...
・One bit line BL of the n-th column is connected to Vcc via the load transistors T6 and T, and also
The other bit line BLτ of the column is a load transistor T,
and T.

It is connected to Vcc via.

Note that the P-channel type transistors T6, . . . , T1° connected between the lines of each pair of bits IBLi, r are conductive during a predetermined precharge period, and the bit line pairs BL, , BL= This is to equalize (equalize) the potential difference between.

FIG. 3(a) is a configuration diagram representatively showing the load transistors T1 to T# in the first column. A node voltage NL (described later) is applied to the gates of the two load transistors T11T4.
is given, and the remaining two transistors Tt,
A precharge signal positive which becomes high level during a predetermined precharge period is applied to the gate of T.

In FIG. 2, the node voltage NL is generated by a potential generation circuit VC consisting of transmission gate transistors Tll to TI4 and voltage dividing transistors THss TI&.

The potential generating circuit VC has a function as the conductivity operating means according to claim (1), or the potential generating means and potential selecting means according to claim (2), and (iii) the precharge signal Φ is During the high level, i.e. during a predetermined precharge period, two of the four transmission gate transistors (T
+ T1
Set to the potential of vcc (first potential, VH) (NL=
V.

= Vcc) On the other hand, (2) While the precharge signal is at a low level (or when the inverted signal of Φ is at a high level), that is, during a period other than the predetermined precharge period, for example, during the read period, the remaining 2
The two transmission gate transistors (T, 3, T14) are made conductive, and the node voltage NL is set to a second potential (1) lower than the first potential vM (NL=Vt<VN).

Here, the magnitude of the second potential VL is determined by the voltage division ratio of the two voltage dividing transistors TIS and TI6, but the point is that it is lower than the potential Vcc of the constant power line and lower than the ground potential Ov. Any high voltage is sufficient. In this embodiment, a voltage lower than Vcc by about 0.1 to 0.2 V is set.

Note that memory cells II to 1. For example, as shown in FIG. 3(b), a pair of transfer transistors T2 and T
! z, current supply resistors R, , R, and drive transistor T! 3, T'z4, and is constructed of a so-called resistive load type, and is arranged in an m×n matrix on the chip.

Note that 21 is a row address buffer that buffers a row address signal that specifies a row of a matrix; 22 is a row address buffer that decodes a row address signal, and according to the decoding result, a plurality of word lines WL, -WL;
, 01; 23 is a column address buffer that buffers a column address signal specifying a column of the matrix; 24 is a column address buffer that decodes a column address signal, and according to the decoding result, a row decoder for each column; column selection transistors (T23, T
26) Column decoder that generates column selection signals CD, ~CD, l that selectively turn on ~(T27, T28); 2
Reference numeral 5 denotes an ATD (Address Tran) that detects changes in the row address signal and column address signal and outputs the detection signal (also referred to as the ATD clock signal) SATD.
26 generates a precharge signal Φ (and its inverted signal), and changes the precharge signal Φ to a high level in response to the detection signal SATO (its inverted signal is low). Clock driver; 28.2
9 is a data amplifier and a write amplifier that buffers input data during writing; 30 is a write amplifier that amplifies manual data and writes it to a selected memory cell via the data bus DB and bit line pair BL□, 31 is a data bus reset circuit that resets the data bus DB in response to an inverted signal of the precharge signal Φ;
32 indicates the potential difference between the bit line pair BL and the "mouth potential difference (
Sense amplifier that amplifies the data of the selected memory cell; 3
3 is a data out buffer that buffers the data amplified by the sense amplifier 32 and outputs it to the outside. Note that FIG. 4 is a configuration diagram of the ATD circuit 25,
It is composed of a flip-flop circuit 25a provided for each bit of the row address signal and column address signal, and a NAND gate 26b that outputs a NAND signal of the output signal of each flip-flop circuit 25a.When the logic of one bit changes, At the moment of this change, a high level pulse signal (ATD clock signal 5ATD) is generated.

Next, the operation of this embodiment will be explained according to the operation timing chart of FIG.

Here, it is assumed that during the end period t of the read cycle, part of the read data in the read cycle remains on the bit line pair BL, , BL.

This residual voltage is precharged to a potential corresponding to the node voltage NL at that time in the subsequent precharge period t2.

That is, when a change in the address signal is detected by the ATD circuit 25, the precharge signal Φ changes to the 71 level (the inverted signal Φ is at the low level).
two of the two transmission gate transistors (T18, T
lz) is turned on, the remaining two (Tl3, Tl4) are turned off, and the node voltage NL becomes the first potential (Vcc=VH).
is set to

Then, this node voltage NL (VN) is applied to the load transistors (Tl, Ta) to (T,,,T,), and a high-level precharge signal Φ is applied to the load transistors (Tz, T3) to (T,). 'l,'
rs).

Therefore, the on-resistance of all the load transistors is operated in the direction of decreasing, or in other words, the conductivity of the transistors is operated in the direction of increasing. As a result, each bit line BLi, Tτ and the constant power line Vcc are connected with low resistance. The potential of each voltage line BL
c, VT14L (VTHL: threshold voltage of the load transistor) can be precharged.

On the other hand, in period t3 corresponding to the initial readout period, the precharge signal Φ changes to low level again, and two of the four transmission gate transistors (T1 and T1□) are turned off.
The remaining two (Tl3, T14) are turned on, and the node voltage NL is at a second potential (VL) lower than the first potential.
) is set.

This node voltage NL is then applied to the load transistor (T
1, T4) to (T8, T,), a low-level precharge signal Φ is applied to the load transistor (
Tz, T3) to (T1, T,).

When reading starts, current flows from the bit lines BL, , U■ to the memory cell, and the pair of bit lines BL, BL, U■ flow into the memory cell.
, BL, and a potential difference begins to appear between them.

During this period t3, the load transistors (T2, T3) to (T
? , Ts) are in the off state, and the node voltage N
A load transistor (Tl,
Ta) to (Ta, T9) also have a bit line potential of V
It remains off until it reaches L-VTHL.

Here, the node voltage NL in the period t3 is a second potential (VL) lower than the first potential, and the load transistor ('r, , T
4) to (Ta 1Tq ) make the on-resistance larger than the on-resistance in the precharge period t2. In other words, this corresponds to an operation in which the conductivity of the transistor is decreased.

As a result, each bit line BL, , f'f: and constant power line Vc
Since each pinto line B is connected with a “high” resistance,
The load current (current flowing through the load transistor) supplied to L, , r can be made almost zero, and the start of the opening of the potential of the bit line pair BL, , r during data reading can be increased to start the read operation. You can hasten it.

At time t4 when the bit line potential reaches vLVTHL, the load transistors (TI, T4) to (T6, Tq) to which the second potential ■ is applied are turned on, and the load current flows through these transistors. is supplied to the bit line.

Thereafter, at time t, when the current flowing from the bit line to the memory cell and the load current are balanced, the bit line potential is saturated and stabilized at the potential at that time.

Therefore, according to this embodiment, the gate potential of the load transistor is operated in two stages, the first potential (Vcc=Vo) and the second potential (VL:VL<7M), so that the gate potential of the load transistor during the precharge period is controlled. By lowering the conductivity of the bit line and increasing the conductivity of the load transistor at the beginning of the read period, ■ the load current can be quickly supplied to the bit line during the precharge period; In the early stage of the process, the load current can be supplied to almost zero to speed up the readout operation.Furthermore, during the readout period, the load current can be supplied to saturate the pinto line potential to a predetermined potential. can.

As a result, it is possible to avoid an excessive potential difference on the bit line especially during the read period (a drawback of the conventional rAC loading method), shorten the precharge period for the next cycle, and further improve the operating speed. be able to.

In the above embodiment, the voltage of Vcc is divided by the transistors T+s and T1 to create the second potential VL. However, the present invention is not limited to this, and for example, as shown in FIG.
3°, Vcc may be divided by R1+ to create VL.

Further, in the above embodiment, the transmission gate transistor Tll
Although ~TI4 has a CMO3 configuration, it may be configured with only P channel transistors T0 and TI3, or only N channel transistors T, 2, and TI4, for example.

Furthermore, the load transistors T, , T, may be P-channel transistors. However, in that case, the control voltage (NL) is set to have a polarity opposite to that in the case of an N-channel transistor (the above embodiment).

〔Effect of the invention〕

According to the present invention, since the conductivity of the load transistor is changed between the initial reading period and the other periods, the precharge time can be shortened and the operating speed can be further improved. can.

[Brief explanation of drawings]

The first page is a diagram showing the principle configuration of the present invention. Figures 2 to 6 are diagrams showing an embodiment of the present invention. Figure 2 is a configuration diagram thereof, and Figure 3 (a) is a circuit diagram of the load transistor. Figure 3(b) is a circuit diagram of the memory cell, Figure 4 is a circuit diagram of the ATD circuit, Figure 5 is an operation timing chart, and Figure 6 is a circuit diagram of a modified example of the voltage divider circuit. It is. 7 to 10 are diagrams showing conventional examples, FIG. 7(a) is a configuration diagram of the main parts of the DC load method, FIG. 7(b) is a diagram of the main parts of the DC load method, Figure 8 is a waveform diagram of the bit line potential at the initial stage of reading for the DC load method, Figure 9 (a) is a configuration diagram of the second main part of the AC load method, and Figure 9 (b) is for the AC load method. Another main part configuration diagram, FIG. 10, is a waveform diagram of the bit line potential at the initial stage of AC loading and reading. VC... Potential generation circuit (conductivity control means, potential generation means, potential selection means). 10.11...Load transistor, 12...
...Memory cell, 13...Conductivity operating means, Vcc-...Constant voltage agi line, BL, T...Bit line, BL8, ■T-... ...Bit line, 1+-11I・
...Memory cell, T1 to T4...Load transistor, T6 to T, ...Load transistor, Figure L - Circuit diagram of load transistor of embodiment (a) One implementation Circuit diagram of the example memory cell (b) Figure 3 Circuit diagram of the ATD circuit of one embodiment Figure 4 Operation timing chart of one embodiment Figure 5

Claims (2)

[Claims] (1) A load transistor that connects between a power supply line and a bit line, a memory cell that connects to the bit line, and a conductivity level of the load transistor that is lowered at the beginning of the read period of the memory cell; A semiconductor memory device comprising: a conductivity control means for increasing the conductivity of the load transistor during a period other than the above. (2) a load transistor that connects between a power supply line and a bit line; a memory cell that connects to the bit line; and potential generation means that generates a first potential and a second potential that is lower than the first potential. and potential selection means for selecting the first potential or the second potential and applying the selected potential to the control electrode of the load transistor, and selecting the first potential at least during a precharge period of the bit line. . A semiconductor memory device, wherein a second potential is selected at the beginning of a read period for the memory cell.