JPH04129448A - Frame synchronization system and transmitter and receiver adopting the system - Google Patents

Abstract

PURPOSE:To attain accurate frame synchronization locking at all times by implementing insertion of a frame synchronizing signal and establishment of frame synchronization before differential logic coding and after differential logic decoding respectively. CONSTITUTION:A frame insertion means 1 is arranged before a differential logic coding means 2 in a sender side equipment to insert a frame synchronizing signal to a transmission digital signal before differential logic coding, and a frame synchronization means 10 is arranged after a differential logic decoding means 9 at a receiver side equipment to implement the processing for establishing frame synchronization. Then a signal selection means 8 is provided between an error correction decoding means 6 and the differential logic decoding means 9, and a reception digital signal not implementing error correction decoding is selected when the frame synchronization is not established and the reception digital signal after error correction decoding is selected while the frame synchronization is established to implement the differential logic decoding processing. Thus, frame synchronization is accurately taken.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention is directed to a digital microwave radio communication system that employs a multilevel quadrature amplitude modulation method, such as a terrestrial microwave radio communication system. In particular, the present invention relates to a frame synchronization method used when error correction processing is performed after differential conversion processing has been performed on a transmission signal, and to a transmitting device and a receiving device to which this method is applied.

(Prior Art) In recent years, 22m value (m-1, 2, 3,...) quadrature amplitude modulation (Q A M ) has been used as one of the transmission methods for digital microwave communication.
tude Mo-claration) method is adopted. This QAM method transmits digital data by changing both the amplitude and phase of a carrier wave, and can realize more efficient transmission.

By the way, in systems that have recently applied this type of method,
From 16Q AM modulation system to 64Q AM modulation system,
Multi-value modulation is progressing toward 256Q AM modulation, and as a result, communication devices are required to have even higher precision in amplitude characteristics, delay characteristics, linearity, and the like. However, there is a certain limit to the increase in precision of hardware, and in the BER characteristic for C/H, which represents the performance of a communication device, a remaining amount BER occurs where the BER decreases below a certain value.

Therefore, an error correction circuit has been conventionally used as an effective means for reducing this residual BER. Block codes such as BCH codes and Reed-Solomon codes are generally used as error correction codes. When error correction processing is performed using this block code, it is necessary to know the delimiter of each block, and therefore, it is necessary for the communication device on the receiving side to establish frame synchronization with respect to the received signal.

On the other hand, in a digital microwave wireless communication system, differential conversion processing is performed in order to remove phase uncertainty of a recovered carrier wave that occurs in a communication device on the receiving side. Differential conversion processing is such that a communication device on the transmitting side performs a summation operation on a transmission code and transmits the result, and a communication device on the receiving side performs a differential operation on the received code. However, when this differential conversion processing is used, errors occurring in the transmission code on the transmission path will be doubled when the receiving communication device calculates the difference, so if error correction processing is performed after the difference calculation, the error will be doubled. This leads to a decline in correction ability. For this reason, error correction processing is generally performed between the summation calculation and the difference calculation, that is, inside the differential logic.

(Problems to be Solved by the Invention) However, when error correction processing is performed inside the differential logic in this way, the following problems occur. That is, when a block code is used as an error correction code as described above, frame synchronization must be performed in the communication device on the receiving side in order to know the delimitation of the block. However, when trying to achieve frame synchronization before the difference calculation, the phase of the recovered carrier wave changes to 0', 90°, and 180°.
' or 270°, the phase of the frame synchronization signal can take on four different patterns. Therefore, if the correct pattern cannot be detected,
This has caused a problem in that frame synchronization cannot be established, which makes it impossible to perform accurate error correction.

Therefore, the present invention focuses on the above-mentioned circumstances, and provides a frame synchronization method and transmission that makes it possible to accurately synchronize frames without reducing error correction ability and without being affected by the phase uncertainty of a reproduced carrier wave. The purpose of the present invention is to provide a device and a receiving device.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the frame synchronization method of the present invention provides a frame synchronization method in which a transmitting side device performs differential logic encoding on a transmitted digital signal using a differential logic encoding means. After that, error correction encoding is performed, and then multi-level orthogonal amplitude modulation is performed and transmitted. On the other hand, at the receiving side device, after performing multi-level orthogonal amplitude demodulation on the received signal, error correction decoding means is used to remove errors. In a digital microwave wireless communication system that performs correction decoding and then performs differential logic decoding processing by differential logic decoding means to reproduce a digital signal,
The transmitting side device arranges a frame inserting means before the differential logic encoding means to insert a frame synchronization signal into the transmitted digital signal before differential logic encoding, and the receiving side device inserts a frame synchronization signal into the transmitted digital signal before differential logic encoding. A frame synchronization means is arranged after the dynamic logic decoding means to perform processing for establishing frame synchronization, and a signal selection means is provided between the error correction decoding means and the differential logic decoding means, and the signal selection means is provided between the error correction decoding means and the differential logic decoding means. In a state where frame synchronization is not established, the received digital signal that has not been subjected to the error correction decoding is selected and supplied to the differential logic decoding process, and in a state where frame synchronization is established, the received digital signal is subjected to the error correction decoding. The received digital signal after conversion is selected and supplied to the differential logic decoding process.

Another transmitting device of the present invention includes a frame insertion means for inserting a frame synchronization signal into a transmission digital signal, and a differential logic encoding process for performing differential logic encoding processing on the transmission digital signal outputted from the frame insertion means. dynamic logic encoding means; error correction encoding means for performing error correction encoding processing on the transmission digital signal output from the differential logic encoding means; and transmission digital signal output from the error correction encoding means. and multi-value orthogonal amplitude modulation means for performing multi-value orthogonal amplitude modulation on the signal for transmission.

Still another receiver of the present invention includes a multi-level quadrature amplitude demodulation means for performing multi-level quadrature amplitude demodulation on a received signal and outputting the demodulated received signal, and a An error correction decoding means for performing error correction decoding processing on a received signal, a received signal subjected to error correction decoding processing by the error correction decoding means, and a received signal without error correction decoding processing performed. a signal selection means for alternatively selecting the signal selection means; a differential logic decoding means for performing differential logic decoding processing on the received signal selected by the signal selection means; and the differential logic decoding means. frame synchronization means for detecting a frame synchronization signal from a received signal output from the frame synchronization means and performing processing for establishing synchronization;
The signal selection means is controlled based on the operation of establishing frame synchronization by the frame synchronization means, and in a state where frame synchronization is not established, the received digital signal that has not been subjected to error correction decoding is selected. In the established state, the signal selection control means selects the received digital signal after the error correction decoding.

(Function) As a result, according to the present invention, insertion of a frame synchronization signal and establishment of frame synchronization are performed before differential logic encoding and after differential logic decoding, respectively.

That is, processing related to establishing frame synchronization is performed outside the differential logic. Therefore, frame synchronization is established without being affected by the phase uncertainty of the reproduced carrier wave, and thereby accurate frame synchronization can be performed at all times. In addition, in a state where frame synchronization has not been established, the received digital signal that has not been subjected to error correction decoding or is used to establish frame synchronization through differential logic decoding processing, so the influence of incorrect error correction processing frame synchronization can be established without receiving

(Embodiment) FIG. 1 is a diagram for explaining a frame synchronization method in an embodiment of the present invention, and shows a block configuration of a modulation unit of a transmitting side wireless device and a demodulation unit of a receiving side wireless device. .

The modulation unit includes a sum calculation section 2 that performs differential logic encoding on the transmission digital signal, an error correction encoding section 3 that performs error correction encoding, and a modulation section 4 that performs orthogonal amplitude modulation.
A frame insertion section 1 is arranged before the summation calculation section 2. This frame insertion section 1 inserts a frame synchronization signal consisting of a predetermined signal pattern into the transmission digital data before differential logic encoding.

On the other hand, the demodulation unit includes a demodulation section 5 that performs orthogonal amplitude demodulation of the received signal, an error correction decoding section 6 that performs error correction decoding on the demodulated digital signal, and a difference calculation section 9 that performs differential logic decoding. A frame synchronization section 10, which generates a frame synchronization detection signal $5YNC necessary for the error correction decoding, is arranged at a subsequent stage of the difference calculation section 9.

That is, in the demodulation unit, processing is performed to establish frame synchronization based on the differentially logically decoded received digital signal. In addition, the error correction decoding section 6
A signal switching section 8 is inserted between the demodulating section 5 and the difference calculating section 9, and a delay circuit section 7 is inserted between the demodulating section 5 and the signal switching section 8.
is provided. The signal switching section 8 is connected to the frame synchronization section 1
In a state in which the frame synchronization detection signal 5YNC is not supplied from 0 to 0, that is, in a state in which frame synchronization is not established, the delay circuit section 7 side switches to the difference calculation section 9 to convert the received digital signal that has not been subjected to error correction decoding to the frame synchronization detection signal 5YNC. supply to. On the other hand, the frame synchronization detection signal 5Y from the frame synchronization unit 10
In a state where NC is supplied, that is, when frame synchronization is established, the error correction decoding section 6 side is switched to supply the error correction decoded received digital signal to the difference calculation section 9.

FIG. 2 shows an example of a specific configuration of a digital microwave wireless communication system to which the frame synchronization method of this embodiment is applied. It shows.

The transmitting side wireless device A includes a transmitting digital signal processing unit (T-DPU) 11 that performs predetermined signal processing on a transmitting digital signal output from a terminal device (not shown);
A modulation unit 20 and a transmission unit (TX
) 30.

Among these, the modulation unit 20 is a speed conversion circuit (SPDC).
ONV) 21 and frame insertion circuit (FRMINS) 2
2, a sum calculation circuit (SUMLOG) 2B, an error correction circuit encoder (FECENC) 24, and a 64-value quadrature amplitude modulation circuit (64QAMMOD) 25. The frame insertion circuit 23 inserts a frame synchronization signal at the beginning position of the transmitted digital signal before the summation calculation, as shown in FIG. 3, for example.

On the other hand, the radio device B on the receiving side is a receiving unit (RX) that receives the microwave signal sent from the radio device A on the transmitting side via the wireless line via the receiving antennas 41 and 42.
40 and the Space Diperity Synthesis Unit (SDC)
OMB) 50 and fading automatic equalization unit (EQ
L) 60, a demodulation unit 70, and a reception digital signal processing unit (R-DPU) 80.

Among these, the demodulation unit 70 includes a 64-value quadrature amplitude demodulation circuit (64QAMDEM) 71 and an l\ibrid circuit (H
YB) 72 and error correction circuit decoder (FECDEC) 7
B, selector (SELECT) 74, difference calculation circuit (DIFLOG) 75, and frame synchronization circuit (FRMR).
EC) 76, a speed conversion circuit (SPDCONV) 77, and a delay circuit (DELAY) 78.

The hybrid circuit 72 branches the demodulated digital signal output from the 64-value orthogonal amplitude demodulation circuit 71 into two, supplies one to the error correction circuit decoder 73, and supplies the other to the selector 74 via the delay circuit 78.

The selector 74 operates depending on whether or not the frame synchronization detection signal 5YNC is generated from the frame synchronization circuit 76. During the period when the frame synchronization detection signal 5YNC is not generated, the selector 74 operates based on the presence or absence of the frame synchronization detection signal 5YNC from the frame synchronization circuit 76. A signal is selected and output to the difference circuit 75. On the other hand, during the period when the frame synchronization detection signal 5YNC is being generated,
The error correction decoded demodulated digital signal output from the error correction circuit decoder 73 is selected and the difference calculation circuit 75
Output to.

The frame synchronization circuit 76 stores and holds a preset comparison signal pattern, and establishes frame synchronization by comparing the signal pattern of the demodulated frame synchronization signal after differential calculation processing with this comparison signal pattern. Then, in a state where frame synchronization is established, a frame synchronization detection signal 5YNC is generated.

The delay circuit 78 has a delay time corresponding to the signal processing time of the error correction circuit decoder 73, and delays the demodulated digital signal by this delay time.

Next, the operation of the system configured as above will be explained.

First, the 64Q A system adopted in this embodiment
The differential conversion method of M will be explained. That is, in general, in 84QAM, as shown in FIG. 2, the highest two sequences (a,.

a2) is called the first bus, the two series below it (a3 and a4) are called the second path, and the lowest two series (a5 and a6) are called the third pass. As one method for improving the bit error rate characteristics, a rotationally symmetric arrangement differential conversion method has been adopted.

FIG. 4 shows the signal point arrangement of this system, where () represents the first bus, () the second path, and the part without parentheses represents the third path. As shown in the figure, the rotationally symmetric signal point arrangement performs sum-difference calculations by correlating the first bus signal with the signal representing the quadrant, and gray-codes the signals from the second pass onwards. The code of the second pass, which is later represented by two bits in the first quadrant, is assigned to the other quadrants in a rotationally symmetrical manner. With such a signal point arrangement, as can be seen from FIG. 4, the signals of the second and third paths are the same in each quadrant, and only the first bus is different in each quadrant. Therefore, when performing differential conversion, it is only necessary to perform differential conversion on the first bus, and it is not necessary for the second and third paths.

Furthermore, Fig. 5 shows the change in the signal pattern of the received digital signal that occurs due to the influence of the phase uncertainty of the recovered carrier wave on the receiving side when such a rotationally symmetric arrangement type differential conversion is used. . Therefore, if frame synchronization is to be established inside the differential logic, it is necessary to compare signal patterns in consideration of the influence of the phase uncertainty of the reproduced carrier wave.

Now, in such a configuration, first, the following operation is performed in the transmitting side wireless device A. That is, the transmission digital signals a, to a6 outputted from the transmission digital signal processing unit 11 are first subjected to speed conversion in a speed conversion circuit 21, and then a frame synchronization signal is added to them in a frame insertion circuit 22. Next, the transmission digital signal into which this frame synchronization signal has been inserted is subjected to a summation calculation using a rotationally symmetric arrangement type difference conversion method in a summation calculation circuit 23, and then an error correction circuit encoder 24 performs a summation calculation using a rotationally symmetric arrangement type difference conversion method. The signal is subjected to correction encoding processing, then modulated by an 84-value orthogonal amplitude modulation circuit 25, and further frequency-converted into microwaves by a transmitting unit 30, and then wirelessly transmitted from a transmitting antenna 31.

That is, in the transmitting side wireless device A, a frame synchronization signal is inserted into the transmitted digital signal before differential logic processing, and error correction encoding is performed after differential logic processing.

On the other hand, the radio device B on the receiving side performs the following operation. That is, a microwave signal that arrives from the transmitting side wireless device A via a wireless line is received by the receiving unit 40 via two receiving antennas 41 and 42 provided for space diversity, and then received by the receiving unit 40. The signals are synthesized by a space diversity synthesis unit 50 and subjected to fading correction processing by an automatic fading equalization unit 60, and then input to a demodulation unit 70.

In this demodulation unit 70, a received digital signal is first demodulated in a 64-value orthogonal amplitude demodulation circuit 71, and then is partially demodulated by a hybrid circuit 72 and supplied to an error correction circuit decoder 73 and a delay circuit 78, respectively. The demodulated digital signal after error correction processing outputted from the error correction circuit decoder 73 and the demodulated digital signal delayed by the delay circuit 78 are sent to the selector 7.
After being selectively selected in step 4, it is supplied to a difference calculation circuit 75, and after being subjected to difference calculation processing by this difference calculation circuit 75, it is supplied to a frame synchronization circuit 76, where frame synchronization pull-in processing is performed.

By the way, in a state where frame synchronization has not yet been established, the frame synchronization detection signal 5YNC is not generated from the frame synchronization circuit 76. For this reason, the selector 74
Then, the demodulated digital signal output from the delay circuit 78 and which has not been subjected to error correction decoding is selected and supplied to the difference calculation circuit 75. After differential calculation processing is performed in this circuit 75, the signal is supplied to a frame synchronization circuit 76. Therefore, frame synchronization circuit 76 performs frame synchronization based on the demodulated frame synchronization signal that has not been subjected to error correction decoding. That is,
In the frame synchronization circuit 76, frame synchronization is performed on the demodulated digital signal that has undergone differential logic processing. Therefore, when performing frame synchronization pull-in, there is no need to consider the influence of phase uncertainty of the reproduced carrier.

Now, when frame synchronization is established, the error correction circuit decoder 73 starts correct error correction processing in synchronization with the frame signal FRM output from the frame synchronization circuit 76. At the same time, the selector 74 outputs a frame synchronization detection signal 5 output from the frame synchronization circuit 76.
In accordance with YNC, a demodulated digital signal that has been correctly error-corrected decoded by the error correction circuit decoder 73 is selected in place of the previously selected demodulated digital signal with no error correction, and is supplied to the difference calculation circuit 75. be done. The error-corrected demodulated digital signal is subjected to a difference calculation in the difference calculation circuit 75, and then subjected to frame synchronization monitoring in a frame synchronization circuit 76, and then subjected to speed conversion in a speed conversion circuit 77. The received digital signal is supplied to a processing unit 80, where the digital data is reproduced.

In this way, the frame synchronization method of this embodiment arranges the error correction circuit encoder 24 and the error correction circuit decoder 73 inside the differential logic, while the frame insertion circuit 22 and the frame synchronization circuit 76 are arranged inside the differential logic. placed outside of
In addition, a selector 74 is provided in the radio device B on the receiving side, and when frame synchronization is not established, the selector 74 selects a demodulated digital signal that is not subjected to error correction decoding and uses it for frame synchronization pull-in processing. It is.

Therefore, since error correction processing is performed inside the differential logic, errors occurring in the transmission path can be corrected without deteriorating the error correction capability. In addition, since the frame synchronization required for this error correction process is performed outside the differential logic, frame synchronization cannot be achieved due to the influence of the phase uncertainty of the recovered carrier wave, unlike when establishing frame synchronization inside the differential logic. There is no fear that frame synchronization will not be established correctly, and frame synchronization can always be established correctly. Furthermore, in order to establish frame synchronization outside the differential logic, the selector 74 selects a demodulated digital signal that is not subjected to error correction decoding when frame synchronization is not established, and uses it for frame synchronization. There is no problem in which frame synchronization is performed based on an unreliable demodulated digital signal that has been subjected to error correction processing in an unsynchronized state, and thus frame synchronization can be achieved correctly.

Note that the present invention is not limited to the above embodiments.

For example, in radio equipment B on the receiving side, the error correction decoding unit performs exclusive OR processing on the error correction decoding circuit 61, the delay circuit 62, and the output signals of these circuits 61 and 62, as shown in FIG. and an exclusive OR circuit 63. That is, the error correction decoding section 6' already has a delay circuit 62 within itself. Therefore, focusing on this point,
In FIG. 1, the delay circuit section 7 provided separately from the error correction decoding section 6 is replaced with the delay circuit section 7 in the error correction decoding section 6'.
2 may be used for both purposes.

In this way, the circuit configuration of the demodulation unit can be made simple and inexpensive.

In addition, the configurations of the transmitting side wireless device and the receiving side wireless device, the type of differential conversion method, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, the present invention provides a frame insertion means arranged before the differential logic encoding means in the transmitting side device,
A frame synchronization signal is inserted into the transmitted digital signal before differential logic encoding, and in the receiving side device, a frame synchronization means is arranged after the differential logic decoding means to perform processing for establishing frame synchronization, and A signal selection means is provided between the error correction decoding means and the differential logic decoding means, and the signal selection means selects the received digital signal that has not been subjected to the error correction decoding in a state where frame synchronization is not established. The received digital signal is subjected to the differential logic decoding process, and when frame synchronization is established, the received digital signal subjected to the error correction decoding is selected and subjected to the differential logic decoding process.

Therefore, according to the present invention, it is possible to provide a frame synchronization method that can accurately achieve frame synchronization without reducing error correction capability and without being affected by phase uncertainty of a reproduced carrier wave.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of a digital microwave wireless communication system applying a frame synchronization method according to an embodiment of the present invention, and FIG. 2 is an example of a specific configuration of the system shown in FIG. 1. 3 is a diagram showing the insertion position of the frame synchronization signal, FIG. 4 is a diagram showing the signal point arrangement in the case of rotationally symmetrical arrangement type differential conversion method, and Fig. 5 is a diagram showing the rotationally symmetrical arrangement type. FIG. 6 is a diagram showing a change in a reception pattern due to phase uncertainty of a reproduced carrier wave in the case of a differential conversion method. FIG. 6 is a circuit block diagram showing a main part configuration of a demodulation unit in another embodiment of the present invention. A... Radio device on the transmitting side, B... Radio device on the receiving side, 1... Frame insertion section, 2... Sum calculation section, 3.
...Error correction encoding unit, 4...Modulation unit, 5...Demodulation unit, 6, 6'...Error correction decoding unit, 7...Delay circuit unit, 8...Signal switching unit , 9... difference calculation section, 10
...Frame synchronization unit, 11...Transmission digital signal processing unit) (T-DPU), 20...Modulation unit, 2]...Speed conversion circuit (SPDCONV),
22・-Frame insertion circuit (FRMINS), 2B・
... Sum calculation circuit (SUMLOG), 24... Error correction circuit encoder (FECENC), 25... 64-value quadrature amplitude modulation circuit (84QAMMOD) 30...
Transmission unit (TX) 31... Transmission antenna, 4
0...Reception 1 nit (RX) 41.42...Reception antenna, 50...Space diversity combining unit (SDCOMB), 60...Fading automatic equalization unit) (EQL), 70... Demodulation unit, 71...64-value quadrature amplitude demodulation circuit (84QAMDE
M) 72...Hybrid circuit (HYB), 7B.
...Error correction circuit decoder (FECDEC), 74...
・Selector, 75...Difference calculation circuit (DI FLO
G), 76...Frame synchronization circuit (FRMREC)
, 7711. Speed conversion circuit (SPDCONV), 8
Zero Mountain Reception Digital Signal Processing Unit (R-DPU). Applicant's representative Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) The transmitting device performs differential logic encoding on the transmission digital signal using differential logic encoding means, performs error correction encoding, and then performs multilevel orthogonal amplitude modulation and transmits the signal. In the receiving side device, after performing multilevel orthogonal amplitude demodulation on the received signal, the error correction decoding means performs error correction decoding, and then the differential logic decoding means performs differential logic decoding processing to convert the digital signal. In the reproducing digital microwave wireless communication system, the transmitting side device arranges a frame insertion means before the differential logic encoding means, and inserts a frame synchronization signal into the transmitted digital signal before differential logic encoding. The receiving side device arranges a frame synchronization means after the differential logic decoding means to perform processing for establishing frame synchronization, and the receiving side device performs processing for establishing frame synchronization between the error correction decoding means and the differential logic decoding means. is provided with a signal selection means, and the signal selection means selects the received digital signal which has not been subjected to the error correction decoding in a state where frame synchronization has not been established and provides it to the differential logic decoding process, while the frame synchronization A frame synchronization method characterized in that in a state in which the error correction decoding has been established, the received digital signal after the error correction decoding is selected and subjected to the differential logic decoding processing. (2) On the transmitting side, the transmitted digital signal is subjected to differential logic encoding, then error correction encoding, and then multilevel orthogonal amplitude modulation is performed and transmitted. On the other hand, on the receiving side, the received signal is In a transmitting device used in a digital microwave wireless communication system that performs multilevel orthogonal amplitude demodulation, then performs error correction decoding, and then performs differential logic decoding processing to reproduce the digital signal, the transmitted digital signal is a frame insertion means for inserting a frame synchronization signal into the frame; a differential logic encoding means for performing differential logic encoding processing on the transmission digital signal outputted from the frame insertion means; an error correction encoding means for performing error correction encoding processing on the transmission digital signal output from the error correction encoding means; and a multi-value orthogonal amplitude modulation of the transmission digital signal output from the error correction encoding means for use in transmission. 1. A transmitting device comprising orthogonal amplitude modulation means. (3) On the transmitting side, the transmitted digital signal is subjected to differential logic encoding, then error correction encoding, and then multilevel orthogonal amplitude modulation is performed and transmitted; on the other hand, on the receiving side, the received signal is In a receiving device used in a digital microwave wireless communication system that performs multilevel orthogonal amplitude demodulation, then performs error correction decoding, and then performs differential logic decoding processing to reproduce the digital signal, Multi-value orthogonal amplitude demodulation means for performing multi-value orthogonal amplitude demodulation and outputting a demodulated received signal; and error correction decoding for performing error correction decoding processing on the received signal output from the differential logic decoding means. signal selection means for selectively selecting between a received signal subjected to error correction decoding processing by the error correction decoding means and a received signal not subjected to error correction decoding processing; , differential logic decoding means for performing differential logic decoding processing on the received signal selected by the signal selection means; and detecting a frame synchronization signal from the received signal output from the differential logic decoding means. A frame synchronization means performs processing for establishing synchronization, and the signal selection means is controlled based on the frame synchronization establishing operation by the frame synchronization means, whereby error correction decoding is performed in a state where frame synchronization is not established. 1. A receiving device comprising signal selection control means for selecting a received digital signal that has not been decoded, while selecting a received digital signal that has been subjected to error correction decoding in a state where frame synchronization has been established.