JPH04127460A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04127460A JPH04127460A JP2248256A JP24825690A JPH04127460A JP H04127460 A JPH04127460 A JP H04127460A JP 2248256 A JP2248256 A JP 2248256A JP 24825690 A JP24825690 A JP 24825690A JP H04127460 A JPH04127460 A JP H04127460A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- substrate
- group
- pad electrode
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 229910010293 ceramic material Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920002050 silicone resin Polymers 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特に外部接続用電極
としてリードピンを用いる多端子型混成集積回路の構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and particularly to the structure of a multi-terminal hybrid integrated circuit using lead pins as external connection electrodes.
従来、リードピンを有する混成集積回路の例は少ないが
、半導体素子のパッケージ方法の一つとして、多層の半
導体素子搭載基板の裏面全体にリードピンを配列したＰ
Ｇ Ａ （Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ；ビン・グ
リッド・アレイ）が用いられている。また、このＰＧＡ
の応用例として、第３図に示される様なマルチチップ実
装を行なったＰＧＡが用いられる様になった。この第３
図は、セラミックスあるいはガラスエポキシ等の基材を
用いた多層ピングリッドアレイ基板１３上に半導体素子
６を複数個搭載したもので、半導体素子６はワイヤボン
ディング後にチップコート樹脂８による樹脂封止を行な
うか、金属キャップ等によるキャップシールを行なって
いる。このＰＧＡは、リードピンの配置を格子状にする
ことができるため、例えば３０畦四方の小型サイズの基
板であっても、２．５４＋ｎｍピッチで１００ピン以上
の多端子基板とすることができる。Conventionally, there are few examples of hybrid integrated circuits that have lead pins, but as one method of packaging semiconductor elements, a P-type integrated circuit in which lead pins are arranged on the entire back surface of a multilayer semiconductor element mounting board is used.
G A (Pin Grid Array) is used. Also, this PGA
As an application example, a PGA with multi-chip mounting as shown in FIG. 3 has come to be used. This third
The figure shows a plurality of semiconductor elements 6 mounted on a multilayer pin grid array substrate 13 using a base material such as ceramics or glass epoxy, and the semiconductor elements 6 are resin-sealed with chip coat resin 8 after wire bonding. Alternatively, a cap seal is performed using a metal cap or the like. In this PGA, the lead pins can be arranged in a lattice pattern, so even a small board with 30 square ridges, for example, can be made into a multi-terminal board with 100 or more pins at a pitch of 2.54+nm.
このようなＰＧＡの特徴を活かして多数のり−ドピンを
配置したＰＧＡ基板と、電子部品を実装した多層基板と
をはんだにより結合し、ＰＧＡタイプの混成集積回路と
することが提案されている。その構造例は、第４図に示
される。この図の様に多層基板１の裏面に形成された第
１のパッド電極層群１１とＰＧＡ基板２の上に形成され
た第二のパッド電極層群１２とが各々はんだ３により接
合され、外部リードとなるリードピン４と電気的に接続
される。この場合、はんだ３はその表面張力によって高
さを有し、従って多層基板１とＰＧＡ基板２との間に隙
間が生じてくる。It has been proposed that, taking advantage of such characteristics of PGA, a PGA board on which a large number of bonded pins are arranged and a multilayer board on which electronic components are mounted are connected by solder to form a PGA type hybrid integrated circuit. An example of its structure is shown in FIG. As shown in this figure, the first pad electrode layer group 11 formed on the back surface of the multilayer substrate 1 and the second pad electrode layer group 12 formed on the PGA substrate 2 are each bonded by solder 3, and the external It is electrically connected to a lead pin 4 serving as a lead. In this case, the solder 3 has a height due to its surface tension, and therefore a gap is created between the multilayer substrate 1 and the PGA substrate 2.
このように従来のＰＧＡあるいは、マルチチップＰＧＡ
では、リードピンと半導体素子を含む電子部品を実装す
る基板とを合わせた製品固有の基板構造として開発する
ために、多額の開発コストがかかっていた。また、基板
そのものの汎用性が少なく、製品価格が高くなるために
民生機器への応用が少ないのが実情であった。In this way, conventional PGA or multi-chip PGA
However, a large amount of development costs were required to develop a product-specific board structure that includes lead pins and a board on which electronic components including semiconductor elements are mounted. In addition, the board itself has little versatility and the product price is high, so there are few applications for consumer devices.
この問題を解決する方法として、多層基板上に電子部品
を実装し、リードピンを規則的に配列したピングリッド
アレー基板とをはんだにより接続する方法が提案されて
いる。この方法を用いた場合、電極ピッチが大きくはん
だ接続面積が大きい場合には問題とならないが、例えば
電極ピッチが１．２７ｎ＋ｍ程度まで小さくなると、は
んだ接続電極は一辺６００μｍとなり、モジュールの抜
き差し時に応力が集中して接続部の強度が不十分となる
。また、はんだ接続部が露出した状態となるために、は
んだ接続部の酸化、腐食等による劣化等長期的信頼性の
面からも問題点が多くなる。As a method to solve this problem, a method has been proposed in which electronic components are mounted on a multilayer board and connected to a pin grid array board in which lead pins are regularly arranged using solder. When using this method, there is no problem when the electrode pitch is large and the solder connection area is large, but if the electrode pitch is reduced to about 1.27n+m, for example, the solder connection electrode will be 600μm on a side, and stress will be generated when inserting and removing the module. The strength of the connection part becomes insufficient due to the concentration of the parts. Furthermore, since the solder joints are exposed, there are many problems in terms of long-term reliability such as deterioration of the solder joints due to oxidation, corrosion, etc.
本発明の目的は、これらの欠点を解決し、はんだ接続部
に強度があり、接続不良もなく信頼性の高い混成集積回
路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve these drawbacks and provide a highly reliable hybrid integrated circuit with strong solder connections and no connection defects.
本発明の構成は、−面上に電子部品あるいは半導体素子
を搭載し、他面に他への接続用の第１のパッド電極層群
を設けた第１の絶縁基板と、外部との接続用に規則的に
配列されたり−ドピン群を一面に設け、このリードピン
群の各々と電気的に接続された第２のパッド電極層群を
他面に設けた第２の絶縁基板とを備え、前記第１のパッ
ド電極層群の各パッドと前記第２のパッド電極層群の各
パッドとがはんだあるいは導電性樹脂により電気的に接
続された混成集積回路装置において、前記第１の絶縁基
板と前記第２の絶縁基板との間の全域あるいはその周縁
部に封止樹脂が充填されたことを特徴とする。The structure of the present invention includes a first insulating substrate on which an electronic component or a semiconductor element is mounted on one side and a first pad electrode layer group for connection to another on the other side, and a first insulating substrate for connection to the outside. a second insulating substrate provided with a group of doped pins arranged regularly on one surface and a second group of pad electrode layers electrically connected to each of the group of lead pins on the other surface; In the hybrid integrated circuit device in which each pad of the first pad electrode layer group and each pad of the second pad electrode layer group are electrically connected by solder or conductive resin, the first insulating substrate and the It is characterized in that the entire area between it and the second insulating substrate or its periphery is filled with a sealing resin.
次に本発明について、図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例を示す概略断面図である。図
に示される様に、ガラスエポキシまたはセラミックス等
を基材とする多層基板１上に半導体素子６．チップ部品
９．ミニモールド部品１０等が実装される。この多層基
板１上への部品実装は、リードピンの付いていない状態
、で行なわれるために、通常の混成集積回路と同様の工
程により電子回路部の実装が行なわれる。リードピン４
は、あらかじめピングリッドアレー基板２へ規則的に配
置されており、各基板に形成されたパッド電極群がはん
だにより接続される。FIG. 1 is a schematic sectional view showing an embodiment of the present invention. As shown in the figure, semiconductor elements 6. Chip parts9. Mini mold parts 10 and the like are mounted. Since components are mounted on the multilayer substrate 1 without lead pins attached, the electronic circuit section is mounted using the same steps as those for a normal hybrid integrated circuit. Lead pin 4
are arranged regularly on the pin grid array substrate 2 in advance, and the pad electrode groups formed on each substrate are connected by solder.
この混成集積回路は、このはんだ接続部のある二基板間
に樹脂を充填し、接続部を封止すると同時に、機械的に
補強する。補強用の樹脂としては、熱硬化型のシリコン
系樹脂あるいはエポキシ系樹脂あるいは常温硬化型のシ
リコーン系樹脂等が利用できる。はんだの接続強度は、
はんだの弓張り強度が常温で５ 、７５ ｋｇ／ ｌ１
１２であるとすると、−辺０．５ｍｍの一電極あたりの
引張り強度は約１．４ｋｇである。ピングリッドアレー
基板の場合、３０１１１１四方の基板には約１００の電
極が形成可能であり、基板全体としては１４０ ｋｇ以
上の強度が得られる。しかしながらモジュールの抜き差
し時等には偏った力が加わることによって−電極あたり
数ｋｇの力が加わることが予想される。In this hybrid integrated circuit, a resin is filled between the two substrates where the solder connection portion is located to seal the connection portion and at the same time mechanically reinforce the connection portion. As the reinforcing resin, a thermosetting silicone resin, an epoxy resin, a room temperature curing silicone resin, or the like can be used. The solder connection strength is
The bow strength of solder is 5.75 kg/l1 at room temperature.
12, the tensile strength per electrode with a negative side of 0.5 mm is approximately 1.4 kg. In the case of a pin grid array substrate, approximately 100 electrodes can be formed on a 301111 square substrate, and the entire substrate has a strength of 140 kg or more. However, it is expected that a force of several kilograms per electrode will be applied due to biased force being applied when the module is inserted or removed.
本実施例に示される様に、基板間に封止樹脂５を充填し
硬化させることによって、接続部が補強され、特に偏っ
た力が加わった場合に応力を分散させ、特定電極に力が
集中することが避けられるなめ接続部の信頼性は非常に
高いものとなる。As shown in this example, by filling the sealing resin 5 between the substrates and curing it, the connection part is reinforced, and especially when uneven force is applied, the stress is dispersed and the force is concentrated on a specific electrode. The reliability of the lick joint is very high as it avoids the possibility of
例えば、比較的引張り強度の弱いシリコン系の樹脂の場
合でも、樹脂の引張り強度は２０〜３０ｋｇ ／ ｃｍ
２であり、３０１四方の基板に充填した場合１８０〜
２７０ ｋｇ以上の強度を有する様になり、通常の製品
の取り扱いでは強度に関する問題は無くなる。For example, even in the case of silicone resin, which has a relatively low tensile strength, the tensile strength of the resin is 20 to 30 kg/cm.
2, and when filled in a 301 square board, 180 ~
It now has a strength of over 270 kg, and there are no problems with strength during normal product handling.
第２図は本発明の第２の実施例を示す概略断面図である
。本実施例は、多層基板１とピングリッドアレー基板２
との間の周縁部のみに封止樹脂５ａを充填した構造を有
している。本実施例では、側基板間のはんだ接続部を完
全に封止することはできないが、機械的な補強という意
味では十分な効果が得られる。充填される樹脂は、対向
する二辺部分とする等、基板周縁の一部分であってもよ
い。FIG. 2 is a schematic sectional view showing a second embodiment of the invention. This embodiment consists of a multilayer substrate 1 and a pin grid array substrate 2.
It has a structure in which only the peripheral edge between the two is filled with sealing resin 5a. In this embodiment, although it is not possible to completely seal the solder connection between the side substrates, a sufficient effect can be obtained in terms of mechanical reinforcement. The resin to be filled may be a part of the periphery of the substrate, such as two opposing sides.
以上説明したように本発明は、電子部品を実装した多層
基板と、リードピンを配置したピングリッドアレー基板
とをはんだ接続し、多層基板とビングリッドアレー基板
との間の全域あるいは一部に樹脂を充填することによっ
て、はんだ接続部を機械的に補強し、特にその取板い時
に生じる接続不良等を防ぐことができ、またその接続部
は樹脂により封止されるために、腐食、酸化を防止し長
期の信頼性を得られるという効果がある。As explained above, the present invention connects a multilayer board on which electronic components are mounted and a pin grid array board on which lead pins are arranged, and applies resin to the entire area or part of the space between the multilayer board and the pin grid array board. By filling the solder joint, it can be mechanically reinforced and prevent connection failures that occur especially when removing the solder, and since the joint is sealed with resin, it prevents corrosion and oxidation. This has the effect of providing long-term reliability.
第１図は本発明の一実施例の概要を示す概略断面図、第
２図は本発明の第２の実施例を示す概略断面図、第ｐ図
および第４図は従来例の混成集積回路を示す概略断面図
である。
１・・・多層基板、２・・・ビングリッドアレー基板、
３・・・はんだ、４・・・リードピン、５・・・封止樹
脂、６・・・半導体素子、７・・・ボンディングワイヤ
、８・・・チップコート樹脂、９・・・チップ部品、１
０・・・ミニモールド部品、１１・・・第１パッド電極
群、１２・・・第２パッド電極群、１３・・・多層ビン
グリッドアレー基板。FIG. 1 is a schematic cross-sectional view showing an overview of an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing a second embodiment of the present invention, and FIGS. P and 4 are conventional hybrid integrated circuits. FIG. 1... Multilayer board, 2... Bin grid array board,
3... Solder, 4... Lead pin, 5... Sealing resin, 6... Semiconductor element, 7... Bonding wire, 8... Chip coat resin, 9... Chip component, 1
0...Mini mold component, 11...First pad electrode group, 12...Second pad electrode group, 13...Multilayer bin grid array substrate.
Claims (1)
に他への接続用の第１のパッド電極層群を設けた第１の
絶縁基板と、外部との接続用に規則的に配列されたリー
ドピン群を一面に設け、このリードピン群の各々と電気
的に接続された第２のパッド電極層群を他面に設けた第
２の絶縁基板とを備え、前記第１のパッド電極層群の各
パッドと前記第２のパッド電極層群の各パッドとがはん
だあるいは導電性樹脂により電気的に接続された混成集
積回路装置において、前記第１の絶縁基板と前記第２の
絶縁基板との間の全域あるいはその周縁部に封止樹脂が
充填されたことを特徴とする混成集積回路装置。A first insulating substrate with electronic components or semiconductor elements mounted on one side and a first pad electrode layer group for connection to other devices on the other side, and a first insulating substrate having electronic components or semiconductor elements mounted thereon and a first group of pad electrode layers arranged regularly for connection to the outside. a second insulating substrate provided with a group of lead pins on one surface and a second group of pad electrode layers electrically connected to each of the group of lead pins on the other surface; In a hybrid integrated circuit device in which each pad and each pad of the second pad electrode layer group are electrically connected by solder or conductive resin, between the first insulating substrate and the second insulating substrate. A hybrid integrated circuit device characterized in that the entire area or the periphery thereof is filled with a sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2248256A JPH04127460A (en) | 1990-09-18 | 1990-09-18 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2248256A JPH04127460A (en) | 1990-09-18 | 1990-09-18 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04127460A true JPH04127460A (en) | 1992-04-28 |
Family
ID=17175459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2248256A Pending JPH04127460A (en) | 1990-09-18 | 1990-09-18 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04127460A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8079600B2 (en) | 2005-08-30 | 2011-12-20 | Nok Corporation | Sealing structure |
| KR20160044011A (en) * | 2013-08-16 | 2016-04-22 | 어플라이드 머티어리얼스, 인코포레이티드 | Sealing groove methods for semiconductor equipment |
-
1990
- 1990-09-18 JP JP2248256A patent/JPH04127460A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8079600B2 (en) | 2005-08-30 | 2011-12-20 | Nok Corporation | Sealing structure |
| KR20160044011A (en) * | 2013-08-16 | 2016-04-22 | 어플라이드 머티어리얼스, 인코포레이티드 | Sealing groove methods for semiconductor equipment |
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