JPH04122023A - Method for manufacturing semiconductor wafers and methods for manufacturing semiconductor integrated circuit devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a manufacturing technology of semiconductor wafers and a manufacturing technology of semiconductor integrated circuit devices, and in particular, to a manufacturing technology of epitaxial wafers and an epitaxial growth layer (hereinafter referred to as a shrimp layer). The present invention relates to technology for forming semiconductor integrated circuit elements.

[Conventional technology]

An epitaxial wafer is a wafer in which a striped layer is formed by epitaxial growth on the main surface of a mirror-finished mirror wafer. The epitaxial growth method is capable of forming a single-crystal silicon (Sl) layer with good crystallinity on a semiconductor wafer, and also has the feature of being able to set the impurity concentration in the shrimp layer with very high precision, and is suitable for semiconductor integrated circuits. It is expected to be applied to device formation technology, and its practical application is progressing. In MOS-LSI, especially DRAM (
Application of epitaxial growth technology is seen as promising in the field of dynamic RAM. In this case, the use of a shrimp layer can reduce the parasitic capacitance of semiconductor integrated circuit elements by forming a high-resistance shrimp layer on a low-resistance semiconductor wafer, and reduce defective charges in the high-resistance shrimp layer. It is attracting attention because it is possible to suppress the leakage of charge from the capacitor due to defective charge by discharging it to the semiconductor wafer side of the resistor, and to make it difficult to be affected by alpha rays. As a result, in recent years, semiconductor integration ports
Epitaxial wafers are increasingly being adopted in the production of single-lids.

FIG. 6 shows a conventional epitaxial wafer manufacturing process. First, in an ingot growth step 51, a single crystal S1 ingot is formed by a pulling method or the like. continue,
After the single crystal S1 ingot is divided into a number of 81 blocks, an orientation flat surface is formed on the S1 blocks.

Next, in a slicing step 52, the Sl block is sliced into wafer shapes to form semiconductor wafers. Subsequently, the main surface or both surfaces of the semiconductor wafer are polished with abrasive grains or the like in order to remove processing distortion caused in the semiconductor wafer during slicing of the S1 block and to make the thickness of the semiconductor wafer constant. After that, the outer peripheral portion of the semiconductor wafer is ground.

This process is a process for setting the diameter of the semiconductor wafer, preventing the edges of the semiconductor wafer from chipping, and further reducing the occurrence of crowns during epitaxial growth, which will be described later.

Next, in an etching step 53, the entire surface of the semiconductor wafer is etched to a thickness of about several tens of micrometers in order to remove processing strain caused in the semiconductor wafer during polishing. Subsequently, a gettering layer is formed on the semiconductor wafer by a predetermined gettering method.

Next, in a mirror polishing step 54, the main surface or both surfaces of the semiconductor wafer are chemically and mechanically polished to form a mirror wafer. This treatment makes it possible to improve the surface flatness and cleanliness of the semiconductor wafer. Subsequently, in an epitaxial growth step 55, a shrimp layer made of single crystal S1 is formed on the main surface side of the semiconductor wafer to form an epitaxial wafer. After that, after going through steps such as final cleaning and inspection, wafer process step 5
Move to 6. However, the semiconductor wafer is also subjected to cleaning treatment after each treatment.

Regarding epitaxial growth technology, for example, Ohmsha Co., Ltd., published November 30, 1980, rLSI
It is described in Handbook JP P343-P358.

[Problem that the invention seeks to solve]

Incidentally, in recent years, in semiconductor wafers and road coverings, the integration of elements and the miniaturization of elements and wiring are progressing. Accordingly, from the viewpoint of improving pattern transfer precision, even stricter precision is required for the surface flatness of semiconductor wafers.

However, in the case of epitaxial wafers, for example, due to the way the gas flows during epitaxial growth or abnormalities in the gas flow, the growth thickness of the shrimp layer may become uneven, or a bulge (crown) may be formed on the outer periphery of the semiconductor wafer. Alternatively, when cleaning the main surface of a semiconductor wafer with HCf gas before epitaxial growth, the back side of the semiconductor wafer may be partially etched by HC1 gas, or a shrimp layer may grow on the back side of the semiconductor wafer during epitaxial growth. As a result, the surface flatness deteriorates, so there is a problem that it cannot be applied to the formation of semiconductor integrated circuit elements that require fine patterns.

The present invention has been made in view of the above problems, and its purpose is to provide a technique that can significantly improve the surface flatness of epitaxial wafers.

Another object of the present invention is to provide a technique capable of forming a semiconductor integrated circuit element requiring a fine pattern on an epitaxial wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the invention according to claim 1 provides a semiconductor wafer which is sliced from a single crystal ingot and subjected to an epitaxial growth process, and then mirror-polished at least the surface of the semiconductor wafer on which a shrimp layer is formed. This is a wafer manufacturing method.

The invention according to claim 4 provides a semiconductor wafer in which at least a surface of the semiconductor wafer on which a shrimp layer is formed is mirror-polished after performing an epitaxial growth treatment on a semiconductor wafer sliced from a single crystal ingot and not yet subjected to mirror-polishing treatment. This is a manufacturing method.

[Effect]

According to the invention described in claim 1, the thickness of the shrimp layer formed on the semiconductor wafer can be made uniform by performing mirror polishing treatment even after epitaxial growth, thereby improving the surface flatness of the epitaxial wafer. It becomes possible to improve the

According to the invention described in claim 4 above, by eliminating the mirror polishing step before epitaxial growth, it is possible to improve the surface flatness of the epitaxial wafer without increasing the number of manufacturing steps of the semiconductor wafer. Become.

〔Example〕

FIG. 1 is a process diagram showing the manufacturing process of a semiconductor wafer according to an embodiment of the present invention, FIGS. 2(a) to (C) are cross-sectional views of the semiconductor wafer during the manufacturing process of the semiconductor wafer, and FIG. 31!
l is a cross-sectional view of the epitaxial growth apparatus, FIG. 4(a) ~
(6) is a sectional view of the main part of the semiconductor wafer during the manufacturing process of the semiconductor integrated circuit lid.

As shown in FIG. 1, the semiconductor wafer manufacturing process of this embodiment includes an ingot growth process 1, a slicing process 2, an etching process 3, a mirror polishing process 4, an epitaxial growth process 5, and a mirror polishing process 6. have. The method for manufacturing a semiconductor wafer according to this embodiment will be explained below with reference to FIGS. 1 to 3.

First, an ingot growing process 1, a slicing process 2, an etching process 3, and a mirror polishing process 4 are performed in order according to a normal semiconductor wafer manufacturing method to form a semiconductor wafer 7 shown in FIG. 2(a). The semiconductor wafer 7 is made of, for example, p-type single crystal Si, and has a thickness of, for example, 500 to 700 μm.
It is about m. Further, the specific resistance of the semiconductor wafer 7 is set to be low, for example, about 0.020 cm.

Next, in the epitaxial growth step 5, the following steps are performed, for example.

First, the bell jar 10 of the epitaxial growth apparatus 9 shown in FIG. Subsequently, the bell jar 10 is returned to its original position, and an inert gas such as nitrogen (N2) gas is allowed to flow into the reaction chamber 12 for several minutes. Thereafter, a small amount of hydrogen (B2) gas or the like is flowed into the reaction chamber 12 together with N2 gas. Next, the flow rate of N2 gas is reduced and the flow rate of B2 gas is increased.

Subsequently, the N gas is turned off and the H gas is increased to the flow rate used for etching the oxide. Thereafter, power is applied to the high frequency work coil 13, and the semiconductor wafer 7 is
Heat to about ~1200°C. In this state, for example, 10
The oxide formed on the surface of the semiconductor wafer 7 is etched in H gas for about 20 minutes. Here, if HC
If etching with H etc. is desired, the required amount of H
CI gas is added to the main surface side of the semiconductor wafer 7, for example, to a temperature of 0.
After etching about 5 to 5 μm, the HCI gas is stopped.

Next, H2 gas is flowed for about 5 minutes, for example, to set the temperature of the semiconductor wafer 7, etc. Next, silicon tetrachloride (S
A Si crystal raw material gas such as +CC) gas and an impurity addition gas such as diborane (B2 H@) are introduced to grow p-type single crystal Si on the main surface of the semiconductor wafer 7. In addition, the Si crystal raw material gas is 5tCj! It is not limited to a and can be changed in various ways, such as trichlorosilane (SIHCj!i) and dichlorosilane (S
i Hz C1, ) or monosilane (SiHi). Thereafter, after forming a p-type single crystal Si layer with a desired thickness, the supply of the Si crystal raw material gas and the impurity addition gas is stopped. However, in order to remove all the 81 crystal raw material gas from inside the reaction chamber 12, the H gas is left flowing. Next, the power to the high-frequency work coil 13 is cut off, and the temperature of the semiconductor wafer 7 is returned to room temperature. Next, slowly add N2 gas and reduce N3 (. Then, N2
Turn off the gas, N.

Purge with gas for about 5 minutes and proceed to epitaxial growth step 5.
end. Note that epitaxial growth electrical manufacturing is not limited to the vertical device shown in FIG.

In the above manner, an epitaxial layer 8 made of p-type single crystal Si or the like is formed on the semiconductor wafer 7, as shown in FIG. 2 et al. The specific resistance of the shrimp layer 8 is, for example, several ΩCl11 to several tens of Ω.
cm, and is set to have a higher resistance than the semiconductor wafer 7.

Next, in this example, as shown in FIG. 1, a mirror polishing step 6 was provided after the epitaxial growth step 5. In the mirror polishing step 6, the semiconductor wafer is polished with a predetermined polishing cloth using, for example, a polishing agent in which colloidal silica is dispersed in a strong alkaline solution, that is, a combination of chemical polishing with an alkaline solution and mechanical polishing with silica. Mirror polish both sides of 7. However, only the shrimp layer 8 side of the semiconductor wafer 7 may be subjected to the mirror polishing process. This eliminates the deviation in the growth thickness of the shrimp layer 8 shown in FIG.
The unevenness on the back side of the semiconductor wafer 7 caused by the etching gas such as L is removed, and a semiconductor wafer 7 with excellent surface flatness is manufactured as shown in FIG. 2(C). Thereafter, after passing through a final cleaning process and an inspection process, the process moves to wafer process 14. Note that the semiconductor wafer 7 is also subjected to cleaning treatment after each processing step.

Next, in this embodiment, the shrimp layer 8 of the semiconductor wafer 7 is
The wafer process 14 will be explained with reference to FIGS. 4(a) to 4(d), taking as an example the case where a DRAM memory cell is formed.

First, for example, L OG OS < Local 0xid
Figure 4 (
As shown in a), a field insulating film 15 is formed in the element isolation region of the shrimp layer 8. At this time, field insulating film 1
A channel stopper region 16 in which p-type impurities are introduced is formed in the lower layer of the channel stopper region 5 .

Subsequently, as shown in FIG. 4(C), a selection M consisting of a gate insulating film 17, diffusion layers 18a and 18b, and a gate electrode 19 is formed in the element formation region surrounded by the field insulating film 15.
Form O3-FET20.

The diffusion layers 18a and 18b are doped with an n-type impurity such as phosphorus (P), and the selective MOS/FET 20
Forms the source and drain regions.

After that, the 41st! As shown in I(C), the diffusion layer 18a
A stacked capacitor 23 is formed by stacking an upper layer electrode 21b on a lower layer electrode 2Ia connected to the lower layer electrode 2Ia with a capacitive insulating film 22 interposed therebetween. That is, the selected MO3-
A memory cell 24 including an FET 20 and a stacked capacitor 23 is formed.

Next, as shown in the fourth Im(d), the semiconductor wafer 7
After depositing an insulating film 25 made of phosphosilicate glass (PSG) or the like on the main surface of the insulating film 25, a contact hole 26 reaching the shrimp layer 8 is formed in the insulating film 25.

Subsequently, an alloy layer made of an Aβ-3i-Cu alloy is deposited on the insulating film 25, and then the alloy layer is patterned by photolithography to form a bit line 27, thereby forming a DRAM.

As described above, according to this embodiment, by mirror polishing both sides of the semiconductor wafer 7 after the epitaxial growth step 5, the thickness of the shrimp layer 8 formed on the semiconductor wafer 7 can be made uniform, and Since the unevenness on the back side of the semiconductor wafer 7 formed during epitaxial growth can be removed, it is possible to significantly improve the surface flatness of the semiconductor wafer 7 after the epitaxial growth process. As a result, it is possible to prevent exposure defects caused by the surface flatness of the semiconductor wafer 7 after the epitaxial growth process, so that the memory cells 24 that require fine patterns can be removed from the shrimp layer 8 without causing a significant decrease in yield. It becomes possible to form

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, in the above embodiment, a case has been described in which epitaxial growth is performed after performing a mirror polishing process on a semiconductor wafer after a slicing process, but the invention is not limited to this, and for example, as shown in FIG. , the mirror polishing process before epitaxial growth may be deleted. In this case, the mirror polishing step before epitaxial growth can be omitted, making it possible to improve the surface flatness of the epitaxial wafer without increasing the number of semiconductor wafer manufacturing steps.

Further, in the above embodiment, a case was explained in which a DRAM memory cell consisting of a selection MOS-FET and a capacitor was formed on the shrimp layer, but this is not limited to this and various modifications are possible. For example, a fine pattern can be formed. The required bipolar integrated circuit elements and charge-coupled devices (Cha
rge Coupled Devices = CC
D) etc. may be formed in the shrimp layer. However, when forming a CCD on the shrimp layer, the resistance values of the shrimp layer and the semiconductor wafer are set to be the same.

Further, in the above embodiments, the case where the DRAM memory cell is a stacked capacitor cell has been described, but the invention is not limited to this and various modifications can be made. For example, it may be a Brenna type capacitor cell or a trench capacitor cell. .

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

(1), that is, according to the invention set forth in claim 1, by performing mirror polishing treatment after epitaxial growth, the thickness of the shrimp layer formed on the semiconductor wafer can be made uniform; It becomes possible to significantly improve surface flatness. As a result, it becomes possible to form semiconductor integrated circuit elements such as MOS-FET, C, CD, etc., which require fine patterns, on epitaxial wafers. .

(2) According to the invention set forth in claim 4, by eliminating the mirror polishing treatment before epitaxial growth, it is possible to improve the surface flatness of the epitaxial wafer without increasing the number of manufacturing steps of the semiconductor wafer. It becomes possible.

[Brief explanation of the drawing]

'M1 is a process diagram showing the manufacturing process of a semiconductor wafer according to an embodiment of the present invention, FIGS. 2(a) to (C) are cross-sectional views of the semiconductor wafer during the manufacturing process of the semiconductor wafer, and FIG. Cross-sectional view of the epitaxial growth apparatus, Fig. 4 (a
) to (6) are sectional views of main parts of a semiconductor wafer during the manufacturing process of a semiconductor integrated circuit device, FIG. 5 is a process diagram showing a manufacturing process of a semiconductor wafer according to another embodiment of the present invention, and FIG. FIG. 2 is a process diagram showing a conventional semiconductor wafer manufacturing process. 1... Ingot growing process, 2... Slicing process,
3... Etching process, 4... Mirror polishing process, 5...
...Epitaxial growth process, 6...Mirror polishing process,
7... Semiconductor wafer, 8... Shrimp layer, 8a... Crown, 8b... Shrimp film, 9... Epitaxial growth device, 10... Belljar, 11... Support stand, 12
...Reaction chamber, 13...High frequency work coil, 14.
...Wafer process, 15...Field insulating film, 1
6... Channel stopper region, 17... Gate insulating film, 18a, 18b... Diffusion layer, 19... Gate electrode, 20... Select MO3 FET, 21a... Lower layer electrode, 21b... ... Upper layer electrode, 22... Capacitive insulating film,
23... Stacked capacitor, 24... Memory cell, 25... Insulating film, 26... Contact hole,
27... Bit line, 51... Ingot growth process,
52... Slicing process, 53... Etching process,
54...Mirror polishing process, 55...Epitaxial growth process, 56...Wafer flossing. Agent Patent Attorney Daiwa Tsutsui 2nd Figure 7: Semiconductor wafer a 8: Shrimp layer diagram a

Claims (1)

[Claims] 1. A semiconductor wafer sliced from a single crystal ingot and subjected to mirror polishing is subjected to epitaxial growth treatment, and then at least the surface of the semiconductor wafer on which the epitaxial growth layer is formed is mirror polished. A method for manufacturing a semiconductor wafer. 2. MOS・F in the epitaxial growth layer according to claim 1
A method of manufacturing a semiconductor integrated circuit device, comprising forming an ET. 3. A method for manufacturing a semiconductor integrated circuit device, comprising forming a charge-coupled device in the epitaxial growth layer according to claim 1. 4. Manufacture of a semiconductor wafer characterized by subjecting a semiconductor wafer sliced from a single crystal ingot and undergoing mirror polishing to an epitaxial growth treatment, and then mirror polishing at least the surface of the semiconductor wafer on which an epitaxial growth layer is formed. Method.