JPH04109661A - Layout structure for integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a wasteful region in an entire block disposing region and to enhance integration by aligning the widths of blocks aligned in parallel in divided disposing regions, and disposing parallel block groups of the region in parallel with each other. CONSTITUTION:A block disposing region 1 is partitioned to rectangular first and second divided disposing regions 1A, 1B by a linear partition line 1c parallel to the vertical side line 1a of the region 1. The widths L1 of blocks 2-4 of first group disposed in parallel on the region 1A are aligned, and the widths L2 of the blocks 5-7 of a first group disposed in parallel on the region 1B are aligned. The blocks 2-4 of the first group and the blocks 5-7 of the second group are disposed in parallel with one another. Thus, a wasteful range of the region 1 is sufficiently reduced to enhance integration.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a layout structure of a plurality of blocks constituting an integrated circuit.

<Prior Art> FIG. 3 shows a layout structure of a plurality of automatically placed and routed blocks in a conventional integrated circuit.

In FIG. 3, numeral 1 indicates a block placement area in which a plurality of blocks are to be automatically placed and routed, 2 to 7 indicate each block that has been automatically placed and routed, and 8 indicates a cell in each block 2 to 7.

In this conventional integrated circuit layout structure, the dimensions of the blocks 2 to 7 are different, and the individual blocks 2 to 7 are arranged in the block arrangement 6N area 1 regardless of the direction of each cell 8. It had become something like that.

<Problems to be Solved by the Invention> The layout structure of the conventional integrated circuit is configured as described above, and since the dimensions of each block 2 to 7 are uneven, there is a lot of wasted area and the degree of integration is low. In addition, since the directions of the cells 8 are not aligned, it is difficult to conduct power supply/GND wiring (not shown) between blocks, and this causes a decrease in the productivity of integrated circuits. This resulted in an increase in costs.

This invention was devised to solve the above-mentioned problems, and by improving the degree of integration and making power supply/GND wiring easier, it improves productivity and reduces costs. The purpose is to obtain an achievable integrated circuit layout structure.

Means for Solving the Problems> The layout structure of an integrated circuit according to the present invention is configured as follows.

The block arrangement area is divided into two rectangular divided arrangement areas, a first and a second rectangular arrangement area, by a straight partition line.

The plurality of blocks in the first divided arrangement area are arranged in parallel along the direction of the partition line, with each cell length direction being perpendicular to the partition line. The widths of the blocks in the first divided arrangement area along the cell length direction are equal to each other. Furthermore, the side lines of each of these blocks are arranged on the same straight line parallel to the partition line.

The plurality of blocks in the second divided arrangement area are arranged in parallel along the direction of the partition line, with each cell length direction being parallel to the partition line. The widths of the blocks in the second divided arrangement area in the direction perpendicular to the cell length direction are equal to each other. Furthermore, the side lines of each of these blocks are arranged on the same straight line parallel to the partition line.

<Actions> The effects of the above configuration of the layout structure of an integrated circuit according to the present invention are as follows.

In both the first divided placement area and the second divided placement area, the blocks arranged in parallel have the same width, and the widths of the blocks in the first divided placement area and the blocks in the second divided placement area are the same. Since the plurality of blocks in the second divided arrangement area are arranged parallel to each other, there is very little wasted area and the degree of integration is high.

In addition, since the cell length directions of each block in each subdivision placement area are parallel, and the cell length directions are at right angles to each other in the first division placement area and the second division placement area, , power supply/GND wiring is easy to perform.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a plan view showing the layout structure of an integrated circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a block placement area in which all blocks in the integrated circuit are to be placed and routed, and this block placement area 1 is a vertical side line 1 of the block placement area 1.
It is divided into a first divided arrangement area IA and a second divided arrangement area IB each having a rectangular shape with a straight partition line IC parallel to a.

2.3.4 is the first group of blocks automatically placed and routed in the first divided placement area IA, and 5 and 6.7 are the second group of blocks automatically placed and routed in the second divided placement area IB. be.

8 is a cell in each block 2-7.

The first group of blocks 2.3.4 arranged in the first divided arrangement area IA are such that the length direction of each cell 8 is parallel to each other and relative to the horizontal side line 1b of the block arrangement area 1. are also parallel.

First group of blocks 2. 3. 4 are configured such that the widths L1 along the length direction of the cells 8 are equal to each other.

The first group of blocks 2, 3.4 are arranged in parallel along the direction perpendicular to the cell length direction, that is, along the direction of the partition line 1c.

In the second group of blocks 5.6.7 arranged in the second divided arrangement area IB, extension lines in the length direction of the respective cells 8 are parallel to each other and parallel to the partition line IC. ing. That is, the length direction of the cell 8 in the second group of blocks 5.6.7 is the same as that of the first group of blocks 2, 3, .
It is perpendicular to the length direction of the cell 8 in 4.

The blocks 5.6.7 of the second group are configured to have the same width L2 in the direction perpendicular to the length direction of the cell 8, that is, in the direction of the lateral side line 1b of the block arrangement area 1. . Note that the second group of blocks 5, 6 .
The direction of the radius L2 of block 7 is the same as the direction of the radius L1 of blocks 2, 3.4 of the first group.

The blocks 5.6.7 of the second group are arranged in parallel along the cell length direction, that is, the direction of the longitudinal side line 1a of the block arrangement region l.

The parallel direction of the blocks 2, 3.4 of the first group and the parallel direction of the blocks 5.6.7 of the second group are parallel. That is, the first divided placement area IA and the second divided placement area I
In B, the parallel directions of the blocks are parallel to each other, but
The cell length directions are perpendicular to each other.

The outer side lines 2a, 3a, 4a of the first group of blocks 2.3.4 lie on the same straight line, and the inner side lines 2b, 3b, 4b also lie on the same straight line.

The inner side lines 5a, 6a, 7a of the second group of blocks 5.6.7 lie on the same straight line, and the outer side lines 5b, 6b, 7b also lie on the same straight line.

A line segment connecting the inner side lines 2b, 3b, 4b of blocks 2, 3.4 of the first group, and block 5.4 of the second group.
The line segments connecting the inner side lines 5a, 6a, and 7a in 6.7 are parallel to each other, and the interval between the two lines is constant over the entire length.

First group of blocks 2. 3. The line segment connecting the outer side lines 2b, 3b, and 4b in block placement area 1 is parallel to the left vertical side line 1a of the block arrangement area 1, and the interval between them is constant over the entire length. .

Similarly, the line segment connecting the outer side lines 5b, 6b, 7b of the blocks 5, 6.7 of the second group and the right vertical side line 1d of the block arrangement area 1 are parallel to each other, and both The spacing between them is constant over the entire length.

The blocks 2 and 3.40 of the first group arranged in parallel in the first divided arrangement area IA are aligned, and the blocks 5 of the second group arranged in parallel also in the second divided arrangement area IB.
．． 6. The width L2 of 7 is aligned, and the blocks 2 of the first group,
Since block 3.4 and block 5.6.7 of the second group are arranged parallel to each other, the wasted area in block arrangement area 1 is sufficiently reduced, and the degree of integration is higher than in the conventional example. .

FIG. 2 shows a plurality of blocks 2 arranged as shown in FIG.
Integrated circuit 1 with power supply/GND wiring 9 connected to ~7
Indicates 0.

The tfi-GND wiring 9 extends around the four circumferences of the block arrangement area 1,
Since wiring can be performed linearly along the partition line IC between the first divided placement area IA and the second divided placement area IB, the wiring can be easily performed.

Note that in the above embodiment, each block is automatically placed and routed, but of course it may be placed and routed manually.

<Effects of the Invention> As described above, according to the present invention, the widths of the plurality of blocks arranged in parallel in both the first divided placement area and the second divided placement area are made the same, and both the divided placement areas Since the parallel block groups in the arrangement area are made parallel to each other, the wasted area in the entire block arrangement area is sufficiently reduced, and the degree of integration can be increased.

In addition, the distance between the plurality of blocks in the first divided placement area and the plurality of blocks in the second divided placement area, and the distance between each divided placement area and the side line of the block placement area are determined by straight lines of a constant width. In addition, the cell length direction of each block in both side placement areas is parallel to each other, and the cell length direction in the first divided placement area and the cell length in the second divided placement area are parallel to each other. By making the length directions perpendicular to each other, tf! X-GND wiring can be facilitated.

By improving the degree of integration and making power supply/GND wiring easier, it is possible to improve the productivity of integrated circuits, and
Cost reduction can be achieved.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 relate to one embodiment of the present invention.
The figure is a layout diagram of blocks that are the constituent elements of an integrated circuit, and FIG. 2 is a layout diagram with power supply and GND wiring completed. FIG. 3 shows the layout of blocks in a conventional integrated circuit. In Figure 8, 1 is the block placement area, IA is the first divided placement area, IB is the second divided placement area, lc is the partition line,
2.3.4 is the first group of blocks, 2a, 3a, 4a are the side lines of the first group of blocks, 5, 6.7 are the second group of blocks, 5a, 6a6a are the side lines of the second group of blocks 8 is a cell, 9 is a power supply/GND wiring, and 10 is an integrated circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The block placement area is divided into two rectangular first and second divided placement areas with straight partition lines, and the blocks in the first divided placement area are arranged in the cell length direction. are arranged in parallel along the direction of the partition line, with the blocks being perpendicular to the partition line, and the widths of each block along the cell length direction are equal to each other, and the side line of each block is are located on the same straight line parallel to the partition line, and the plurality of blocks in the second divided arrangement area are arranged such that the length direction of each cell is parallel to the partition line, The blocks are arranged in parallel along the direction of the partition line, the widths of each block in the direction perpendicular to the cell length direction are equal to each other, and the side lines of each block are on the same straight line parallel to the partition line. A layout structure of an integrated circuit characterized by being arranged and configured in a state located at .