JP2508386B2 - Layout structure of integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout structure of a plurality of blocks constituting an integrated circuit.

<Prior Art> FIG. 3 shows a layout structure of a plurality of blocks automatically arranged and wired in a conventional integrated circuit.

In FIG. 3, reference numeral 1 denotes a block arrangement area in which a plurality of blocks are to be automatically arranged and wired, 2 to 7 are each automatically arranged and wired, and 8 is a cell in each of the blocks 2 to 7.

In this conventional integrated circuit layout structure, the blocks 2 to 7 have different sizes, and the individual blocks 2 to 7 are arranged in the block arrangement region 1 regardless of the direction of the cells 8. It was a thing.

<Problems to be Solved by the Invention> The conventional layout structure of an integrated circuit is configured as described above, and the blocks 2 to 7 are not uniform in size, so that there are many useless areas and the degree of integration is low. In addition, the direction of the cells 8 is not uniform, which makes it difficult to connect the power supply / GND wiring (not shown) between the blocks, which reduces the productivity of the integrated circuit. And increased costs.

The present invention was devised to solve the above-mentioned problems, and improves productivity and simplifies power supply / GND wiring to improve productivity and reduce cost. It is an object to obtain an achievable integrated circuit layout structure.

<Means for Solving the Problems> The layout structure of the integrated circuit according to the present invention is configured as follows.

The block arrangement area is divided into two first and second rectangular divided arrangement areas with a straight partition line.

The plurality of blocks in the first divided arrangement area are arranged in parallel along the direction of the partition line with their cell length directions being at right angles to the partition line. The widths of the respective blocks in the first divided arrangement area along the cell length direction are equal to each other. Further, the side lines of each of these blocks are arranged so as to be located on the same straight line parallel to the partition line.

The plurality of blocks in the second divided arrangement area are arranged in parallel along the direction of the partition line, with their cell length directions parallel to the partition line. The widths of the respective blocks of the second divided arrangement area in the direction perpendicular to the cell length direction are equal to each other. Further, the side lines of each of these blocks are arranged so as to be located on the same straight line parallel to the partition line.

<Operation> The operation of the above-described layout structure of the integrated circuit according to the present invention is as follows.

In both the first divided arrangement area and the second divided arrangement area, the plurality of blocks arranged in parallel have the same width, and moreover, the plurality of blocks in the first divided arrangement area have the same width. Since the plurality of blocks in the two divided arrangement areas are arranged in parallel with each other, the area that is wasted is extremely small and the degree of integration is high.

Further, since the cell length directions of the respective blocks of the two divided arrangement areas are parallel to each other, and the cell length directions of the first divided arrangement area and the second divided arrangement area are perpendicular to each other. The power and GND wiring is easy to do.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a layout structure of an integrated circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a block arrangement area in which all blocks in the integrated circuit are to be arranged and wired. This block arrangement area 1 is a vertical side surface line of the block arrangement area 1.
A first dividing arrangement area 1A and a second dividing arrangement area 1B each having a rectangular shape with a straight partition line 1c parallel to 1a.
It is divided into and.

2,3,4 are first group blocks automatically placed and routed in the first divided placement area 1A, and 5,6,7 are second group blocks automatically placed and routed in the second divided placement area 1B. is there. Reference numeral 8 is a cell in each block 2-7.

Blocks of the first group arranged in the first divided arrangement area 1A
The cells 2, 8 are parallel to each other in the longitudinal direction of the cells 8 and also to the lateral side line 1b of the block arrangement region 1. The blocks 2, 3, 4 of the first group are configured such that the widths L1 along the length direction of the cells 8 are equal to each other.

The blocks 2, 3, 4 of the first group are arranged in parallel along a direction perpendicular to the cell length direction, that is, along the direction of the partition line 1c.

The second group of blocks arranged in the second divided arrangement area 1B
5, 6 and 7 have extension lines in the longitudinal direction of the cells 8 which are parallel to each other and to the partition line 1c. That is, the length direction of the cells 8 in the blocks 5, 6, 7 of the second group is perpendicular to the length direction of the cells 8 in the blocks 2, 3, 4 of the first group.

The blocks 5, 6 and 7 of the second group are in the direction perpendicular to the length direction of the cell 8, that is, the lateral side line of the block arrangement area 1.
The widths L2 along the direction of 1b are equal to each other. The direction of the width L2 of the blocks 5, 6, 7 of the second group is the same as the direction of the width L1 of the blocks 2, 3, 4 of the first group.

The blocks 5, 6, 7 of the second group are arranged in parallel along the cell length direction, that is, in the direction of the vertical side surface line 1a of the block arrangement region 1.

The parallel direction of the blocks 2, 3, 4 of the first group and the parallel direction of the blocks 5, 6, 7 of the second group are parallel. That is,
In the first divided arrangement area 1A and the second divided arrangement area 1B,
The blocks are parallel to each other, but the cell lengths are perpendicular to each other.

Outer lateral line 2a in blocks 2, 3 and 4 of the first group,
3a and 4a are located on the same straight line, and inner side lines 2b, 3b and 4
b is also located on the same straight line.

Inner lateral line 5a in the second group of blocks 5, 6, 7
6a and 7a are located on the same straight line, and the outer lateral lines 5b, 6b and 7a
b is also located on the same straight line.

Inner lateral line 2b in blocks 2, 3, 4 of the first group,
The line segment connecting 3b, 4b and the line segment connecting the inner side lines 5a, 6a, 7a in the blocks 5, 6, 7 of the second group are parallel to each other, and the distance between both line segments is the total length. It has been constant throughout.

The outer lateral line 2b in the blocks 2, 3 and 4 of the first group,
The line segment connecting 3b and 4b and the vertical side surface line 1a on the left side of the block arrangement region 1 are parallel to each other, and the interval between them is constant over the entire length.

Similarly, the line segment connecting the outer side surface lines 5b, 6b, 7b in the blocks 5, 6, 7 of the second group and the vertical side surface line 1d on the right side of the block arrangement area 1 are parallel to each other. The interval between them is constant over the entire length.

The first group of blocks 2, 3, 4 arranged in parallel in the first divided arrangement area 1A have the same width L1 and the second divided arrangement area 1B
Width L of the blocks 5, 6, 7 of the second group arranged in parallel in
Since 2 are arranged and the blocks 2, 3, 4 of the first group and the blocks 5, 6, 7 of the second group are arranged in parallel with each other, the wasteful range in the block arrangement area 1 is sufficiently reduced. ,
The degree of integration is higher than that of the conventional example.

FIG. 2 shows an integrated circuit 10 in which a power supply / GND wiring 9 is connected to a plurality of blocks 2 to 7 arranged as shown in FIG.
Indicates.

The power / GND wiring 9 can be wired in a straight line along the partition line 1c between the first divided arrangement area 1A and the second divided arrangement area 1B on the four sides of the block arrangement area 1. Can be done.

In the above embodiment, each block is automatically placed and routed, but of course, it may be manually placed and routed.

<Effects of the Invention> As described above, according to the present invention, the widths of the plurality of blocks arranged in parallel in the first divided arrangement region and the second divided arrangement region are equalized, and both blocks are divided. Since the parallel block groups in the placement area are parallel to each other,
The wasted area is sufficiently reduced in the entire block arrangement area, and the degree of integration can be increased.

In addition, a plurality of blocks in the first divided arrangement area
The distance between the plurality of blocks in the divided arrangement area and the distance between each divided arrangement area and the side line of the block arrangement area are linear intervals of a constant width, and each block in both divided arrangement areas Cell length directions are parallel to each other, and the cell length direction in the first divided arrangement region and the second
By making the cell length direction in the divided arrangement area of each other at right angles to each other, the power supply / GND wiring can be facilitated.

And, by improving the degree of integration and facilitating power supply / GND wiring, the productivity of integrated circuits can be improved, and
Cost reduction can be achieved.

[Brief description of drawings]

1 and 2 relate to an embodiment of the present invention.
FIG. 1 is a layout diagram of a block which is a constituent element of the integrated circuit, and FIG. 2 is a layout diagram in a state where power supply / GND wiring is performed. FIG. 3 is a layout diagram of blocks in a conventional integrated circuit. In the figure, 1 is a block arrangement area, 1A is a first divided arrangement area, 1B is a second divided arrangement area, 1c is a partition line, 2, 3,
4 is the block of the first group, 2a, 3a, 4a is the side line of the block of the first group, 5, 6, 7 is the block of the second group, 5a, 6a, 6a is the side line of the block of the second group, 8 is a cell, 9 is a power supply / GN
D wiring, 10 is an integrated circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A block arrangement area is divided into two first and second rectangular divided arrangement areas with straight partition lines, and a plurality of blocks in the first divided arrangement area have respective cell lengths. In a state in which the depth direction is perpendicular to the partition line, the blocks are arranged in parallel along the direction of the partition line, and the widths along the cell length direction of each block are equal to each other, and A state in which the side lines are arranged on the same straight line parallel to the partition line, and the plurality of blocks in the second divided layout region have cell length directions parallel to the partition line. In addition, the blocks are arranged in parallel along the direction of the partition line, and the widths along the direction perpendicular to the cell length direction of each block are equal to each other. Ku, and the layout structure of the integrated circuit side line of each block, characterized in that it is an arrangement in a state positioned collinear on a line parallel to the partition line.