JPH04102296A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To permit access to an address even when the address being rewritten exists by executing the erasure/write of data held with a latch means as write data by an instruction execution means. CONSTITUTION:Memory control circuits 18-1 to 18-4 execute the erasure/write operation of the data held with latch circuits 17-1 to 17-4 with corresponding addresses for storage parts 10-1 to 10-4 with corresponding addresses for prescribed time as the write data replying to an erasure/write operation command from a memory control circuit 11. Therefore, an erasure/write instruction accepted by the circuit 11 is executed on all addresses A1-A4 by the circuits 17-1 to 17-4 and the circuits 18-1 to 18-4 with individual address in spite of the common circuit 11 and a data line 15, and the circuit 11 and the line 15 are controlled by one erasure/write instruction only when the instruction is accepted, and the circuit 11 can accept a following instruction after accepting one instruction.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device using electrically rewritable non-volatile memory cells, particularly to an EEF ROM (Electrical Era
sable and Prograsnable Mem
ory)l related.

(Prior art) Since EEFROM can electrically erase and rewrite data, data can be erased and rewritten on the board of the system in which it is installed, and it is non-volatile.
Since it has the advantage of retaining memory data even without supplying a power supply voltage, it is expected to be used as a nonvolatile RAM.

By the way, the read/write control for this EEFROM can be applied to the conventional volatile memory. However, in this case, read control can be achieved using conventional volatile memory, but write control takes several milliseconds, which is the time required to rewrite the EEFROM, and writing can only be done in real time. A control system for controlling the write time is added to the write control system for volatile memory.

FIG. 3 is a block diagram showing the configuration of a conventional EEFROM and its read/write control device.

Here, in order to simplify the illustration and explanation, a memory configuration of four addresses is shown.

In this figure, 1-1 to 1-4 are data storage units for each address, 2 is a memory control circuit, 3 is a timer, 4 is a data line, 5 is an address line, 6 is an R (read) control line, and 7 is a E/W (erase/write) control lines, 8-1 to 8-4 are operation control lines, and 9 is a timer line.

The data line 4 is for exchanging data with an access control device (not shown), and the address line 5 includes:
The specified address from this access control device is input,
A read control command is input from the access control device to the R control line 6, and a write control command is input from the access control device to the E/W control licensee.

Each of the storage units 1-1 to 1-4 is composed of, for example, 8-bit cells.

When a read control command is input to the R control line 6, the memory control circuit 2 selects one of the operation control lines 8-1 to 8-4 for the address specified by the address data from the address line 5. A read control signal is generated through a control line corresponding to a designated address. Then,
Among the storage units 1-1 to 1-4, data in the storage unit that receives the read control signal is sent to the data line 4. The access control device captures the data in real time.

Further, when the E/W control control license included control command is input, the memory control circuit 2 sends the operation control lines 8-1 to 8-4 to the address specified by the address data from the address line 5. A write control signal is generated through a control line corresponding to the specified address. Then, the data on the data line 4 is written into the cell receiving the write control signal among the storage units 1-1 to 1-4. At this time, if this write operation is an erase, the FF
H data is present on data line 4.

When the write operation is a rewrite, there are 8 bits of data to be written to all bits of the storage section 1.

The timer 3 is for controlling the time required for this erasing/rewriting, and outputs a clock signal of a constant cycle.

The clock signal from this timer 3 is given to the memory control circuit 2 through the timer line 9, and the memory control circuit 2 counts the time since receiving the write control signal based on this clock signal, and performs a predetermined write operation. When the elapsed time has elapsed, a write end signal is output to the access control device. The access control device terminates the access input operation in response to this write end signal, and terminates sending signals to the address line 5 and data line 4.

In this way, by incorporating a write time control system into the conventional control system for volatile memory, it is possible to electrically achieve erase/rewrite control.

However, when considering the use of such a conventional semiconductor memory device as a nonvolatile RAM, there are the following difficulties.

In other words, when accesses are continuous, subsequent processing becomes stagnant because erasing and rewriting take a long time. According to the read/write control device described above, while one address is being accessed, access to that address and other addresses is impossible. If the access is a read, similar to volatile memory,
It is possible to proceed to the next process with a short waiting time, or if the access is a write, a long waiting time of several milliseconds as described above will occur before proceeding to the next process.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor memory device described above, although electrical erasing/rewriting control is possible, due to the long write processing time, the RAM There was a problem that it was difficult to utilize it as a.

The present invention has been made in view of the above-mentioned problems of the prior art, and from the viewpoint of how to enable access at a speed equivalent to that of conventional volatile memory. The object of the present invention is to provide a semiconductor memory device using electrically rewritable non-volatile memory cells that allows access to that address and other addresses even if the address is currently being rewritten. .

[Structure of the invention]

(Means for Solving the Problems) A semiconductor memory device of the present invention according to claim 1 is provided with a storage section consisting of non-volatile memory cells that can be electrically erased and rewritten, an erase/write command receiving means that receives the erase/write command and outputs an erase/write operation command to the specified address; a latch means for latching, and an erase/write operation provided corresponding to each address for performing an erase/write operation for a predetermined time on the storage section using the data of the latch means as write data in response to the erase/write operation command. and write operation execution means.

The semiconductor memory device of the present invention according to claim 2 includes a read command receiving means for receiving a read command and outputting a read operation command to the specified address, and a read command receiving means provided corresponding to each address, and a read command receiving means for receiving a read command and outputting a read operation command to the specified address. In response, when the erase/write operation is being executed, the data in the latch means is used as read data, and when the erase/write operation is not being executed, the data in the storage section is sent as read data to the data transmission path. equipped with the means.

The semiconductor memory device of the present invention according to claim 3 includes a control counting means that starts a counting operation for a predetermined time in response to an erase/write operation command, and writing data in the latch means only during the counting operation of the control counting means. Erase/write execution means that executes an erase/write operation to the storage unit as data, and a control counting means that resets the counting operation of the control counting means when receiving the erase/write operation command while the control counting means is in the counting operation. and reset means.

(Function) According to the present invention as set forth in claim 1, the instruction received by the erase/write instruction receiving means is processed by the execution means provided corresponding to each address, and the write data is sent to the latch corresponding to each address. Since the data held in the latch means is held in the latch means and the instruction execution means erases/writes the data held in the latch means as write data, this instruction is executed by the command receiving means and data which are a common unit for all addresses. Regardless of the transmission path, this is performed by the latch means and erase/write execution means, which are individual units for each address, so the command receiving means and data transmission path, which are common hardware for all addresses, are required. The erasure/write command of the command is controlled only when the command is accepted.
During erasing/writing, it can be opened and subsequent commands can be accepted.

According to the present invention as set forth in claim 2, when a read command is received, the data in the latch means is used as read data when the rewriting operation is being executed at the address, and the data in the storage unit is read when the rewriting operation is not in progress. Since the read data sending means for sending the data as read data to the data transmission path is provided, even if the address to be read is being erased/written, the address can be accessed for reading.

According to the present invention as set forth in claim 3, when the address where the erase/write is being executed receives a new erase/write command,
The counting operation of the control counting means that controls the erase/write operation time is reset, and new data is erased/written from the beginning again.
Even if the address to be written is being erased/written, the address can be accessed for erasing/writing.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows an EEFROM according to an embodiment of the present invention, and here a 4-address configuration is shown.

In this figure, Al-A4 is an address, 10-1 to 1
0-4 are storage units for each address A1 to A4. The storage units 10-1 to 10-4 are electrically erasable/rewritable 8
It is made up of 1-bit non-volatile cells.

11 is a memory control circuit as erase/write command receiving means and read command receiving means; 12 is an R control line; 13
is an E/W control line, 14 is an address line, and 15 is a data line.

A read command from an access control device (not shown) is input to the R control line 12, an erase/write command from the same device is input to the E/W control line 13, and a specified address from the same device is input to the address line 14. be done. data line 1
5 contains write data from the same device and each address A1~
The read data from A4 is sent out respectively.

The memory control circuit 11 is configured so that the level of the R control line 12 is “
When the level of the E/W control line 13 becomes ``1'', this is determined to be a read command, and when the level of the E/W control line 13 becomes ``1'', this is determined to be an erase/write command. Upon receiving the command, it issues a read or erase/write operation command to the address specified on the address line 14 and completes the operation.

These memory control circuit 11, R control line 12, E/W
The control line 13, address line 14, and data line 15 form a common unit for all addresses A1 to A4.

16-1 to 16-4 are operation control lines corresponding to each address. The memory control circuit 11 sends read and erase/write operation commands through operation control lines 16-1 to 16-4 corresponding to each address A1 to A4.

17-1 to 17-4 are latch circuits corresponding to each address. The latch circuits 17-1 to 17-4 latch data on the data line 15 in response to an erase/write operation command to the corresponding address.

Reference numerals 18-1 to 18-4 are memory control circuits corresponding to each address serving as erase/write command execution means, and 19 is a timer. In response to an erase/write operation command from the memory control circuit 11, the memory control circuits 18-1 to 18-4 write the data held in the latch circuits 17-1 to 17-4 at the corresponding address as write data. , has a function of executing erasing/writing operations for a predetermined time on the storage units 10-1 to 10-4 at corresponding addresses.

Therefore, the erase/write data received by the memory control circuit 11 is
The write command is executed by the latch circuits 17-1 to 17-4 and the memory control circuit, which are units for each address individually, regardless of the memory control circuit 11 and data line 15, which are a common unit for all addresses A1 to A4. 18-1~18
-4, the memory control circuit 11 and data line 15 are controlled by the erase/write command of - only when the command is accepted, and can be opened during erasure/write. Then, after the - command is accepted, subsequent commands can be accepted.

The erase/write time in the memory control circuits 18-1 to 18-4 is controlled by counting the edges of the clock signal from the timer 19.

This counting operation is reset in response to an erase/write operation command to that address. Therefore, when a certain address receives a new erase/write command during an erase/write operation, the count operation is reset and the write operation is performed again with new data from the beginning. Even if an address is being erased/written, it is possible to perform erase/write access to that address.

Furthermore, in response to a read operation command from the memory control circuit 11, the memory control circuits 18-1 to 18-4 hold the address in the latch circuits 17-1 to 17-4 when the address is being erased/written. The data that has been written is read data, and if no erase/write operation is in progress,
It also has a function of reading data from the corresponding storage units 10-1 to 10-4 and sending it out to the data line 15 as read data. Thereby, even if the address to be read is being erased/written, it is possible to perform read access to that address.

Next, FIG. 2 is a detailed diagram of the units for each address A1 to A4. That is, each address A1 to A4 is provided with a unit surrounded by a broken line, and has an 8-bit configuration.

In this figure, MO, Ml, . . . , M7 are transistors forming memory cells, and are electrically erasable/writable transistors such as F A M OS (Floating
gate Avalanche 1 injection
It is a p-channel type (MOS) type. These transistors MO to M7 correspond to the storage section 10 described above. DO~
D7 is a data line corresponding to each bit, and constitutes the data line 15.

r is a read operation control line, and ω is an erase/write control line, which correspond to the operation control line 16. The memory control circuit 11 issues a read operation command by raising the level of the control line r and generating a one-shot pulse, and also issues an erase operation command by raising the level of the control line ω and generating a one-shot pulse. / Issue a write operation command.

LO to L7 are latch circuits corresponding to each bit, which correspond to the latch circuit 17, and are composed of D flip-flops. Data input terminals of each latch circuit LO to L7 are connected to data lines DO to D7 of corresponding bits, and the G input is commonly connected to a control line ω for all bits. Therefore, these latch circuits LO to L7 transfer the levels of the data lines DO to D7 to the output terminal Q as the level of the control line ω rises.
The inverted level is also generated at the output terminal Q, and new data is latched every time an erase/write control pulse is generated on the control line ω.

CO to C7 are program circuits corresponding to each bit, and a program pulse of voltage VpI) is supplied to the program circuit CD-C7 through the source and drain of the transistor TrGP in series. WO to W7 are rewriting processing units for each program circuit CO to C7, and EO to E7.
is the same erasure processing section.

The rewriting processing units WO to W7 each have a corresponding latch circuit LO.
The output level of the output terminal Q of (LL/.../L7) is “
When the distance is 1 m, the cell transistor MO (Ml/...7M7
) is supplied with its program voltage VpI) to the drain of
Output terminal Q of the same latch circuit LO (LL/.../L7)
GND (ground) when the output level is “0”
level voltage of cell transistor MO (Ml/...7
M7). The erasing processing units EO to E7 apply the signal to the gate of the cell transistor MO (M1/...7M7) when the output level of the output terminal Q of the corresponding latch circuit LO (LL/.../L7) is "1 degree". The program voltage Vpp is supplied, and the same latch circuit LO (Ll/...
When the output level of the output terminal Q of the cell transistor MO (Ml/...7M7) is "O", a voltage at the GND (ground) level is supplied to the gate of the cell transistor MO (Ml/...7M7).

Therefore, the latch circuit LD (Ll/.../L7) is "1".
”, the rewrite processing unit WO (W
l/.../W7) to each transistor MO (Ml/.../W7)
A program pulse is supplied to the drain of .

In addition, the latch circuit LO (Ll/.../L7) is "0"
, the erasure processing unit EO (El/
.../E7) to each transistor M0 (M1/...
A program pulse is supplied to the gate of 7M7), a voltage Vpp is applied to the gate, and a level "0" is written due to electron accumulation at the floating gate.

LTSLW is a latch circuit for controlling read/erase/write operations, OR is an OR gate, and IVIIV2 is an inverter gate.

The latch circuit LW is composed of a D-flip flop, and a voltage Vcc of level "1" is input to its input terminal, and a control line ω is connected to its input terminal G. Therefore, when the level of the reset input terminal R of this latch circuit LW is 02, the level of the control line ω falls (fall of the pulse serving as the erase/write control command).
In response to this, the level of the input terminal is generated at the output terminal Q.

The latch circuit LT is a D flip-flop with a counting function. An output terminal Q of a latch circuit LW is connected to its input terminal. A clock pulse signal from the timer 19 is also input to the count clock input terminal CLK. The rising and falling cycles of this clock pulse signal are the time required to program the transistors MO to M7, for example, several tens of rnsec.

The latch circuit LT is designed to perform a counting operation at both the rising and falling edges of this clock pulse signal, and when two edges are counted after starting this counting operation, the level at the input terminal is changed to the output terminal Q. occurs in This output terminal Q is connected to the reset terminal R of the latch circuit LW. The output terminal Q of the latch circuit LW is connected to the reset terminal R of the latch circuit LT via a series circuit of an inverter gate IVI and an OR gate OR, and the control line ω is connected via the OR gate OR.

Here, it is assumed that the control line ω maintains the level "0".

When starting up the circuit, first, if the level of the output terminal Q of the latch circuit LW is "0", the latch circuit LW goes to its reset terminal R as long as the level of the control line ω maintains "0". regardless of the input level of the latch circuit (that is, the latch circuit L
Regardless of the operation of T), the output of output terminal Q will never become "1".

Furthermore, when the circuit is started up, if the level of the output terminal Q of the latch circuit LW is "1", the latch circuit LT enters a state where counting operation is permitted, so the count value becomes "2". When this happens, the level of the output terminal Q rises. Then, in response to this, the latch circuit LW is reset, and the level of its output terminal Q becomes "0", and similarly to the above, as long as the level of the control line ω maintains "0", the latch circuit LW is reset. Regardless of the input level to the terminal R (that is, regardless of the operation of the latch circuit LT), the output of the output terminal Q will never become "1".

Therefore, as long as the control line ω maintains the level "0", the level of the output terminal Q of the latch circuit LW is "0°".
It becomes stable in the state of .

Next, assume that an erase/write control pulse is generated on the control line ω in this state.

Then, first, due to the falling edge, the latch circuit LW
The level of the output terminal Q of the launch circuit LT becomes "1", thereby canceling the counting inhibited state of the launch circuit LT and starting its counting operation.

Eventually, when this latch circuit LT counts two edges of the timer clock pulse, the level of its output terminal Q rises, the latch circuit LW is reset, and the level of its output terminal Q falls.

Therefore, when an erase/write control pulse is generated on the control line ω, a pulse having a time width of level “1” corresponding to the counting operation time of the latch circuit LT is generated from the output terminal Q of the latch circuit LW. . At this time, the count operation time of the latch circuit LT is shorter as the edge generation timing of the clock pulse from the timer 19 after the fall of the erase/write control pulse is closer to the fall of the erase/write control pulse. The farther the timer clock pulse is, the longer it becomes the value between half cycles of the timer clock pulse. Therefore, the pulse time width generated from the latch circuit LW has a value in a range larger than a half cycle of the timer clock pulse and smaller than one cycle.

Furthermore, if a new erase/write control pulse is generated on the control line ω while the latch circuit LT is in the counting operation, the rising edge of the pulse resets the counting operation of the latch circuit LT (initializes the count value). Since the counting operation starts again from the beginning, the number 1 required for one erase/write operation is output from the output terminal Q of the latch circuit LW.
A new pulse having a time width of 0 Se is output.

The pulse from this latch circuit LW is the transistor T r
This transistor TrGP is turned on only during the pulse generation period, and the voltage Vpp is supplied to the program circuits CO to C7. Therefore, the pulse from the latch circuit LW is supposed to control the erase/write time in the program circuits CO to C7.

That is, when an erase/write control pulse is generated on the control line ω, a pulse having a time width of level “1” corresponding to the counting operation time of the latch circuit LT is generated from the output terminal Q of the latch circuit LW. Therefore, erasing/writing is performed in a sufficient period of time, which is longer than half the period of the timer clock pulse, where the edge appearance period is several tens of milliseconds.

Also, when the latch circuit LT is in the counting operation, the control line ω
When a new erase/write control pulse is generated, the rising edge of the pulse resets the counting operation of the latch circuit LT (initializes the count value), restarts the counting operation from the beginning, and then resets the counting operation of the latch circuit LT. From the output terminal Q of the
Since a new pulse having a time width of c is output, data newly held in the latch circuits LO to L7 is written, and a sufficient writing time is secured.

Trol~Tr71, Tr02~Tr72, Tr
03 to Tr73 are read control transistors corresponding to each bit, respectively.

The drains of the cell transistors MO to M7 are connected to the data lines DO to D7 through the source-drain series circuit of the transistors Tr03 to Tr73 and the source-drain of the transistors Tr01 to Tr71.

The output terminal Q of the latch circuits LO to L7 is connected to the transistor T
It is connected to the data line Do-D7 through a series circuit of sources and drains of transistors r02 to Tr72 and sources and drains of transistors Tr01 to Tr71.

When a read control pulse is generated on the control line r, the transistors Tr01 to Tr71 are turned on for only that period.
The transistors T r02 to Tr72 are turned on when the level of the output terminal Q of the latch circuit LW is "1" (during erase/write operation), and the transistors T r03 to T
In r73, the level of the output terminal Q of the latch circuit LW is “0”
Turns on when (not during erase/write operation).

Therefore, if a read command occurs while erasing/writing is not being performed, the transistor TrO]
By turning on ~Tr71, Tr03~Tr73 and turning off transistors Tr02~Tr72, data of transistors MO~M7 is sent to data lines DO~D7. Furthermore, if a read command occurs while erasing/writing is being performed, transistors Tr01 to
By turning on Tr71, Tr02-Tr72 and turning off transistors Tr03-Tr73, the latch circuit L is turned on.
Data from O to L7 will be sent to data lines DO to D7.

〔Effect of the invention〕

As explained above, according to the present invention, the command received by the erase/write command receiving means is processed by the execution means provided corresponding to each address, and the write data is held in the latch means corresponding to each address. Since the instruction execution means executes erasing/writing using the data held in the latch means as write data, this instruction is not sent to the instruction receiving means or data transmission path, which is a common unit for all addresses. Regardless, since the latch means and erase/write execution means are separate units for each address, the command receiving means and data transmission path, which are common hardware for all addresses, are used for erasing/writing.
It is governed by the write command, and the command can only be accepted at certain times, and it can be released at the time of erasing/writing.
Subsequent commands can then be accepted.

According to the present invention as set forth in claim 2, when a read command is received and an erase/write operation is being executed at that address, the data in the latch means is set as read data;
Since the read data sending means is provided to read the data in the storage section and send it to the data transmission path as read data when the above erase/write operation is not being executed, even if the address to be read is being erased/written, the address can be read. Can be accessed.

According to the third aspect of the present invention, when an address that is currently being erased/written receives a new erase/write command, the counting operation of the control counting means that controls the erase/write operation time is reset; Since new data is written again from the beginning, even if the address to be erased/written is being erased/written, the address can be accessed for erasing/writing.

(reset means), OR...OR gate (reset means).

[Brief explanation of drawings]

FIG. 1 is a block diagram of an EEF ROM according to an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of each address, and FIG. 3 is a block diagram of a conventional EEF ROM.

Claims (1)

[Scope of Claims] 1. A semiconductor memory device comprising a storage section consisting of electrically erasable/rewritable nonvolatile memory cells, which accepts an erase/write command and erases/writes to a specified address. Erase/write command receiving means for outputting an operation command; latch means provided corresponding to each address for latching data on a data transmission path in response to the erase/write operation command; erase/write command execution means for executing an erase/write operation for a predetermined time on the storage section by using the data of the latch means as write data in response to the erase/write operation command; Device. 2. A read command receiving means that receives a read command and outputs a read operation command to the specified address; and a read command receiving means that is provided corresponding to each address and that responds to the read operation command while executing an erase/write operation. Claim 1 further comprising read data sending means for making the data of the latch means read data when the erase/write operation is in progress, and sending the data of the storage section as the read data to the data transmission line when the erase/write operation is not being executed. The semiconductor storage device described above. 3. Control counting means that performs a counting operation for a predetermined period of time in response to an erase/write operation command, and executes an erase/write operation on the storage section using the data of the latch means as write data only during the counting operation of the control counting means. A claim comprising: erasure/write execution means; and reset means for resetting the counting operation of the control counting means when the control counting means is in counting operation and receives the erasure/writing operation command. A semiconductor memory device according to any one of claims 1 and 2.