JPS63140494A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate the possibility of erroneous writing in an external writing cycle and an internal writing cycle by providing a decoder Y control circuit which controls a decoder Y so that a write enable signal can be activated in the active external writing cycle and can be inactive in the internal writing cycle. CONSTITUTION:When a signal WE comes to 'L', a timer is activated, and the operation enters the external writing cycle. Only while the signal WE is at 'L', an output from a NAND gate 20a becomes 'H'. During that period a signal R/B is 'H', and hence a NAND gate 21a outputs 'L' to activate the decoder Y. Only an object gate line Y becomes 'H' to prevent the erroneous writing. When the operation enters the internal writing cycle, the signal R/B becomes 'L', the decoder Y becomes inactive to lead all gate lines Y to 'L'. Thus writing to an erroneous address, which depends on an address Y buffer, can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device (EEFROM), and particularly relates to an improvement in its programming means.

[Conventional technology]

To write to EEPROM memory cells, a high voltage pulse of 15 to 20V (VPP pulse) is applied inside the chip.
By generating this V□ pulse and applying it to the control gate or drain of the memory transistor, electrons are injected into the floating gate or erased from the floating gate. When a VPP pulse is applied to the control gate and electrons are injected into the floating gate, the threshold value of the memory transistor is shifted to a higher side.

This operation is called erasing, and information "1" is stored. When a vpp pulse is applied to the drain and electrons are removed from the floating gate, the threshold value of the memory transistor is shifted lower. This operation is called a program, and information "0" is stored.

Since the control gates of the memory transistors of 1-byte memory cells are commonly connected, erasing is performed first, and after "1" is written to all bits, the information "O'
Perform a program operation on the bit to be written. ■□The width of the pulse is usually 1 millisecond to several milliseconds, so 1
It takes about 10 milliseconds to write data to a byte, so it takes a very long time to write data to the entire chip. Therefore, highly integrated EEFROMs with 64 bits or more are provided with a page mode function in which multiple bytes on the same word line are written at once.

A simple flow diagram of this page mode write cycle is shown in FIG.

In page mode writing, the write cycle is divided into an external write cycle CYI and an internal write cycle CY2.

The external write cycle CYI is a cycle for writing data into the device from the outside, and performs addressing and inputting data in a manner similar to writing to static RAM. However, in this cycle, the input data is not written directly to the memory cell, but rather to each bit line.
It is once taken into a launch (column latch) provided on the control gate line. The duration of this cycle is controlled by timer T.

When the external write cycle ends, the process automatically moves to the internal write cycle. In this cycle CY2, a high voltage pulse is generated inside the memory device using a charge pump circuit, etc., and the bit line and control gate line are boosted to high voltage based on the data latched in the column latch, and the memory cell is Erasing and programming are performed. First, the deletion is 1
This is done for the byte of the page that you want to rewrite, and then “
The bits to be written with 0'' are programmed.

A conventional example of a column latch is shown in FIG. 4, and its timing chart is shown in FIG. The bit line column launch (built into the high voltage switch that boosts the bit line) 20 is
1st to 4th MOS) transistors 1 to 4, 1st. It is composed of second capacitors C1 and C2. The column ruff 3'0 of the control gate line (hereinafter referred to as CG line) is
1st to 4th MOS) transistors 5 to 8, 1st to 4th MOS) It is composed of second capacitors C3 and C4. column latch 20
．． 30 and bit line 16. Transfer gates 9 and 10 are provided between the control gate lines 17, and a clock φ is connected to their gates.

Note that 40 is an X decoder, 50 is a Y decoder, 70 is a memory cell 11 consisting of a memory cell transistor 71 and a transfer gate 72, which is a CG line, 12 is I10&i, 1
34:! Y gate) lines 14 and 15°61 are transfer gates.

Next, the specific operation of the conventional column latch will be explained with reference to FIGS. 4 and 5. At power-on and at the end of a write cycle, a first reset signal a is applied to the gate of transistor 4, and a second reset signal a is applied to the gate of transistor 8.

Transistors 4 and 8 are rendered conductive in response to reset signals a and b, respectively, the charges stored in capacitors C2 and C4 are discharged, and the column latch is reset.

When the external write cycle starts, the CG line 11 is kept at the 'H' level as shown in FIG. ,
Changes to “H”. In FIG. 5, "0" is input as input data, and the I10 line 12 is "
For a combination of Y addresses, one Y gate line 13 becomes H" as shown in Figure 5g, and Y gates 14 and 15 are respectively conductive. do. As a result, l10vA12 and the bit line 16 of the selected byte are connected, and the CG line 11
and control gate line 17 are connected.

Control game) vA17 as shown in Figure 5f,
becomes “H”, and the bit line 16 becomes “H” as shown in FIG. 5g.
When the input data is O, it becomes "H" level. During the external write cycle, the clock signal is held at the "H" level, as shown in Figure 5, so that transistors 9.
10 is conductive. As a result, the potential of each of the bit line 16 and control gate line 17 increases to a capacity 1tc2.
It is stored in °C4.

When the external write cycle ends, an erase cycle begins.

In the erase cycle, the high voltage V□ rises to 20V as shown in FIG. 5i, and the clock signal φ2 begins to oscillate as shown in FIG. 5j.

Further, the clock signal also rises to 20V, as shown in FIG. 5k.

The control gate line 17 of the selected byte is rendered conductive because the gate potential of the transistor 7 is "H", and the clock signal φ2 is applied to the source of the transistor 5 via the capacitor C3. As a result, the transistor 5.6 becomes conductive, and the control gate line 17 rises to a high voltage V□, as shown in FIG. 5m.

When the erase cycle is finished, the second reset signal
As shown in FIG. During this period, the control gate line 17 is connected to 'L' as shown in FIG.
″ level.

In the program cycle, as shown in FIG. 5P, the clock signal φ1 starts to oscillate, and the transistor 2 is also turned on via the capacitor ICI. As a result, the high voltage V□ rises as shown in FIG. 5q, and the clock signal also rises to a high voltage as shown in FIG. 5r. As a result, as shown in FIG. 5, the bit line 16 of the bit to which '0'' is to be written rises to a high voltage.
As shown in FIG. 2, the first reset signal becomes "H", the transistor 4 becomes conductive, the charge accumulated in the capacitor C2 is discharged, and the column latch is reset.

[Problem that the invention seeks to solve]

Conventional non-volatile semiconductor memory devices are configured as described above, and when the Y gate opens, data is written to the column launch of that Y address, resulting in a timing shift or so-called skew in the address bit. If there was, there was a risk of writing errors. Furthermore, during the internal write cycle, the operation of the Y address buffer 1 is prohibited and the output of the Y address buffer becomes a certain predetermined value, so there is a risk of erroneous writing to this Y address.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a nonvolatile semiconductor memory device that is free from the possibility of erroneous writing during external write cycles and internal write cycles.

[Means for solving problems]

The nonvolatile semiconductor memory device according to the present invention activates the Y decoder in response to the WE multiplication signal during writing, and deactivates the Y decoder during the internal write cycle.

[Effect]

In this invention, the Y decoder has a WE multiplied signal “L”
During the internal write cycle, one Y gate line is set to "H" level according to the input address, and "L" is output to all Y gate lines during the internal write cycle, so errors caused by skinny address input during the external write cycle are avoided. During write and internal write cycles, erroneous writes to addresses determined by the inactive Y address buffer are prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a Y decoder (column decoder) circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
o, Yo, . . . Y, , Yd are output signals of the Y address buffer. In the figure, 60 is a Y decoder, and in the erroneous decoder, 18 is a NAND gate, 1
9 is an inverter.

Further, 70 is a Y decoder control circuit, and in the error circuit 70, 20a is a two-man NAND gate to which the timer output and WE multiplied signal are input, 21a is a predecode signal, and R/B
It is a three-man powered NAND gate into which signals and the output of the NAND gate 20a are input, and the NAND gate 21a
The output of is connected to the gate of a transistor 22 whose drain is connected to the Y gate line and to an inverter 23. Further, the output of the inverter 23 is connected to the source of the P-channel MOS transistor of the inverter 19.

The predecode signal is also a type of decoder output, and is a signal for selecting a block when the memory array is divided into a plurality of blocks. R/
The B (Ready/Busy) signal is a signal that is "L" during the internal write cycle, and the timer is for determining the period of the external write cycle.

FIG. 2 shows the timing of each clock and the potential of the Y gate. When the WE multiplication signal becomes "L", the timer is activated and an external write cycle begins. When the timer output becomes “H”, the NAND gate 20a is activated only during the period of the WE multiplication signal “L”.
The output becomes H1. During this period, the R/B/ signal is “H”, so the block is selected and the predecode signal is “H”.
When this happens, the NAND gate 21a outputs “L” and activates the Y decoder (the P channel MO3 of the inverter 19
) gives voltage to the source of the transistor).

That is, since the Y decoder is activated only during the period of the WE multiplication signal 1L, which has no risk of skew during the external write cycle, only one target Y gate line is activated.
When the internal write cycle starts, the R/100x signal becomes "L" and the output of the NAND gate 21a becomes "H", so the Y decoder becomes inactive and all Y gates Since the line becomes "L", writing to an incorrect address determined by the Y address buffer is prevented.

Note that as in another embodiment of the present invention shown in FIG.
A transfer gate 24° transistor 25 to which the signal is input may be provided, and the same effect as in the above embodiment can be obtained.

Note that the R/100 times signal or a signal output to an external pin may be used, but any signal that becomes "Ll" during the internal write cycle may be used.

〔Effect of the invention〕

As described above, according to the nonvolatile semiconductor memory device according to the present invention, in an external write cycle, Y
Since the decoder is activated and the Y decoder is deactivated during the internal write cycle, it is possible to obtain an EEPROM without the risk of erroneous writing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of the present invention,
FIG. 3 is a diagram showing a write cycle of an EEPROM, FIG. 4 is a diagram showing a conventional column latch, FIG. 5 is a timing diagram of the conventional example, and FIG. 6 is a diagram showing another embodiment of the present invention. FIG. In the figure, 60 is a Y decoder, 70 is a Y decoder control circuit, 18 is a NAND gate, 19 is an inverter, 20
a, 21a is a NAND gate, 22 is a transistor, 2
3 is an inverter, 24 is a transfer gate, and 25 is a transistor.

Claims (1)

[Claims] (1) In a page mode write nonvolatile semiconductor memory device in which a write cycle consists of an external write cycle and an internal write cycle, the write enable signal is activated during the active period of the external write cycle, and the internal write 1. A nonvolatile semiconductor memory device comprising a Y-decoder control circuit that controls a Y-decoder to be inactive during a cycle.